TW201826445A - Method of manufacturing a stacked chip - Google Patents
Method of manufacturing a stacked chip Download PDFInfo
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- TW201826445A TW201826445A TW106131129A TW106131129A TW201826445A TW 201826445 A TW201826445 A TW 201826445A TW 106131129 A TW106131129 A TW 106131129A TW 106131129 A TW106131129 A TW 106131129A TW 201826445 A TW201826445 A TW 201826445A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 235000012431 wafers Nutrition 0.000 claims description 199
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 24
- 238000005259 measurement Methods 0.000 description 14
- 238000003475 lamination Methods 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000002407 reforming Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052902 vermiculite Inorganic materials 0.000 description 3
- 235000019354 vermiculite Nutrition 0.000 description 3
- 239000010455 vermiculite Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Dicing (AREA)
Abstract
Description
[0001] 本發明係關於層疊複數晶片而構成的層疊晶片之製造方法。[0001] The present invention relates to a method for manufacturing a laminated wafer configured by laminating a plurality of wafers.
[0002] 為了實現半導體裝置之更小型化，高積體化，在厚度方向重疊複數半導體晶片而以貫通電極(TSV：Through Silicon Via)等連接之三次元安裝技術。在該技術中，為了抑制最終製造出的層疊晶片之厚度，使用以研削等方法變薄的半導體晶片。 [0003] 然而，當構成層疊晶片之半導體晶片之厚度具有偏差時，難以形成特定之厚度一致的層疊晶片。於是，提案有於以研削等之方法使成為半導體晶片之晶圓變薄之前，使表面側之樹脂層平坦化，抑制由於研削所引起的厚度偏差之方法(例如，參照專利文獻1)。 [先前技術文獻] [專利文獻] [0004] [專利文獻1]日本特開2008-182015號公報[0002] In order to achieve smaller size and higher integration of a semiconductor device, a three-dimensional mounting technology in which a plurality of semiconductor wafers are stacked in a thickness direction and connected with a through electrode (TSV: Through Silicon Via) or the like. In this technique, in order to suppress the thickness of a laminated wafer to be finally manufactured, a semiconductor wafer that is thinned by a method such as grinding is used. [0003] However, when the thickness of the semiconductor wafers constituting the laminated wafers varies, it is difficult to form a specific laminated wafer with a uniform thickness. Therefore, a method of flattening the resin layer on the surface side and suppressing the thickness variation due to grinding is proposed before the wafer to be a semiconductor wafer is thinned by grinding or the like (for example, refer to Patent Document 1). [Prior Art Document] [Patent Document] [0004] [Patent Document 1] Japanese Patent Laid-Open No. 2008-182015
[發明所欲解決之課題] [0005] 但是，在上述方法中，因需要準備與研削裝置不同的切刃切削用之切削裝置(切刃切削裝置)，故製造成本容易變高。再者，即使在該方法中，亦無法完全抑制厚度之偏差。 [0006] 本發明係鑒於如此之問題點而創作出，其目的在於提供可以製造特定厚度一致的層疊晶片之嶄新的層疊晶片之製造方法。 [用以解決課題之手段] [0007] 若藉由本發明之一態樣時，提供一種層疊晶片之製造方法，其係複數晶片被層疊之層疊晶片之製造方法，具備：晶片形成步驟，其係研削晶圓之背面而使晶圓變薄，將晶圓分割成複數晶片；測量步驟，其係測量在該晶片形成步驟所取得之各晶片之厚度；及晶片層疊步驟，其係以層疊複數晶片之時成為特定厚度之方式，根據在該測量步驟所測量出之各晶片之厚度，選擇應層疊之複數晶片而予以層疊。 [0008] 在本發明之一態樣中，在該晶片形成步驟中，沿著交叉之複數分割預定線而在晶圓形成分割用之構造之後，研削晶圓之背面，依此使晶圓變薄而分割成複數晶片即可。 [發明效果] [0009] 在與本發明之一態樣有關的層疊晶片之製造方法中，因以於層疊複數晶片之時，成為特定厚度之方式，根據各晶片之厚度，選擇應層疊之複數晶片而予以層疊，故可以製造出特定厚度一致的層疊晶片。[Problems to be Solved by the Invention] 000 [0005] However, in the above method, since a cutting device (a cutting device for cutting edge) for cutting with a cutting device different from the grinding device is required, the manufacturing cost tends to increase. Furthermore, even in this method, variations in thickness cannot be completely suppressed. [0006] The present invention has been made in view of such problems, and an object thereof is to provide a novel method for manufacturing a laminated wafer which can produce laminated wafers having a uniform thickness. [Means to Solve the Problem] [0007] According to one aspect of the present invention, a method for manufacturing a laminated wafer is provided, which is a method for manufacturing a laminated wafer in which a plurality of wafers are laminated, comprising: a wafer forming step, which is Grind the back side of the wafer to make the wafer thin and divide the wafer into multiple wafers; a measurement step that measures the thickness of each wafer obtained in the wafer formation step; and a wafer lamination step that laminates multiple wafers A method of forming a specific thickness at that time is based on the thickness of each wafer measured in this measurement step, and a plurality of wafers to be stacked are selected and stacked. [0008] In one aspect of the present invention, in the wafer forming step, a plurality of predetermined division lines are divided along the cross to form a structure for dividing the wafer, and then the back surface of the wafer is ground to change the wafer accordingly. It can be thin and divided into multiple wafers. [Effects of the Invention] [0009] In the method for manufacturing a laminated wafer related to one aspect of the present invention, since a plurality of wafers are laminated to a specific thickness, a plurality of wafers should be selected according to the thickness of each wafer. The wafers are laminated, so that a laminated wafer having a uniform thickness can be manufactured.
[0011] 參照附件圖面，針對與本發明之一態樣有關之實施型態進行說明。與本實施型態有關之層疊晶片之製造方法包含晶片形成步驟(參照圖2(A)、圖2(B)、圖3(A))、測量步驟(參照圖3(B))及晶片層疊步驟(參照圖4(A)、圖4(B))。 [0012] 晶片形成步驟，其係研削晶圓之背面而使晶圓變薄，再者，將晶圓分割成複數晶片。在測量步驟中，測量在晶片形成步驟所取得之各晶片之厚度。在晶片層疊步驟中，根據各晶片之厚度，選擇應層疊之複數晶片而予以層疊。以下，針對與本實施型態有關之層疊晶片之製造方法予以詳細敘述。 [0013] 圖1為示意性表示在本實施型態中所使用之晶圓之構成例的斜視圖。如圖1所示般，本實施型態之晶圓11使用矽(Si)等之半導體材料而形成圓盤狀。晶圓11之表面11a側以被配列成格子狀之分割預定線(切割道)13被區劃成複數區域，在各區域形成IC、LSI等之裝置15。 [0014] 另外，在本實施型態中，雖然使用矽等之半導體材料所構成之圓盤狀之晶圓11，但是晶圓11之材質、形狀、大小、構造等不受限制。例如，亦可以使用陶瓷、樹脂、金屬等之材料所構成之晶圓11。同樣，裝置15之種類、數量、大小、配置等也不受限制。 [0015] 與本實施型態有關之層疊晶片之製造方法中，首先，進行分割上述晶圓11而形成複數晶片之晶片形成步驟。圖2(A)係示意性表示在晶片形成步驟中，在晶圓之表面側形成分割用之溝(分割用之構造)之樣子的一部分剖面側面圖。分割用之溝使用例如圖2(A)所示之切削裝置2而被形成。 [0016] 切削裝置2具備吸引、保持晶圓11之挾盤載置台4。挾盤載置台4與馬達等之旋轉驅動源(無圖示)連結，在與垂直方向大概平行之旋轉軸之周圍旋轉。再者，在挾盤載置台4之下方，設置加工進給機構(無圖示)，挾盤載置台4係藉由該加工進給機構在加工進給方向(水平之第1方向)移動。 [0017] 挾盤載置台4之上面之一部分成為吸引、保持晶圓11之背面11b側之保持面4a。保持面4a通過被形成在挾盤載置台4之內部之吸引路(無圖示)等而被連接於吸引源(無圖示)。藉由使保持面4a作用吸引源之負壓，晶圓11被吸引、保持於挾盤載置台4。 [0018] 在挾盤載置台4之上方，配置有用以切削晶圓11之切削單元6。切削單元6具備成為與水平方向大概平行之旋轉軸的主軸8。在主軸8之一端側，安裝環狀之切削刀10。在主軸8之另一端側，連結馬達等之旋轉驅動源(無圖示)，被安裝於主軸8之切削刀10藉由從該旋轉驅動源傳遞的力而旋轉。 [0019] 切削單元6被支撐於升降機構(無圖示)及分度進給機構(無圖示)，藉由升降機構在垂直方向移動(升降)，藉由分度進給機構，在與加工進給方向成垂直之分度進給方向(水平的第2方向)移動。 [0020] 於使用該切削裝置2而形成分割用之溝之時，首先，使晶圓11之背面11b側接觸於挾盤載置台4之保持面4a，使吸引源之負壓作用。依此，晶圓11在表面11a側露出於上方之狀態下，被保持於挾盤載置台4。另外，即使在晶圓11之背面11b，事先黏貼切割膠帶等亦可。 [0021] 接著，使挾盤載置台4旋轉，使任意之分割預定線13與加工進給方向成平行。並且，使挾盤載置台4和切削單元6相對性移動，使切削刀10對準任意之分割預定線13之延長線上。之後，使旋轉之切削刀10之下端下降至較晶圓11之表面11a低且較背面11b高之位置，使挾盤載置台4在加工進給方向移動。 [0022] 依此，使切削刀10切入晶圓11，可以形成沿著對象之分割預定線13之分割用之溝(分割用之構造)17(半切割)。另外，上述動作係重複至沿著所有的分割預定線13而形成分割用之溝17為止。 [0023] 於形成分割用之溝17之後，研削背面11b使晶圓11變薄，分割成複數晶片。圖2(B)示意性表示在晶片形成步驟中，晶圓之背面被研削之樣子的一部分剖面側面圖。背面11b之研削使用例如圖2(B)所示之研削裝置22而進行。 [0024] 切削裝置22具備吸引、保持晶圓11之挾盤載置台24。挾盤載置台24與馬達等之旋轉驅動源(無圖示)連結，在與垂直方向大概平行之旋轉軸之周圍旋轉。再者，在挾盤載置台24之下方，設置有移動機構(無圖示)，挾盤載置台24藉由該移動機構在水平方向移動。 [0025] 挾盤載置台24之上面之一部分成為吸引、保持晶圓11之表面11a側之保持面24a。保持面24a通過被形成在挾盤載置台24之內部之吸引路(無圖示)等而被連接於吸引源(無圖示)。藉由使保持面24a作用吸引源之負壓，晶圓11被吸引、保持於挾盤載置台24。 [0026] 在挾盤載置台24之上方，配置有研削單元26。研削單元26具備被支撐於升降機構(無圖示)之主軸殼(無圖示)。在主軸殼收容主軸28，在主軸28之下端部，固定圓盤狀之支架30。 [0027] 在支架30之下面，安裝與支架30大概相同直徑之研削輪32。研削輪32具備不鏽鋼、鋁等之金屬材料所形成的輪基台34。輪基台34之下面，環狀地配列複數研削砥石36。 [0028] 在主軸28之上端側(基端側)，連結馬達等之旋轉驅動源(無圖示)，研削輪32藉由該旋轉驅動源傳遞之力，在與垂直方向大概平行的旋轉軸之附近旋轉。研削單元26之內部或附近，設置有用以對晶圓11等供給純水等之研削液之噴嘴(無圖示)。 [0029] 於使用該研削裝置22研削晶圓11之背面11b之前，在上述晶圓11之表面11a側黏貼保護構件。保護構件21係持有與晶圓11同等之直徑的圓形薄膜(膠帶)，在其表面21a側設置有具有黏接力之糊層。 [0030] 因此，若使該表面21a側密接於被加工物11之表面11a側時，可以在被加工物11之表面11a側黏貼保護構件21。藉由在被加工物11之表面11a側黏貼保護構件21，可以緩和於研削等之時施加的衝擊，保護被形成在晶圓11之表面11a側的裝置15等。另外，在晶圓11之背面11b黏貼切割膠帶等之情況，先除去該些。 [0031] 在晶圓11之表面11a側黏貼保護構件21之後，使被黏貼於晶圓11之保護構件21之背面21b接觸於挾盤載置台24之保持面24a，使作用吸引源之負壓。依此，晶圓11在背面11a側露出於上方之狀態下，被吸引、保持於挾盤載置台24。 [0032] 接著，使挾盤載置台24移動至研削單元26之下方。而且，如圖2(B)所示般，分別使挾盤載置台24和研削輪32旋轉，一面對晶圓11之背面11b等供給研削液，一面使主軸殼(主軸28、研削輪32)下降。 [0033] 主軸殼之下降速度(下降量)被調整成研削砥石36之下面被抵接於晶圓11之背面11b側之程度。依此，可以研削背面11b側而使晶圓11變薄。該研削係一面使用例如非接觸式之厚度測量器38(參照圖3(B))測量晶圓11之厚度，一面持續使晶圓11薄化至特定厚度(最終厚度)為止。另外，即使使用接觸式之厚度測量器取代非接觸式之厚度測量器38亦可。 [0034] 當晶圓11被薄化至特定厚度(最終厚度)時，在背面11b側，露出分割用之溝17，晶圓11係以該分割用之溝17為境界分割成複數晶片。圖3(A)示意性表示被分割成複數晶片之晶圓11之斜視圖。如圖3(A)所示般，於分割晶圓11取得複數晶片19之時，晶片形成步驟結束。 [0035] 在晶片形成步驟之後，進行用以測量各晶片19之厚度的測量步驟。圖3(B)示意性地表示在測量步驟中測量各晶片19之厚度之樣子的一部分剖面側面圖。該測量步驟接著使用研削裝置22而進行。 [0036] 如上述般，在挾盤載置台24之上方，配置利用光之非接觸式之厚度測量器38。厚度測量器38具備放射測量用之光的光源(無圖示)。該光源係例如SLD(超發光二極體)或LED、鹵素燈等，放射在透過晶圓11之特定之波長範圍持有強度分布之光。 [0037] 如上述般，因測量用之光穿透晶圓11，故被照射至晶圓11之測量用之光之一部分，在晶圓11之背面11b側被反射，另外，被照射至晶圓11之測量用之光之另外的一部分在晶圓11之表面11a側被反射。依此，在背面11b側被反射之光和在表面11a被反射之光的干涉光，以因應背面11b和表面11a之光路差(相當於晶圓11之厚度)等的複數波長互相加強。 [0038] 上述干涉光射入例如以被設置在厚度測量器38之內部的繞射光柵等之分光單元(無圖示)。在分光單元之附近，配置檢測出以分光單元被分光之光的強度分布的線感測器(無圖示)。與以線感測器取得之干涉光之強度分布有關之資訊，被送至例如厚度測量器38之控制單元(無圖示)。 [0039] 如上述般，以線感測器所取得之資訊，包含相當於以複數波長互相加強的干涉光之分光光譜的資訊。依此，藉由以例如控制單元，將線感測器所取得之資訊(干涉光之分光光譜)予以傅立葉轉換(以高速傅立葉為代表)等，可以取得與背面11b相對於表面11a之高度(即是，晶圓11之厚度)有關的資訊。 [0040] 於使用該厚度測量器38測量晶片19之厚度之時，例如，一面從厚度測量器38朝向晶圓11之背面11b照射測量用之光，一面使挾盤載置台24和厚度測量器38相對性移動。依此，對各晶片19照射測量用之光，可以測量其厚度。另外，即使使用接觸式之厚度測量器，和厚度測量器38之測量原理不同的非接觸式之厚度測量器等亦可。例如，當測量、記錄所有的晶片19之厚度時，測量步驟結束。 [0041] 於測量步驟之後，進行根據各晶片19之厚度，選擇應層疊之複數晶片19而予以層疊的晶片層疊步驟。圖4(A)為示意性地表示在晶圓層疊步驟中被選擇之複數晶片的側面圖，圖4(B)為示意性地表示在晶片層疊步驟中層疊複數晶片之樣子的側面圖。 [0042] 另外，在本實施型態中，雖然針對在厚度方向重疊3個晶片19a、19b、19c而製造層疊晶片31之情況予以說明，但是重疊之晶片19的數量並不受限制。即是，即使重疊2個晶片19而製造層疊晶片亦可，即使重疊4個以上之晶片19而製造層疊晶片亦可。 [0043] 例如，在將層疊晶片31之厚度設定成T之情況下，根據在測量步驟測量、記錄之各晶片19之厚度，如圖4(A)所示般，選擇各個的厚度t1、t2、t3之和成為T之3個晶片19a、19b、19c。藉由重疊該些3個晶片19a、19b、19c而予以固定，可以如圖4(B)所示般，製造厚度為T之層疊晶片31。 [0044] 另外，在本實施型態中，雖然針對僅考慮晶片19a、19b、19c之厚度的例予以說明，但是在層疊晶片包含晶片以外之構成要素(例如，連接各晶片之黏接劑等)之情況下，考慮其構成要素之厚度後，選擇應層疊的複數晶片。 [0045] 如上述般，在與本實施型態有關的層疊晶片之製造方法中，因以於層疊複數晶片19之時，成為特定厚度T之方式，根據各晶片19之厚度，選擇應層疊之複數晶片19a、19b、19c而予以層疊，故可以製造出特定厚度T一致的層疊晶片31。 [0046] 另外，本發明並不限定於上述實施型態之記載，能夠做各種變更而加以實施。例如，在上述實施型態之晶片形成步驟中，雖然在晶圓11之表面11a側形成分割用之溝17，之後，研削晶圓11之背面11b，依此使晶圓11變薄，同時分割成複數晶片19，但是即使使用其他方法，將晶圓分割成複數晶片亦可。 [0047] 例如，使具有穿透性之雷射束聚光於晶圓之內部，形成成為分割之起點的改質層(分割用之構造)，之後，研削晶圓之背面，依此使晶圓變薄，同時利用研削之時施加的力而可以將晶圓分割成複數晶片。 [0048] 同樣，即使使具有穿透性之雷射束聚光於晶圓之內部，形成成為分割之起點的改質層，之後，以研削以外之方法賦予力而將晶圓分割成複數晶片亦可。在此情況下，亦可以於形成成為分割之起點之改質層之前，研削晶圓之背面而使晶圓變薄。 [0049] 再者，即使使用具有吸收性之雷射束或切削刀而切斷晶圓，分割成複數晶片亦可。另外，在此情況下，於切斷晶圓而分割成複數晶片之前，即使研削晶圓之背面而使晶圓變薄亦可。 [0050] 其他，與上述實施型態有關之構造、方法等只要不脫離本發明之目的的範圍，可以做適當變更而加以實施。[0011] With reference to the attached drawings, an implementation mode related to one aspect of the present invention will be described. A method for manufacturing a laminated wafer related to this embodiment mode includes a wafer formation step (refer to FIG. 2 (A), FIG. 2 (B), FIG. 3 (A)), a measurement step (refer to FIG. 3 (B)), and wafer lamination. Steps (refer to FIGS. 4 (A) and 4 (B)). [0012] A wafer forming step involves grinding the back surface of a wafer to make the wafer thinner, and dividing the wafer into a plurality of wafers. In the measuring step, the thickness of each wafer obtained in the wafer forming step is measured. In the wafer lamination step, a plurality of wafers to be laminated are selected and laminated according to the thickness of each wafer. Hereinafter, a method for manufacturing a laminated wafer related to this embodiment mode will be described in detail. [0013] FIG. 1 is a perspective view schematically showing a configuration example of a wafer used in this embodiment. As shown in FIG. 1, the wafer 11 of this embodiment is formed into a disc shape using a semiconductor material such as silicon (Si). The surface 11a side of the wafer 11 is divided into a plurality of regions by predetermined division lines (cut lines) 13 arranged in a grid pattern, and devices 15 such as ICs and LSIs are formed in each region. [0014] In addition, in this embodiment, although a disc-shaped wafer 11 made of a semiconductor material such as silicon is used, the material, shape, size, and structure of the wafer 11 are not limited. For example, a wafer 11 made of a material such as ceramic, resin, or metal may be used. Similarly, the type, number, size, arrangement, etc. of the devices 15 are not limited. [0015] In the method for manufacturing a laminated wafer related to this embodiment mode, first, a wafer forming step of dividing the above-mentioned wafer 11 to form a plurality of wafers is performed. FIG. 2 (A) is a partial cross-sectional side view schematically showing a state in which a groove for division (a structure for division) is formed on the surface side of the wafer in the wafer forming step. The dividing groove is formed using, for example, the cutting device 2 shown in FIG. 2 (A). [0016] The cutting device 2 includes a disk mounting table 4 that sucks and holds the wafer 11. The disk mounting table 4 is connected to a rotation drive source (not shown) such as a motor, and rotates around a rotation axis that is approximately parallel to the vertical direction. In addition, a processing feed mechanism (not shown) is provided below the disk mounting table 4, and the disk mounting table 4 is moved in the processing feed direction (the first horizontal direction) by the processing feed mechanism. [0017] A part of the upper surface of the disk mounting table 4 is a holding surface 4a that attracts and holds the back surface 11b side of the wafer 11. The holding surface 4a is connected to a suction source (not shown) through a suction path (not shown) or the like formed inside the disk mounting table 4. When the negative pressure of the suction source is applied to the holding surface 4a, the wafer 11 is sucked and held on the disk mounting table 4. [0018] Above the disk mounting table 4, a cutting unit 6 for cutting the wafer 11 is arranged. The cutting unit 6 includes a main shaft 8 serving as a rotation axis substantially parallel to the horizontal direction. An annular cutting blade 10 is attached to one end of the main shaft 8. A rotary driving source (not shown) such as a motor is connected to the other end side of the spindle 8, and the cutting blade 10 mounted on the spindle 8 is rotated by a force transmitted from the rotary driving source. [0019] The cutting unit 6 is supported by a lifting mechanism (not shown) and an indexing feeding mechanism (not shown). The cutting unit 6 is moved (elevated) in the vertical direction by the lifting mechanism, and the indexing feeding mechanism The machining feed direction moves in the vertical index feed direction (the second horizontal direction). [0020] When using the cutting device 2 to form a ditch for division, first, the back surface 11b side of the wafer 11 is brought into contact with the holding surface 4a of the pan mounting table 4 to apply a negative pressure from a suction source. As a result, the wafer 11 is held on the disk mounting table 4 in a state where the surface 11 a side is exposed upward. In addition, a dicing tape or the like may be pasted on the back surface 11b of the wafer 11 in advance. [0021] Next, the pan tray mounting table 4 is rotated so that an arbitrary dividing plan line 13 is parallel to the processing feed direction. Then, the disk mounting table 4 and the cutting unit 6 are relatively moved, and the cutting blade 10 is aligned with an extension line of an arbitrary predetermined division line 13. After that, the lower end of the rotating cutter 10 is lowered to a position lower than the surface 11a of the wafer 11 and higher than the back surface 11b, so that the disk mounting table 4 is moved in the processing feed direction. [0022] According to this, the cutting blade 10 is cut into the wafer 11 to form a dividing groove (a structure for dividing) 17 (half cutting) along the target dividing line 13. In addition, the above-mentioned operation is repeated until the division grooves 17 are formed along all the division-planned lines 13. [0023] After forming the grooves 17 for division, the back surface 11b is ground to thin the wafer 11 and divided into a plurality of wafers. FIG. 2 (B) is a partial cross-sectional side view schematically showing how the back surface of the wafer is ground in the wafer forming step. The grinding of the back surface 11b is performed using, for example, a grinding device 22 shown in FIG. 2 (B). [0024] The cutting device 22 includes a disk mounting table 24 that sucks and holds the wafer 11. The disk mounting table 24 is connected to a rotation drive source (not shown) such as a motor, and rotates around a rotation axis that is approximately parallel to the vertical direction. Further, a moving mechanism (not shown) is provided below the disk mounting table 24, and the disk mounting table 24 moves in the horizontal direction by the moving mechanism. [0025] A part of the upper surface of the disk mounting table 24 is a holding surface 24a that attracts and holds the surface 11a side of the wafer 11. The holding surface 24a is connected to a suction source (not shown) via a suction path (not shown) or the like formed inside the disk mounting table 24. When the negative pressure of the suction source is applied to the holding surface 24a, the wafer 11 is sucked and held on the disk mounting table 24. [0026] Above the disk mounting table 24, a grinding unit 26 is arranged. The grinding unit 26 includes a spindle housing (not shown) supported by a lifting mechanism (not shown). The spindle housing 28 is housed in the spindle housing, and a disc-shaped bracket 30 is fixed to the lower end of the spindle 28. [0027] Under the bracket 30, a grinding wheel 32 having a diameter approximately the same as that of the bracket 30 is mounted. The grinding wheel 32 includes a wheel base 34 formed of a metallic material such as stainless steel or aluminum. A plurality of ground vermiculite 36 are arranged in a ring shape below the wheel base 34. [0028] A rotary drive source (not shown) such as a motor is connected to the upper end side (base end side) of the main shaft 28, and the grinding wheel 32 is rotated by a force transmitted by the rotary drive source in a direction approximately parallel to the vertical axis. Rotate around it. Inside or near the grinding unit 26, a nozzle (not shown) for supplying a grinding liquid such as pure water to the wafer 11 or the like is provided. [0029] Before using the grinding device 22 to grind the back surface 11b of the wafer 11, a protective member is adhered to the surface 11a side of the wafer 11. The protective member 21 holds a circular film (tape) having the same diameter as that of the wafer 11, and a paste layer having an adhesive force is provided on the surface 21a side. [0030] Therefore, if the surface 21a side is brought into close contact with the surface 11a side of the workpiece 11, the protective member 21 can be adhered to the surface 11a side of the workpiece 11. By adhering the protective member 21 to the surface 11a side of the workpiece 11, the impact applied during grinding or the like can be reduced, and the device 15 and the like formed on the surface 11a side of the wafer 11 can be protected. When a dicing tape or the like is stuck on the back surface 11b of the wafer 11, these are removed first. [0031] After the protective member 21 is adhered to the surface 11a side of the wafer 11, the back surface 21b of the protective member 21 adhered to the wafer 11 is brought into contact with the holding surface 24a of the pan mounting table 24, so that the negative pressure of the attraction source is applied. . As a result, the wafer 11 is sucked and held on the disk mounting table 24 in a state where the back surface 11 a side is exposed upward. [0032] Next, the pan tray mounting table 24 is moved below the grinding unit 26. Then, as shown in FIG. 2 (B), the chuck mounting table 24 and the grinding wheel 32 are rotated, while the grinding liquid is supplied while facing the back surface 11b of the wafer 11, etc., and the spindle housing (spindle 28, grinding wheel 32) is supplied. )decline. [0033] The descending speed (amount of descending) of the spindle housing is adjusted to such an extent that the lower surface of the grinding vermiculite 36 is abutted on the back surface 11b side of the wafer 11. Accordingly, the wafer 11 can be thinned by grinding the back surface 11b side. This grinding system uses, for example, a non-contact thickness measuring device 38 (see FIG. 3 (B)) to measure the thickness of the wafer 11 while continuously thinning the wafer 11 to a specific thickness (final thickness). In addition, a contact-type thickness measuring device may be used instead of the non-contact-type thickness measuring device 38. [0034] When the wafer 11 is thinned to a specific thickness (final thickness), a groove 17 for division is exposed on the back surface 11b side, and the wafer 11 is divided into a plurality of wafers using the groove 17 for division as a boundary. FIG. 3 (A) is a perspective view schematically showing a wafer 11 divided into a plurality of wafers. As shown in FIG. 3 (A), when the plurality of wafers 19 are obtained by dividing the wafers 11, the wafer forming step is ended. [0035] After the wafer formation step, a measurement step for measuring the thickness of each wafer 19 is performed. FIG. 3 (B) is a partial cross-sectional side view schematically showing how the thickness of each wafer 19 is measured in the measurement step. This measurement step is then performed using the grinding device 22. [0036] As described above, a non-contact type thickness measuring device 38 using light is arranged above the disk mounting table 24. The thickness measuring device 38 includes a light source (not shown) that emits light for measurement. The light source is, for example, an SLD (Super Light Emitting Diode), an LED, or a halogen lamp, and emits light having an intensity distribution in a specific wavelength range transmitted through the wafer 11. [0037] As described above, since the measurement light penetrates the wafer 11, a part of the measurement light irradiated to the wafer 11 is reflected on the back surface 11b side of the wafer 11 and is irradiated to the crystal. The other part of the light for measuring the circle 11 is reflected on the surface 11 a side of the wafer 11. According to this, the interference light of the light reflected on the back surface 11b side and the light reflected on the surface 11a is mutually strengthened by a plurality of wavelengths in accordance with the optical path difference (equivalent to the thickness of the wafer 11) of the back surface 11b and the surface 11a. [0038] The interference light is incident on a spectroscopic unit (not shown), such as a diffraction grating provided inside the thickness measuring device 38. A line sensor (not shown) is disposed near the spectroscopic unit and detects the intensity distribution of the light split by the spectroscopic unit. Information related to the intensity distribution of the interference light obtained by the line sensor is sent to a control unit (not shown) of the thickness measuring device 38, for example. [0039] As described above, the information obtained by the line sensor includes information equivalent to the spectral spectrum of interference light that is mutually reinforced by a plurality of wavelengths. According to this, for example, the information obtained by the line sensor (spectral spectrum of interference light) is Fourier-transformed (represented by high-speed Fourier) by the control unit, for example, to obtain the height of the back surface 11b relative to the surface 11a ( That is, information about the thickness of the wafer 11). [0040] When the thickness of the wafer 19 is measured using the thickness measuring device 38, for example, while the measuring light is radiated from the thickness measuring device 38 toward the back surface 11b of the wafer 11, the pan mounting table 24 and the thickness measuring device 38 Relative movement. According to this, each wafer 19 is irradiated with measurement light, and its thickness can be measured. In addition, a contact-type thickness measuring device or a non-contact type thickness measuring device having a different measuring principle from the thickness measuring device 38 may be used. For example, when the thickness of all the wafers 19 is measured and recorded, the measurement step ends. [0041] After the measurement step, a wafer lamination step is performed in which a plurality of wafers 19 to be laminated are selected and laminated according to the thickness of each wafer 19. FIG. 4 (A) is a side view schematically showing a plurality of wafers selected in the wafer lamination step, and FIG. 4 (B) is a side view schematically showing a state in which a plurality of wafers are laminated in the wafer lamination step. [0042] In addition, in this embodiment mode, although the case where three wafers 19a, 19b, and 19c are stacked in the thickness direction to manufacture the laminated wafer 31 is described, the number of the stacked wafers 19 is not limited. That is, even if two wafers 19 are stacked to produce a laminated wafer, even if four or more wafers 19 are stacked to produce a laminated wafer. [0043] For example, when the thickness of the laminated wafer 31 is set to T, according to the thickness of each wafer 19 measured and recorded in the measurement step, as shown in FIG. 4 (A), each thickness t1, t2 is selected. The sum of T3 and T3 becomes the T wafers 19a, 19b, and 19c. By stacking and fixing the three wafers 19a, 19b, and 19c, as shown in FIG. 4 (B), a laminated wafer 31 having a thickness of T can be manufactured. [0044] In this embodiment, an example in which only the thicknesses of the wafers 19a, 19b, and 19c are considered is described. However, the laminated wafer includes components other than the wafers (for example, an adhesive to connect the wafers, etc.) In the case of), considering the thickness of the constituent elements, a plurality of wafers to be stacked are selected. [0045] As described above, in the method for manufacturing a laminated wafer related to this embodiment mode, since a certain thickness T is used when a plurality of wafers 19 are laminated, the thickness of each wafer 19 is selected to be laminated. Since the plurality of wafers 19a, 19b, and 19c are stacked, a stacked wafer 31 having a uniform specific thickness T can be manufactured. [0046] In addition, the present invention is not limited to the description of the above-mentioned embodiment, and can be implemented with various changes. For example, in the wafer forming step of the above embodiment, although the grooves 17 for division are formed on the surface 11a side of the wafer 11, the back surface 11b of the wafer 11 is ground, and the wafer 11 is thereby thinned and divided simultaneously Although the plurality of wafers 19 are used, the wafer may be divided into a plurality of wafers even if other methods are used. [0047] For example, a penetrating laser beam is condensed inside the wafer to form a reforming layer (structure for division) which is the starting point of division. After that, the back surface of the wafer is ground, and the crystal is formed accordingly. The circle becomes thin, and the wafer can be divided into a plurality of wafers by using a force applied during grinding. [0048] Similarly, even if a penetrating laser beam is condensed inside the wafer to form a reforming layer which is the starting point of division, the wafer is divided into a plurality of wafers by applying force other than grinding. Yes. In this case, the wafer may be thinned by grinding the back surface of the wafer before forming the reforming layer which is the starting point of division. [0049] Furthermore, even if the wafer is cut by using an absorptive laser beam or a cutter, the wafer may be divided into a plurality of wafers. In this case, the wafer may be thinned by grinding the back surface of the wafer before cutting the wafer and dividing it into a plurality of wafers. [0050] In addition, as long as the structure, method, and the like related to the above-mentioned embodiment are not deviated from the scope of the object of the present invention, they can be appropriately modified and implemented.
[0051][0051]
11‧‧‧晶圓11‧‧‧ wafer
11a‧‧‧表面11a‧‧‧ surface
11b‧‧‧背面11b‧‧‧Back
13‧‧‧分割預定線(縫隙)13‧‧‧ divided scheduled line (gap)
15‧‧‧裝置15‧‧‧ device
17‧‧‧分割用之溝(分割用之構造)17‧‧‧Gutter for division (structure for division)
19、19a、19b、19c‧‧‧晶片19, 19a, 19b, 19c
21‧‧‧保護構件21‧‧‧Protective member
21a‧‧‧表面21a‧‧‧ surface
21b‧‧‧背面21b‧‧‧Back
31‧‧‧層疊晶片31‧‧‧Laminated Wafer
2‧‧‧切削裝置2‧‧‧ cutting device
4‧‧‧挾盤載置台4‧‧‧ pan tray mounting table
4a‧‧‧保持面4a‧‧‧ keep face
6‧‧‧切削單元6‧‧‧ cutting unit
8‧‧‧主軸8‧‧‧ Spindle
10‧‧‧切削刀10‧‧‧ Cutter
22‧‧‧切削裝置22‧‧‧ cutting device
24‧‧‧挾盤載置台24‧‧‧ Pan loading platform
24a‧‧‧保持面24a‧‧‧ keep face
26‧‧‧研削單元26‧‧‧grinding unit
28‧‧‧主軸28‧‧‧ Spindle
30‧‧‧支架30‧‧‧ Bracket
32‧‧‧研削輪32‧‧‧grinding wheel
34‧‧‧輪基台34‧‧‧ round abutment
36‧‧‧研削砥石36‧‧‧ Grinding Vermiculite
38‧‧‧厚度測量器38‧‧‧thickness measuring instrument
[0010] 圖1為示意性表示晶圓之構成例的斜視圖。 圖2(A)為示意性表示在晶片形成步驟中在晶圓之表面側形成分割用之溝之樣子的一部分剖面側面圖，圖2(B)為示意性地表示在晶片形成步驟中，晶圓之背面被研削之樣子的一部分剖面側面圖。 圖3(A)為示意性地表示分割成複數晶片之晶圓的斜視圖，圖3(B)為示意性地表示在測量步驟中測量各晶片之厚度之樣子的一部分剖面側面圖。 圖4(A)為示意性地表示在晶圓層疊步驟中被選擇之複數晶片的側面圖，圖4(B)為示意性地表示在晶片層疊步驟中層疊複數晶片之樣子的側面圖。[0010] FIG. 1 is a perspective view schematically showing a configuration example of a wafer. FIG. 2 (A) is a partial cross-sectional side view schematically showing a state in which a trench for division is formed on the surface side of a wafer in a wafer forming step, and FIG. 2 (B) is a schematic view showing a crystal in the wafer forming step. Partial cross-sectional side view of the rounded back surface. FIG. 3 (A) is a perspective view schematically showing a wafer divided into a plurality of wafers, and FIG. 3 (B) is a partial cross-sectional side view schematically showing how the thickness of each wafer is measured in the measurement step. FIG. 4 (A) is a side view schematically showing a plurality of wafers selected in the wafer lamination step, and FIG. 4 (B) is a side view schematically showing a state in which a plurality of wafers are laminated in the wafer lamination step.
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| JP2016-203071 | 2016-10-14 | ||
| JP2016203071A JP6707292B2 (en) | 2016-10-14 | 2016-10-14 | Method of manufacturing laminated chip |
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| TW201826445A true TW201826445A (en) | 2018-07-16 |
| TWI732935B TWI732935B (en) | 2021-07-11 |
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| JP (1) | JP6707292B2 (en) |
| KR (1) | KR102315783B1 (en) |
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| US4617160A (en) * | 1984-11-23 | 1986-10-14 | Irvine Sensors Corporation | Method for fabricating modules comprising uniformly stacked, aligned circuit-carrying layers |
| US4704319A (en) * | 1984-11-23 | 1987-11-03 | Irvine Sensors Corporation | Apparatus and method for fabricating modules comprising stacked circuit-carrying layers |
| TW503531B (en) * | 2000-09-28 | 2002-09-21 | Toshiba Corp | Multi-layered semiconductor apparatus |
| TW479339B (en) * | 2001-03-01 | 2002-03-11 | Advanced Semiconductor Eng | Package structure of dual die stack |
| JP2003007653A (en) | 2001-06-26 | 2003-01-10 | Disco Abrasive Syst Ltd | System and method of dividing semiconductor wafer |
| JP4769048B2 (en) * | 2005-08-23 | 2011-09-07 | 株式会社ディスコ | Substrate processing method |
| JP2008182015A (en) | 2007-01-24 | 2008-08-07 | Disco Abrasive Syst Ltd | Method for grinding wafer |
| JP5059449B2 (en) * | 2007-03-02 | 2012-10-24 | 株式会社ディスコ | Wafer processing method |
| JP4875532B2 (en) * | 2007-04-03 | 2012-02-15 | 株式会社ディスコ | Cutting device |
| JP5122854B2 (en) * | 2007-04-13 | 2013-01-16 | 株式会社ディスコ | Device grinding method |
| EP2137757B1 (en) | 2007-04-17 | 2015-09-02 | Imec | Method for reducing the thickness of substrates |
| JP4980140B2 (en) * | 2007-05-25 | 2012-07-18 | 株式会社ディスコ | Wafer grinding method |
| JP2013084717A (en) * | 2011-10-07 | 2013-05-09 | Tokyo Electron Ltd | Three-dimensional mounting device |
| JP2013138077A (en) | 2011-12-28 | 2013-07-11 | Tokyo Electron Ltd | Three-dimensional mounting device |
| JP5930840B2 (en) * | 2012-05-22 | 2016-06-08 | 株式会社ディスコ | Processing method of plate |
| JP5995616B2 (en) * | 2012-09-05 | 2016-09-21 | 株式会社ディスコ | Wafer processing method |
| JP6215544B2 (en) * | 2013-03-18 | 2017-10-18 | 株式会社ディスコ | Wafer processing method |
| JP5902114B2 (en) * | 2013-03-22 | 2016-04-13 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| CN103413785B (en) * | 2013-08-02 | 2015-08-26 | 南通富士通微电子股份有限公司 | chip cutting method and chip packaging method |
| JP2015041687A (en) * | 2013-08-21 | 2015-03-02 | 株式会社ディスコ | Wafer processing method |
| JP2015176937A (en) | 2014-03-14 | 2015-10-05 | マイクロン テクノロジー， インク． | Semiconductor device manufacturing method |
| JP2015233077A (en) * | 2014-06-10 | 2015-12-24 | 株式会社ディスコ | Method for processing wafer |
| JP6389660B2 (en) * | 2014-07-04 | 2018-09-12 | 株式会社ディスコ | Grinding method |
| JP2016178100A (en) | 2015-03-18 | 2016-10-06 | マイクロン テクノロジー， インク． | Semiconductor device manufacturing method |
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| CN107958848A (en) | 2018-04-24 |
| KR102315783B1 (en) | 2021-10-20 |
| KR20180041592A (en) | 2018-04-24 |
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