CN107919322B - 具有减少谐波的瞬态电压抑制二极管及其制造和使用方法 - Google Patents

具有减少谐波的瞬态电压抑制二极管及其制造和使用方法 Download PDF

Info

Publication number
CN107919322B
CN107919322B CN201710930501.3A CN201710930501A CN107919322B CN 107919322 B CN107919322 B CN 107919322B CN 201710930501 A CN201710930501 A CN 201710930501A CN 107919322 B CN107919322 B CN 107919322B
Authority
CN
China
Prior art keywords
conductive layer
layer
capacitor
conductive
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710930501.3A
Other languages
English (en)
Other versions
CN107919322A (zh
Inventor
M.戈尔班扎德
J.克拉克
W.A.拉塞尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semtech Corp
Original Assignee
Semtech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semtech Corp filed Critical Semtech Corp
Publication of CN107919322A publication Critical patent/CN107919322A/zh
Application granted granted Critical
Publication of CN107919322B publication Critical patent/CN107919322B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/0788—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type comprising combinations of diodes or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66022—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6603—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/864—Transit-time diodes, e.g. IMPATT, TRAPATT diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请涉及具有减少谐波的瞬态电压抑制二极管及其制造和使用方法。半导体器件包括半导体管芯。在半导体管芯中形成瞬态电压抑制（TVS）结构。在半导体管芯上形成电容器。在一个实施例中，通过在半导体管芯上沉积第一导电层、在第一导电层上沉积绝缘层、以及在半导体管芯上沉积第二导电层来形成电容器。在另一个实施例中，通过在半导体管芯中形成沟道、在沟道中沉积绝缘材料、以及在沟道中沉积导电材料来形成电容器。

Description

具有减少谐波的瞬态电压抑制二极管及其制造和使用方法
优先权声明
本申请要求于2016年10月6日提交的美国临时申请No.62/405,135的权益，该申请通过引用并入本文。
技术领域
本发明一般地涉及半导体器件，更具体地，涉及减少瞬态电压抑制二极管中的谐波生成的半导体器件和方法。
背景技术
半导体器件通常见于现代电子产品中。半导体器件在电气部件的数量和密度有所不同。分立半导体器件通常包含一种类型的电气部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包含数百到数百万个电气部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦接器件（CCD）、太阳能电池和数字微镜器件（DMD）。
半导体器件执行宽范围的功能，例如信号处理、高速计算、发送和接收电磁信号、控制电子装置、将阳光转化为电力，以及为电视显示器创建视觉投影。半导体器件也可见于娱乐、通信、功率转换、网络、计算机和消费产品领域中。半导体器件也可见于军事应用、航空、汽车、工业控制器和办公设备中。
电子装置通常包括与负载并联耦接的瞬态电压抑制（TVS）二极管。TVS二极管通过TVS二极管将瞬态电压尖峰分流远离负载以保护负载。TVS二极管的一个问题是TVS二极管可能导致在电子装置中生成不需要的谐波。当在射频（RF）信号路径或电力线附近使用时，由TVS二极管生成的谐波特别成问题。谐波是具有基频的整数倍的频率的信号或波形。因此，对于具有频率f的信号，二次谐波频率为2f，三次谐波为3f，等等。
如果在生成的谐波信号内包含足够的能量，则谐波可能在基频处引起RF或电力线上的初级波形的显著干扰和失真。由于非线性的缘故生成谐波特别是奇次谐波。在TVS二极管的情况下，电容对反向电压（dCj/dVR）存在非线性依赖性，这是因为TVS二极管是由一个或多个p-n结构成的固态硅雪崩器件。p-n结的耗尽区的宽度随着电压而变化，从而导致TVS二极管的电容的非线性变化。
需要通过生成更线性的电容值的器件来减少TVS二极管的谐波生成。
附图说明
图1a-1e示出了在TVS二极管上形成MIM电容器；
图2a-2d示出了封装具有集成MIM电容器的TVS二极管；
图3示出了保护负载的MIM电容器和TVS二极管的电路图；
图4示出了具有MIM电容器的备选TVS二极管实施例；
图5a-5e示出了在具有TVS二极管的半导体管芯中形成沟道电容器；
图6示出了具有沟道电容器的TVS二极管的电路图；以及
图7a-7b示出了具有集成电容器以减少谐波生成的TVS二极管的使用。
具体实施方式
在下面参考附图的描述中的一个或多个实施例中描述了本发明，其中相同的附图标记表示相同或相似的元件。虽然根据实现本发明目标的最佳方式描述了本发明，但是本领域技术人员将理解，该描述旨在涵盖可包括在例如由所附权利要求和由下列公开和附图支持的权利要求的等同物所限定的本发明的精神和范围内的替代、修改和等同物。
图1a示出了具有形成在半导体管芯中的TVS二极管和导向二极管的半导体管芯10。半导体管芯10包括正掺杂（p掺杂）区域20和负掺杂（n掺杂）区域22。在一个实施例中，p掺杂区域20是基底晶片，并且n掺杂区域22是生长在基底晶片上的外延层。沟道26通过n掺杂区域22形成在半导体管芯10中，以电隔离TVS二极管的端子。将绝缘材料沉积到沟道26中以填充沟道。p掺杂区域24是扩散区域，其被掺杂以形成用于TVS二极管的导向二极管。p掺杂区域24与n掺杂区域22之间的p-n结形成如图3所示的四个导向二极管。n掺杂区域22与p掺杂区域20之间的p-n结形成TVS二极管。
虽然示出了一个特定的TVS二极管实施例，但是在其它实施例中，随后在半导体管芯10上形成的金属-绝缘体-金属（MIM）电容器可以与其它TVS或静电放电（ESD）二极管拓扑结构一起形成。底层TVS二极管可以是非快速恢复的硅雪崩p-n结二极管，或者显示出浅或深快速恢复特性的器件。虽然图1a示出了具有导向二极管以进一步减少结电容的TVS二极管，但是在其它实施例中也可使用没有导向二极管的TVS二极管。包括基于硅控整流器（SCR）的器件在内的其它备选保护方案与所公开的MIM电容器一起使用。 虽然仅示出了其中形成有单个TVS二极管的单个半导体管芯，但是用于形成MIM电容器的以下工艺更常见地在器件的整个晶片上同时形成，然后被单体化以得到单独的管芯。
在图1b中，在半导体管芯10上形成绝缘或钝化层30。绝缘层30包含一层或多层二氧化硅（SiO2），氮化硅（Si3N4），氮氧化硅（SiON），五氧化二钽（Ta2O5），氧化铝（Al2O3）或具有相似绝缘和结构性质的其它材料。绝缘层30的一部分通过激光直接烧蚀（LDA）、化学蚀刻或其它合适的工艺去除以暴露扩散区域24以用于随后的电互连。
使用物理气相沉积（PVD）、化学气相沉积（CVD）、电解电镀、无电镀或其它合适的金属沉积工艺在绝缘层30的开口中形成导电层或电触件32。电触件32包含一层或多层铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）或其它合适的导电材料。在一个实施例中，电触件32包括Ti/Cu、钛钨（TiW）/Cu或耦合剂/Cu的粘附或晶种层。诸如Ni、Au或Ag之类的具有良好湿蚀刻选择性的另一种金属选择性地加入晶种层。晶种层通过溅射、无电镀或通过与无电镀结合沉积层叠的Cu箔而被沉积。在另一个实施例中，电触件32是在沉积绝缘层30之前设置在半导体管芯10上的钨引脚。触件32电连接到扩散区域24，以提供到TVS器件的端子的电连接。
使用与上述用于电触件32的类似材料和工艺，在绝缘层30和电触件32上形成导电层36。在一些实施例中，通过使用光刻法图案化和沉积金属来形成导电层36。在其它实施例中，使用用于形成导电层36的任何合适的加成、半加成或减去的方法。在一些实施例中，导电层36和电触件32在相同的金属沉积步骤中被沉积在一起。
在图1c中，在导电层36B的一部分上形成绝缘或电介质层40。电介质层40以与绝缘层30类似的工艺并使用与绝缘层30类似的材料形成并图案化。在电介质层40上形成导电层42。导电层42以与导电层36类似的工艺并使用与导电层36类似的材料形成并图案化。在一个实施例中，导电层42由氮化钛（TiN）形成。相对于通常用于形成下导电层36的铝而言TiN更容易形成较薄的层。
导电层36B和导电层42作为MIM电容器44的板极工作，而电介质层40作为电容器的电介质层工作。调整电介质层40的厚度，使得电介质层可以在ESD事件期间承受TVS二极管的钳位电压，而不会对电介质层造成显著的损害。增加平面图中的电介质层40和导电层42的表面面积以及下部的导电层36B增加了MIM电容器44的电容值。导电层36b的另一部分作为导电迹线工作，以将电容器44的板极耦接到电触件32。绝缘层30提供半导体管芯10中的TVS二极管电路与电容器44之间的电隔离。
在图1d中，绝缘层50以与绝缘层30类似的方式形成在导电层36和电容器44上。电触件52以与电触件32类似的方式通过绝缘层50形成到达导电层36和42。在一些实施例中，电触件52是在形成绝缘层50之前设置在导电层36和42上的钨引脚。
在图1e中，导电层60形成在绝缘层50和电触件52上。导电层60类似于导电层36，并提供均匀平坦表面以用于晶片的应力消除。导电层60A将电触件52A电连接到电触件52B和导电层42。钝化层62形成在导电层60上，具有通过钝化层形成的开口64以用于电互连。在一些实施例中，导电凸起或另一种类型的互连结构形成在导电层60上的开口64中，以用于将半导体管芯10和电容器44安装和/或电连接到印刷电路板（PCB）或其它衬底。在一些实施例中，在绝缘层62之上或之下形成凸起下金属化。
导电层60A和60B用作TVS器件的两个端子。在一些实施例中，随后在导电层60A和60B上形成互连结构，以将TVS二极管耦接到电子装置的衬底。在其它实施例中，导电层60A和60B保持暴露在连接盘栅格阵列配置中。电容器44与半导体管芯10的TVS二极管并联耦接在导电层60A与60B之间。导电层60A将外部电路通过电触件52B耦接到电容器44的导电层42，并通过电触件52A和导电层36A耦接到底层TVS器件。导电层60B将外部电路耦接到作为导电层36B的一部分的电容器44的相对板极，并且通过导电层36B将外部电路耦接到底层TVS器件的第二端子。
电容器44包括固定或线性电容值。选择电容器44的电容与半导体管芯10中的TVS二极管的电容的比例，使得器件的整体电容由MIM电容器44的更高的线性电容所支配。在一个实施例中，电容器44的电容值大约是底层TVS二极管的电容的十倍。电容器44的线性特性基本上掩盖了TVS二极管的非线性电容，获得具有改进的谐波特性的结构。在具有ESD能力的TVS二极管的相同半导体封装中集成的电容器44通过增加与TVS结电容并联的更大的稳定电容使得TVS电容线性化。
图2a-2d示出了封装具有嵌入式MIM电容器44的上述TVS器件。在图2a中，半导体晶片100具有形成在其中的多个TVS器件。半导体晶片100设置在具有热释放带、UV释放带、双面胶带或另一种类型的界面层104的载体102上。半导体晶片100使用锯片或激光切割工具106单体化成多个单独的TVS器件110。每个TVS器件110包括在具有TVS二极管的半导体管芯10上的层中形成的MIM电容器44。
在图2b中，使用锡膏印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂或其它合适的涂覆器将密封剂或模塑料114沉积在TVS器件110上作为绝缘材料。密封剂114可以是聚合物复合材料，例如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂114是不导电的并且从周围保护半导体器件免受外部元件和污染物的影响。密封剂114还保护TVS器件110免于因暴露于光而劣化。
在图2c中，TVS器件110和密封剂114的面板翻转并设置在具有界面层118的第二载体116上。导电凸起120形成在导电层60上的开口64中。为了形成凸起120，使用蒸发、电解电镀、无电镀、球滴或丝网印刷工艺将导电凸起材料沉积在导电层60上。凸起材料可以是可选的助熔溶液中的Al、Sn、Ni、Au、Ag、铅（Pb）、铋（Bi）、Cu、焊料及其组合。例如，凸起材料可以是共熔的Sn/Pb、高铅焊料或无铅焊料。凸起材料使用合适的附着或接合工艺接合到导电层60上。在一个实施例中，通过将材料加热到其熔点以上使凸起材料回流，以形成球或凸起120。在一些应用中，凸起120再次回流以改善与导电层60的电耦接。凸起120也可以是压缩接合或热压接合至导电层60。凸起120表示可以在导电层60上形成的一种类型的互连结构。互连结构还可以使用螺柱凸起、微凸起、微柱、引线接合或其它电互连。
使用锯片、激光切割工具、水切削工具或其它适当的手段通过密封剂114将TVS器件110单体化彼此分开，形成单独的TVS封装130。单体化可以在形成凸起120之前或之后进行。在一些实施例中，多个TVS器件110由密封剂114保持附着，并且作为具有多个TVS器件的单个封装出售。
图2d示出了准备用于集成到电子装置中的单体化的TVS封装130。在半导体管芯10中形成的TVS二极管与MIM电容器44并联地电耦接在导电凸起120A与120B之间。为了使用，如图3所示，TVS封装130与负载并联布线，以保护负载免受瞬态电压尖峰。图3示出了半导体管芯10包括由p掺杂区域20、n掺杂衬底22和绝缘沟道26形成的TVS二极管66。四个导向二极管67由扩散区域24形成。电容器44和半导体管芯10封装在一起，并且并联耦接在作为封装端子工作的导电凸起120A与120B之间。
表示任何待保护电路的负载140耦接在端子120A与120B之间。负载140包括功率输入端子142和接地电压电位端子144。负载140在功率输入端子142处接收功率信号，该功率信号经受周期性瞬态电压尖峰。功率输入端子142上的瞬态电压尖峰通过TVS二极管66而不是通过负载140被路由到接地节点144。TVS二极管66包括随着输入电压而变化的电容。电容器44包括较大的电容，其掩食（eclipse）非线性TVS电容，使得TVS封装130作为基本上线性的电容呈现在系统中。
在一个实施例中，凸起120A和120B耦接在电子装置的耳机插孔的端子之间，而不是功率输入端子上。在耳机插孔处经历的静电放电或其它电击基本上被TVS二极管吸收，TVS二极管保护电子装置内的电路。电容器44使得TVS封装的整体电容具有增加的线性，并且静电放电的吸收比没有电容器44时产生更少的谐波干扰。在其它实施例中，具有TVS二极管和MIM电容器44的半导体管芯10被耦接在功率输入端子、通用串行总线（USB）端口或电子装置的其它I/O端口之间，以通过减少的谐波生成来防止瞬态电压。
虽然示出了封装TVS器件110的一种基本方法，但是在其它实施例中也使用其它封装技术。在一些实施例中，封装衬底或引线框架被使用以支持TVS器件110并提供所需类型的封装端子。
图4示出了在可快速恢复的另一TVS二极管实施例上形成的电容器44。半导体管芯170包括p掺杂的基底衬底172。在p掺杂的基底衬底172上形成n掺杂层174。在n掺杂层174上形成硼-氮化物（BN）隔离层176。在BN隔离层176上形成p掺杂外延层178。绝缘沟道180在半导体管芯170中形成。如图1 C所示，MIM电容器44由导电层36、电介质层40和导电层42形成。MIM电容器44与在半导体管芯170中形成的底层TVS器件并联耦接。
图5a-5e示出了形成具有与TVS二极管并联的沟道电容器的TVS器件200。图5a示出了在衬底内形成正掺杂区域204的n掺杂半导体衬底202。掺杂区域204和衬底202一起形成双向TVS二极管。在其它实施例中使用其它TVS拓扑。
在图5b中，沟道210形成在衬底202中形成的TVS二极管的侧面的两侧。沟道210使用掩模和化学蚀刻、等离子体蚀刻、深度反应离子蚀刻或其它管芯蚀刻方法形成。沟道210可以是TVS二极管的相对端子的两侧的条纹、多个圆形或多边形通孔或其它适当的物理布局。当每个沟道中的金属被并联耦接时，沟道210中的衬底202的更大的整体表面面积增加了总电容。在任何合适的平面布图中，TVS二极管在具有沟道电容器的公共衬底中形成。在图5C中，沟道210衬有绝缘材料212。在一个实施例中，绝缘材料212是在沟道210内生长或沉积到沟道210中的氧化物层。在一些实施例中，绝缘材料212延伸跨过衬底202的顶部或有源表面，以将衬底与随后形成的金属层隔离。
在图5d中，多晶硅214沉积到沟道210中，随后在图5e中，沉积导电层220-222。在一些实施例中，绝缘材料212在衬底202上延伸，以将衬底与导电层220隔离。多晶硅214与衬底202形成电容器，并且绝缘层212用作电容器电介质。在其它实施例中，除了多晶硅之外的导电材料沉积到沟道210中以形成电容器。导电层220将由p掺杂区域204和n掺杂衬底202形成的TVS二极管与在多晶硅214与衬底202之间形成的电容器并联耦接。
图6示出了图5e中的TVS器件200的电路图。双向TVS二极管230由p掺杂区域204和n掺杂衬底202形成。多晶硅214和衬底202形成电容器，其与TVS二极管230并联在电触件220A和220B之间。TVS器件200中的电容器使用硅的垂直区域形成，以形成具有氧化物衬垫的多晶硅填充沟道。当底层TVS结构的电容需要氧化物的大值电容以掩盖TVS电容的非线性时，沟道电容器实施例是有用的。在衬底202中形成的底层TVS可以是p-n结器件、显示浅或深快速恢复特性的器件或任何其它电路保护器件。多晶硅214的线性电容主导着TVS二极管230的非线性电容，这有助于减少可能干扰周围电路的谐波。
图7a-7b示出了将上述TVS封装结合到电子装置中。图7a示出了来自图2d的TVS封装130的部分横截面，其被安装在PCB或作为电子装置的一部分的其它衬底250上。凸起120被回流到导电层252上，以将TVS封装130物理附接并电连接到衬底250上。上述TVS实施例中的任何一个可类似地安装在衬底250上。对于图5e中的实施例而言，TVS器件200以类似于TVS器件110的方式利用在导电层220A和220B上形成的凸起或另一互连结构被封装。在一些实施例中，在TVS封装130与PCB 250之间使用粘合剂层。
半导体管芯10通过凸起120、导电层60、电触件52、导电层36和电触件32电耦接到导电层252。
图7b示出了作为使用TVS封装130的电子装置的一个示例的蜂窝电话、平板计算机或其它移动设备256。移动设备256包括用于输入或输出音频信号的耳机插孔258。导电信号迹线252将耳机插孔258耦接到音频处理器芯片260。模拟信号被转换为数字信号并传送到中央处理单元（CPU）或片上系统（SoC）262。两个信号迹线252被示出连接到耳机插孔258，其允许单个音频信号和接地信号。TVS封装130A耦接在两个导电迹线252之间，以将音频信号迹线上的瞬态电压尖峰路由到接地迹线。在其它实施例中，传送三个音频信号，立体声输出和单声道麦克风输入。具有由密封剂114附接的三个TVS器件110的三联封装可以使用单个封装用来保护所有三个音频信号线。
移动设备256还包括向移动设备提供功率的USB端口266。来自连接的USB线的功率和接地信号被路由到功率芯片268。功率芯片268包括用以控制电池充电并确保输入到SoC262、音频处理器芯片260以及移动设备的其它半导体器件的适当功率的电路。TVS封装130B耦接在USB端口266的功率和接地输入信号迹线252之间。TVS封装130B将USB功率输入信号上的瞬态电压尖峰路由到地，以保护移动设备256的部分免受由于过电压输入的损坏。
TVS封装130A和130B包括集成电容器，使得当经历瞬态电压尖峰时，封装的整体电容不会显著改变。集成电容器的固定或线性电容遮蔽了TVS二极管的依赖电压的电容。减少谐波在诸如蜂窝电话（其包括位于移动设备内的不同位置的若干天线）的移动设备中尤为重要。在许多情况下，一个或多个天线位于耳机插孔258或USB端口266附近，并因此特别容易受到端口上的ESD事件的谐波干扰。在TVS封装中包括集成的MIM或沟道电容器减少了谐波的生成，并从而减少由附近天线拾取的干扰。
虽然已经详细说明了本发明的一个或多个实施例，但是本领域技术人员将理解，在不脱离如所附权利要求中阐述的本发明的范围的情况下，可以对那些实施例进行修改和改写。

Claims (9)

1.一种制造半导体器件的方法，包括：
提供半导体管芯；
在所述半导体管芯中形成瞬态电压抑制结构；
通过如下步骤在所述半导体管芯上形成电容器(44)：在所述半导体管芯上方形成钝化层（30），在所述钝化层上方形成包括所述电容器的第一端子的第一导电层(36)，仅在所述第一导电层的第一部分上直接形成电介质层(40)，以及直接在所述电介质层上形成第二导电层(42)以作为所述电容器的第二端子，其中所述第二导电层通过所述电介质层与所述第一导电层物理隔离；
在所述电容器上方形成与所述钝化层、第一导电层、电介质层和第二导电层物理接触的绝缘层(50)；
形成穿过所述绝缘层到与所述电容器的所述第一端子电隔离的所述第一导电层的第二部分的第一导电通孔(52A)；
形成穿过所述绝缘层到所述第二导电层的第二导电通孔(52B)；
形成穿过所述绝缘层到与所述电容器的所述第一端子电连接的所述第一导电层的第三部分的第三导电通孔(52C)；
在所述绝缘层上方形成第三导电层（60），所述第三导电层的一部分（60A）将所述第一导电通孔电耦合到所述第二导电通孔；以及
形成半导体封装，其中所述瞬态电压抑制结构和电容器并联耦接在所述半导体封装的第一端子和第二端子之间。
2.如权利要求1所述的方法，其中，所述第一导电层包括铝，并且所述第二导电层包括氮化钛。
3.如权利要求1所述的方法，还包括形成包括快速恢复特性的所述瞬态电压抑制结构。
4.如权利要求1所述的方法，还包括形成包括多个瞬态电压抑制结构的所述半导体封装。
5.一种制造半导体器件的方法，包括：
提供半导体管芯，所述半导体管芯包括在所述半导体管芯中形成的瞬态电压抑制结构；
通过如下步骤在所述半导体管芯上形成电容器：在所述半导体管芯上方形成钝化层（30），在所述钝化层上方形成包括所述电容器的第一端子的第一导电层(36)，仅在所述第一导电层的第一部分上直接形成电介质层(40)，以及直接在所述电介质层上形成第二导电层(42)以作为所述电容器的第二端子，其中所述第二导电层通过所述电介质层与所述第一导电层物理隔离，其中所述电容器的电容大于所述瞬态电压抑制结构的结电容；
在所述电容器上方形成与所述钝化层、第一导电层、电介质层和第二导电层物理接触的绝缘层(50)；
形成穿过所述绝缘层到与所述电容器的所述第一端子电隔离的所述第一导电层的第二部分的第一导电通孔(52A)；
形成穿过所述绝缘层到所述第二导电层的第二导电通孔(52B)；
形成穿过所述绝缘层到与所述电容器的所述第一端子电连接的所述第一导电层的第三部分的第三导电通孔(52C)；
在所述绝缘层上方形成第三导电层（60），所述第三导电层有一部分（60A）将所述第一导电通孔电耦合到所述第二导电通孔；以及
形成半导体封装（130），其中所述瞬态电压抑制结构和电容器并联耦接。
6.一种半导体器件，包括：
半导体管芯，所述半导体管芯包括在所述半导体管芯中形成的瞬态电压抑制结构；
在所述半导体管芯上形成的电容器，其中所述电容器包括：在所述半导体管芯上方形成的钝化层（30），在所述钝化层上方形成的包括所述电容器的第一端子的第一导电层(36)，仅在所述第一导电层的第一部分上直接形成的电介质层(40)，以及直接在所述电介质层上形成以作为所述电容器的第二端子的第二导电层(42)，其中所述第二导电层通过所述电介质层与所述第一导电层物理隔离；
在所述电容器上方形成的与所述钝化层、第一导电层、电介质层和第二导电层物理接触的绝缘层(50)；
穿过所述绝缘层到与所述电容器的所述第一端子电隔离的所述第一导电层的第二部分而形成的第一导电通孔(52A)；
穿过所述绝缘层到所述第二导电层而形成的第二导电通孔(52B)；
穿过所述绝缘层到电连接到所述电容器的所述第一端子的所述第一导电层的第三部分而形成的第三导电通孔(52C)；
在所述绝缘层上方形成的第三导电层（60），所述第三导电层有一部分（60A）将所述第一导电通孔电耦合到所述第二导电通孔；在所述第三导电层上形成的第一互连结构(120)；以及
在所述第三导电层上形成的第二互连结构，其中所述瞬态电压抑制结构和电容器并联地电耦接在所述第一互连结构和第二互连结构之间。
7.如权利要求6所述的半导体器件，其中，所述第一导电层包括铝，并且所述第二导电层包括氮化钛。
8.如权利要求6所述的半导体器件，其中，所述半导体器件包括被封装在一起的多个瞬态电压抑制结构。
9.如权利要求6所述的半导体器件，还包括：包括衬底的电子装置，其中，所述瞬态电压抑制结构和电容器通过所述第一互连结构和第二互连结构耦接到所述电子装置的衬底。
CN201710930501.3A 2016-10-06 2017-10-09 具有减少谐波的瞬态电压抑制二极管及其制造和使用方法 Active CN107919322B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662405135P 2016-10-06 2016-10-06
US62/405135 2016-10-06
US15/721488 2017-09-29
US15/721,488 US10510741B2 (en) 2016-10-06 2017-09-29 Transient voltage suppression diodes with reduced harmonics, and methods of making and using

Publications (2)

Publication Number Publication Date
CN107919322A CN107919322A (zh) 2018-04-17
CN107919322B true CN107919322B (zh) 2023-08-29

Family

ID=60080593

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710930501.3A Active CN107919322B (zh) 2016-10-06 2017-10-09 具有减少谐波的瞬态电压抑制二极管及其制造和使用方法

Country Status (5)

Country Link
US (1) US10510741B2 (zh)
EP (1) EP3306661B1 (zh)
KR (2) KR20180038399A (zh)
CN (1) CN107919322B (zh)
TW (1) TWI710104B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9225199B2 (en) 2011-03-22 2015-12-29 Triune Ip, Llc Variable power energy harvesting system
US11276938B2 (en) 2018-01-11 2022-03-15 Semtech Corporation Single layer antenna
FR3085575B1 (fr) 2018-09-03 2021-06-18 St Microelectronics Tours Sas Boitier de puce electronique
US10892652B2 (en) 2018-12-12 2021-01-12 Semtech Corporation Adaptive ping method for wireless charging system with wide charge distance
FR3093230B1 (fr) * 2019-02-27 2023-01-06 St Microelectronics Tours Sas Boîtier de puce électronique
US11791332B2 (en) 2021-02-26 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked semiconductor device and method
CN114038902B (zh) * 2021-12-01 2022-07-01 上海镓芯科技有限公司 一种薄膜型半导体的瞬态电压抑制二极管

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040071816A (ko) * 2003-02-07 2004-08-16 삼성전자주식회사 반도체소자의 커패시터 및 그 제조방법
CN101617382A (zh) * 2007-06-16 2009-12-30 万国半导体股份有限公司 在集成有暂态电压抑制器的对称与非对称emi滤波器中获得线性电容的方法
CN102270588A (zh) * 2010-06-02 2011-12-07 新科金朋有限公司 在半导体管芯周围形成emi屏蔽层的半导体器件和方法
CN205508776U (zh) * 2013-02-28 2016-08-24 株式会社村田制作所 半导体装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050116276A1 (en) 2003-11-28 2005-06-02 Jing-Horng Gau Metal-insulator-metal (MIM) capacitor and fabrication method for making the same
US7781826B2 (en) * 2006-11-16 2010-08-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
SE533579C2 (sv) * 2007-01-25 2010-10-26 Silex Microsystems Ab Metod för mikrokapsling och mikrokapslar
US8120887B2 (en) * 2007-02-28 2012-02-21 Alpha & Omega Semiconductor, Ltd. MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage
US7863995B2 (en) * 2007-06-16 2011-01-04 Alpha & Omega Semiconductor Ltd. Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS
JP5358974B2 (ja) * 2008-02-28 2013-12-04 ダイキン工業株式会社 フッ素化１，３−ジオキソラン−２−オンの製造方法
US7955941B2 (en) 2008-09-11 2011-06-07 Semiconductor Components Industries, Llc Method of forming an integrated semiconductor device and structure therefor
US8035224B2 (en) 2008-11-14 2011-10-11 Infineon Technologies Ag Semiconductor device
US8476745B2 (en) * 2009-05-04 2013-07-02 Mediatek Inc. Integrated circuit chip with reduced IR drop
US8883559B2 (en) * 2009-09-25 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of forming adhesive material to secure semiconductor die to carrier in WLCSP
JP5585366B2 (ja) 2009-10-22 2014-09-10 セイコーエプソン株式会社 集積回路装置及び電子機器
US20130026609A1 (en) * 2010-01-18 2013-01-31 Marvell World Trade Ltd. Package assembly including a semiconductor substrate with stress relief structure
US20110175218A1 (en) * 2010-01-18 2011-07-21 Shiann-Ming Liou Package assembly having a semiconductor substrate
US8501580B2 (en) * 2010-02-26 2013-08-06 Jerry Hu Process of fabricating semiconductor device with low capacitance for high-frequency circuit protection
WO2012023394A1 (ja) 2010-08-18 2012-02-23 株式会社村田製作所 Ｅｓｄ保護デバイス
KR101041752B1 (ko) * 2011-02-01 2011-06-17 주식회사 시지트로닉스 다단형 구조의 반도체 필터 및 그 제조방법
TWI459531B (zh) * 2012-04-18 2014-11-01 Jeng Jye Shau 高面積效率的電子元件及其製造方法
US20150321877A1 (en) * 2014-03-21 2015-11-12 Jorge PRATS Hose Storage Apparatus
KR101621145B1 (ko) * 2014-06-23 2016-05-13 주식회사 케이이씨 과도 전압 억제 소자 및 그 제조 방법
US20160095221A1 (en) 2014-09-27 2016-03-31 Qualcomm Incorporated Integration of electronic elements on the backside of a semiconductor die
US9997510B2 (en) * 2015-09-09 2018-06-12 Vanguard International Semiconductor Corporation Semiconductor device layout structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040071816A (ko) * 2003-02-07 2004-08-16 삼성전자주식회사 반도체소자의 커패시터 및 그 제조방법
CN101617382A (zh) * 2007-06-16 2009-12-30 万国半导体股份有限公司 在集成有暂态电压抑制器的对称与非对称emi滤波器中获得线性电容的方法
CN102270588A (zh) * 2010-06-02 2011-12-07 新科金朋有限公司 在半导体管芯周围形成emi屏蔽层的半导体器件和方法
CN205508776U (zh) * 2013-02-28 2016-08-24 株式会社村田制作所 半导体装置

Also Published As

Publication number Publication date
TW201834195A (zh) 2018-09-16
US10510741B2 (en) 2019-12-17
TWI710104B (zh) 2020-11-11
CN107919322A (zh) 2018-04-17
EP3306661B1 (en) 2022-06-01
US20180102356A1 (en) 2018-04-12
KR20180038399A (ko) 2018-04-16
KR20210061322A (ko) 2021-05-27
EP3306661A1 (en) 2018-04-11
KR102418774B1 (ko) 2022-07-07

Similar Documents

Publication Publication Date Title
CN107919322B (zh) 具有减少谐波的瞬态电压抑制二极管及其制造和使用方法
US11881476B2 (en) Semiconductor device and method of stacking semiconductor die for system-level ESD protection
TWI499030B (zh) 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法
US9153544B2 (en) Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
TWI579977B (zh) 使用引線架體以形成用於半導體晶粒的垂直互連的通過密封物的開口之半導體裝置和方法
US8492197B2 (en) Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
CN102237281B (zh) 半导体器件及其制造方法
TWI575565B (zh) 於晶圓級封裝之上使用紫外線固化導電油墨形成再佈線層的半導體裝置及方法
US9721925B2 (en) Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
US20150001708A1 (en) Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package
CN103681607A (zh) 半导体器件及其制作方法
US20240006335A1 (en) Semiconductor Device and Method of Forming Embedded Magnetic Shielding
KR20230170554A (ko) Fod 재료를 사용한 선택적 차폐 반도체 디바이스 및 그 제조 방법
KR20240001031A (ko) 이중 차폐 반도체 디바이스 및 그 제조 방법
KR20240026097A (ko) 부분 emi 차폐를 위한 반도체 디바이스 및 그 제조 방법
KR20240009340A (ko) 전기 커넥터의 오염을 피하기 위한 2개 단계의 공정에서 emi 차폐 재료를 형성하는 반도체 디바이스 및 그 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant