CN107887348A - 半导体封装结构 - Google Patents
半导体封装结构 Download PDFInfo
- Publication number
- CN107887348A CN107887348A CN201710762051.1A CN201710762051A CN107887348A CN 107887348 A CN107887348 A CN 107887348A CN 201710762051 A CN201710762051 A CN 201710762051A CN 107887348 A CN107887348 A CN 107887348A
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- core substrate
- mask layer
- solder mask
- semiconductor package
- attachment surface
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
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Abstract
本发明实施例提供了一种半导体封装结构。其中该半导体封装结构包括:核心基板,由第一材料形成,并且具有相对的装置附着面与焊料凸块附着面;凸块垫,设置在该焊料凸块附着面上;第一焊料屏蔽层,由该第一材料形成,并且覆盖该核心基板的该焊料凸块附着面以及该凸块垫的一部分;以及第二焊料屏蔽层,覆盖该核心基板的该装置附着面,其中该第二焊料屏蔽层由第二材料形成。本发明实施例,可以提高半导体封装结构的可靠性。
Description
技术领域
本发明涉及封装技术,尤其涉及一种半导体封装结构。
背景技术
为了确保电子产品及通信装置的持续小型化与多功能性,小尺寸、支持多引脚连接、高速操作以及具有多功能性的半导体封装受到期待。这些影响迫使半导体封装制造者开发了扇出(fan-out)半导体封装。但是,多功能芯片封装增长的I/O(Input/output,输入/输出)连接数量会诱发热电问题,例如,散热、串扰、信号传播延迟、RF(Radio Frequency,射频)电路中的电磁干扰等问题。这些热电问题会影响产品的可靠性和质量。
因此,一种创新的半导体封装结构受到期待。
发明内容
有鉴于此,本发明实施例提供了一种半导体封装结构,具有好的可靠性。
本发明实施例提供了一种半导体封装结构,包括:核心基板,由第一材料形成,并且具有相对的装置附着面与焊料凸块附着面;凸块垫,设置在该焊料凸块附着面上;第一焊料屏蔽层,由该第一材料形成,并且覆盖该核心基板的该焊料凸块附着面以及该凸块垫的一部分;以及第二焊料屏蔽层,覆盖该核心基板的该装置附着面,其中该第二焊料屏蔽层由第二材料形成。
其中,该第二材料不同于该第一材料。
其中,该第一材料包括:热固性材料,以及该第二材料包括:光固化材料。
其中,该第一材料包括:聚丙烯树指或者ABF(Ajinomoto build-up film)树脂。
其中,该核心基板以及该第一焊料屏蔽层均包括:分散于其中的玻璃纤维。
其中,该第二材料包括:光可成像焊料屏蔽材料。
其中,进一步包括:第一导电迹线,设置在该装置附着面上并且被该第一焊料屏蔽层覆盖;第二导电迹线,设置在该凸块附着面上并且被该第二焊料屏蔽层覆盖;以及通孔插塞,穿过该核心基板并电性连接该第一导电迹线与该第二导电迹线。
其中,该凸块垫从该第一焊料屏蔽层的第一开口中露出,并且该第一开口相邻于该凸块垫。
其中,进一步包括:装置垫,设置在该核心基板的该装置附着面上,其中该装置垫从该第二焊料屏蔽层的第二开口中露出并且与该第二开口以一距离隔开。
本发明实施例提供了一种半导体封装结构,包括:核心基板,具有第一表面与相对于该第一表面的第二表面;第一焊垫,设置在该核心基板的该第一表面上;焊料屏蔽层,覆盖该核心基板的该第一表面;以及导电插塞结构,具有顶部和底部,其中该顶部位于该核心基板的该第一表面上,其中该底部位于该第一表面与该第二表面之间。
其中,该核心基板包括:沟槽,形成为从该核心基板的该第二表面延伸进该核心基板的一部分中,以及该导电插塞结构的底部暴露于该沟槽的底部。
其中,该导电插塞结构覆盖该核心基板的该第一表面并且延伸进该核心基板内。
其中,该底部充当接近该第二表面的第二焊垫。
其中,该核心基板与该焊料屏蔽层由不同或者相同的材料形成。
其中,形成该核心基板的材料包括:热固性材料,以及形成该焊料屏蔽层的材料包括:光固化材料。
其中,形成该核心基板的材料包括:聚丙烯树指或者ABF(Ajinomoto build-upfilm),及/或,该核心基板以及该第一焊料屏蔽层均包括:分散于其中的玻璃纤维。
其中,形成该焊料屏蔽层的材料包括:光可成像焊料屏蔽材料。
本发明实施例提供了一种半导体封装结构,包括:基座,其中该基座包括:核心基板,由第一材料形成,并且具有相对的装置附着面与焊料凸块附着面;第一焊料屏蔽层,由该第一材料形成并且覆盖该核心基板的该焊料凸块附着面;以及凸块垫,设置在该核心基板的该焊料凸块附着面上,其中该凸块垫从该第一焊料屏蔽层的开口中露出;以及焊料凸块结构,接触该第一焊料屏蔽层并且电性连接至该凸块垫。
其中,进一步包括:半导体装置,设置在该核心基板的该装置附着面上并且电性耦接至该基座的装置垫,其中该装置垫设置在该基座的该装置附着面上。
其中,该基座包括:第二焊料屏蔽层,覆盖该基座的该装置附着面,并且设置在该半导体装置与该基座之间。
其中,进一步包括:第一导电迹线,设置在该装置附着面上并且被该第一焊料屏蔽层覆盖;第二导电迹线,设置在该凸块附着面上并且被该第二焊料屏蔽层覆盖;以及通孔插塞,穿过该核心基板,其中该通孔插塞电性连接至该第一导电迹线与该第二导电迹线。
其中,该第二焊料屏蔽层由不同于该第一材料的第二材料形成。
其中,该第一材料包括:聚丙烯树指或者ABF(Ajinomoto build-up film),及或,该第一材料包括:分散于其中的玻璃纤维。
其中,该第二材料包括:光可成像焊料屏蔽材料。
本发明实施例的有益效果是:
本发明实施例可以改善半导体封装结构的可靠性。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例,可以更全面地理解本发明,其中:
图1为根据本发明一些实施例的半导体封装结构的横截面示意图;
图2为根据本发明一些实施例的半导体封装结构的横截面示意图;以及
图3为根据本发明一些实施例的半导体封装结构的横截面示意图。
具体实施方式
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解,硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式,而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语,故应解释成“包括(含)但不限定于”。另外,“耦接”一词在此为包括任何直接及间接的电气连接手段。因此,若文中描述第一装置耦接于第二装置,则代表该第一装置可直接电气连接至该第二装置,或透过其它装置或连接手段间接地电气连接至该第二装置。
以下描述为实现本发明的较佳预期方式。但是,该描述仅是出于说明本发明一般原理的目的,而不意味着是对本发明的限制。本发明的范围可通过参考权利要求来确定。
本发明实施例提供了一种半导体封装结构。该半导体封装结构包括:基座(base),其中该基座包括:核心基板,具有装置附着(device-attach)面和相对于该装置附着面的焊料凸块附着(solder-bump-attach)面。在一些实施例中,该核心基板与覆盖该核心基板的焊料凸块附着面的第一焊料屏蔽层可以由相同的材料形成,例如,热固性(thermosetting)材料。该第一焊料屏蔽层有助于平衡由于核心基板与第二焊料屏蔽层之间的CTE(Coefficient of Thermal Expansion,热膨胀系数)不匹配而施加在核心基板上的应力,其中该第二焊料屏蔽层设置在该核心基板的装置附着面上。因此,可以改善半导体封装结构的可靠性。
图1为根据本发明一些实施例的半导体封装结构500a的横截面示意图。在一些实施例中,该半导体封装结构500a可以为通过使用导电结构来将半导体装置连接至基座的倒装芯片封装,其中导电结构例如为铜柱凸块。在一些实施例中,该半导体封装结构500a可以为通过使用线接合技术来将半导体装置连接至基座的封装。请参考图1,该半导体封装结构500a包括:基座250a。在一些实施例中,该基座250a包括:核心基板200a,装置垫204,凸块垫208,导电迹线206和210,通孔插塞(through via plug)214,焊料屏蔽层216a和220。在一些实施例中,该基座250a包括:PCB(Printed Circuit Board,印刷电路板)。
在一些实施例中,如图1所示,基座250a的核心基板200a包括:装置附着面201以及焊料凸块附着面203,其中该装置附着面201以及该焊料凸块附着面203互为相反面。该核心基板200a的装置附着面201用于半导体装置300设置于其上。该核心基板200a的焊料凸块附着面203用于焊料凸块结构226设置于其上。在一些实施例中,核心基板200a由热固性(thermosetting)材料形成。在一些实施例中,核心基板200a由树脂基(resin-base)材料形成。例如,核心基板200a可以由纸质酚醛树脂(paper phenolic resin)、复合环氧树脂(composite epoxy)、聚酰亚胺树脂、BT(Bismaleimide-Triazine,双马来酰亚胺三嗪)树脂或者PP(polypropylene,聚丙烯)树脂形成。在一些实施例中,核心基板200a包括:玻璃纤维205,分散于核心基板200a中以加强基座250a的强度。在一些实施例中,玻璃纤维205是可选的。
如图1所示,装置垫(如焊垫)204和导电迹线206设置在核心基板200a的装置附着面201上。凸块垫208和导电迹线210设置在核心基板200a的焊料凸块附着面203上。在一些实施例中,装置垫204电性连接至半导体装置300,并且凸块垫208电性连接至对应的焊料凸块结构226。在一些实施例中,形成一个或更多的穿过核心基板200a的通孔插塞(throughvia plug)214。通孔插塞214的两端(未示出)分别从核心基板200a的装置附着面201和焊料凸块附着面203露出。另外,通孔插塞214的两端分别接触并电性连接至对应的导电迹线206和对应的导电迹线210。在一些实施例中,导电迹线206和210可以包括:电源迹线部分、信号迹线部分或接地迹线部分。在一些实施例中,导电迹线210具有充当基座200的凸块垫区域的部分212。装置垫204,凸块垫208,导电迹线206,导电迹线210以及通孔插塞214可以用来提供直接安装在基座250a上的半导体装置300的I/O连接。装置垫204,凸块垫208,导电迹线206,导电迹线210以及通孔插塞214可以由含有铜或铜合金的导电金属形成。装置垫204,凸块垫208,导电迹线206,导电迹线210可以通过电镀(electronic plating)工艺和接着的图案化工艺来形成。通孔插塞214可以通过激光钻孔工艺和电镀工艺来形成。在一些实施例中,Ni/Au(镍/金)层结构207通过电镀工艺形成于装置垫204以及凸块垫208上。在一些实施例中,Ni/Au层结构207是可选的。
在一些实施例中,如图1所示,焊料屏蔽层216a覆盖核心基板200a的装置附着面201。焊料屏蔽层216a可以覆盖直接位于通孔插塞214上的导电迹线206。焊料屏蔽层216a可以防止其下面的导电迹线206被氧化。在一些实施例中,焊料屏蔽层216a具有一个或者多个开口218a以露出装置垫204。另外,焊料屏蔽层216a的开口218a与装置垫204通过距离D隔开。焊料屏蔽层216a的开口218a与装置垫204隔开以防止设置在装置垫204上的半导体装置300的导电结构322与其他导线和装置垫短路。另外,焊料屏蔽层216a的开口218a可以提供位置来供半导体装置300的导电结构322接合于其上。在一些实施例中,焊料屏蔽层216a包括:耐浸焊(solder-resistant)材料。在一些实施例中,焊料屏蔽层216a可以包括:光固化(photocuring)材料,诸如光可成像(photoimageable)焊料屏蔽材料。在一些实施例中,焊料屏蔽层216a可以包括:焊料屏蔽或者绝缘材料,其中绝缘材料包括:聚酰亚胺、ABF(Ajinomoto build-up film,曰本味之素公司所供应的一种环氧树脂绝缘膜)、环氧树脂、PMMA(polymethylmethacrylate,聚甲基丙烯酸甲酯)树脂、含环氧树脂和PPMA树脂的复合物,或者PP(polypropylene)树脂。在一些实施例中,焊料屏蔽层216a和核心基板200a可以由不同的材料形成。在一些实施例中,焊料屏蔽层216a可以通过涂布(coating)、印刷工艺、粘附(adhesion)工艺、层压工艺或另一恰当的工艺来形成。
在一些实施例中,如图1所示,另一焊料屏蔽层220覆盖核心基板200a的焊料凸块附着面203。另外,焊料屏蔽层220可以覆盖直接设置在通孔插塞214上的导电迹线210。焊料屏蔽层220可以防止其下面的导电迹线210被氧化。在一些实施例中,焊料屏蔽层220具有一个或者多个开口222,以露出凸块垫208以及导电迹线210的接垫部分212。另外,焊料屏蔽层220的开口222位于凸块垫208的边界内。换言之,焊料屏蔽层220部分地覆盖凸块垫208。焊料屏蔽层220可以相邻于凸块垫208。焊料屏蔽层220的开口222可以防止设置在凸块垫208上的焊料凸块结构226与其他导线和凸块垫短路。另外,焊料屏蔽层220的开口222可以给焊料凸块结构226提供位置,以供焊料凸块结构226形成于其上。
在一些实施例中,焊料屏蔽层220和核心基板200a由相同的材料形成。另外,焊料屏蔽层216a和220可以由不同的材料形成。例如,焊料屏蔽层220和核心基板200a由热固性材料形成,诸如PP树脂。在其他一些实施例中,焊料屏蔽层216a由ABF形成。在一些实施例中,焊料屏蔽层220可以包括:玻璃纤维221,分散于焊料屏蔽层220中以加强焊料屏蔽层220的强度。在一些实施例中,玻璃纤维221是可选的。
在一些实施例中,如图1所示,半导体装置300通过接合工艺以其主动面面向基座250a的方式来安装于基座250a的核心基板200a上。在一些实施例中,半导体装置300包括:晶粒、封装、晶圆级封装。在一些实施例中,如图1所示,该半导体装置300为倒装芯片封装。如图1所示,半导体装置300可以包括:半导体主体301,覆盖在该半导体主体301上的金属垫304,以及覆盖在该金属垫304上的绝缘层302。半导体装置300的电路设置在主动面上,并且金属垫304设置在该电路的顶部。半导体装置300的电路经由多个设置在半导体装置300的主动面上的导电结构322与核心基板200a的装置附着面201上的装置垫204和导电迹线206互连。但是,可以理解的是,图1所示的导电结构222仅是示例,而不是对本发明的限制。
在一些实施例中,导电结构322可以包括:导电凸块结构,诸如铜凸块或焊料凸块结构,导电线结构,或者导电膏(conductive paste)结构。在一些实施例中,如图1所示,导电结构322为由金属堆叠构成的铜凸块结构,其中该金属堆叠包括:UBM(Under-BumpMetallurgy,凸块下金属)层306,铜层316(如电镀铜层),导电缓冲层318和焊料盖320。在一些实施例中,UBM层306可以通过沉积方式形成在开口中露出的金属垫304上,其中沉积方式例如为溅射或电镀方式,以及接着的各向异性蚀刻工艺。该各向异性蚀刻工艺在形成导电柱之后执行。UBM层306也可以延伸至绝缘层302的顶面上。在一些实施例中,UBM层306可以包括:钛、铜、或者他们的组合。铜层316(诸如电镀铜层)可以形成于UBM层306上。开口可以使用铜层316和UBM层306来填充,并且在开口内的铜层316和UBM层306可以形成导电结构322的完整插塞。铜层316的形成位置由干膜光阻(dry film photoresist)或液体光阻图案(未示出)来定义。
在一些实施例中,底部填充材料330可以引入至该半导体装置300和基座250a之间的间隙里。在一些实施例中,底部填充材料330可以包括:CUF(capillary underfill,毛细底部填充材料)、MUF(molded underfill,模塑底部填充材料)或者他们的组合。
在一些实施例中,焊料凸块结构226形成于核心基板200a的焊料凸块附着面203上。另外,形成的焊料凸块结构226填充焊料屏蔽层220的开口222并且电性连接至对应的凸块垫208。在一些实施例中,形成的焊料凸块结构226覆盖焊料屏蔽层220的表面的接近开口222的部分。在一些实施例中,焊料凸块结构226可以由诸如焊膏等材料形成。焊料凸块结构226可以通过沉积工艺和图案化工艺,或者印刷工艺/球附着工艺,来形成于凸块垫208上。
由于焊料屏蔽层216a设置在核心基板200a的装置附着面201上,因此核心基板200a会遭受应力,该应力是因为光固化材料形成的焊料屏蔽层216a与热固性材料形成的核心基板200a之间CTE不匹配而产生的。考虑在核心基板200a上的应力的方向,覆盖核心基板200a的焊料凸块附着面203的焊料屏蔽层220可以由与核心基板200a的材料类似或相同的材料来形成。焊料屏蔽层220有助于平衡来自焊料屏蔽层216a的应力,从而改善半导体封装结构500a的热循环可靠性。
图2为根据本发明一些实施例的半导体封装结构500b的横截面示意图。以下实施例的元件,有相同或类似于先前参考图1已描述了的,出于简洁而不再重复。
半导体封装结构500a(图1)与半导体封装结构500b之间的不同在于:半导体封装结构500b包括:基座250b。该基座250b包括:焊料屏蔽层216b,覆盖该基座250b的核心基板200a的装置附着面201。该焊料屏蔽层216b可以覆盖直接位于通孔插塞214上的导电迹线206。焊料屏蔽层216b可以防止其下面的导电迹线206的氧化。在一些实施例中,焊料屏蔽层216b具有一个或者多个开口218b以露出装置垫204。另外,焊料屏蔽层216b的开口218b可以与装置垫204隔开距离D。开口218b与装置垫204隔开,以防止设置在晶粒垫204上的半导体结构300的导电结构322与其他的导线和装置垫短路。另外,焊料屏蔽层216b的开口218b可以提供位置来用于半导体装置300的导电结构322接合于其上。
在一些实施例中,焊料屏蔽层216b和220由相同的材料形成。在一些实施例中,焊料屏蔽层216b和核心基板200a由相同材料形成。例如,焊料屏蔽层216b由热固性材料形成,诸如PP树脂。在其他一些实施例中,焊料屏蔽层216b由ABF形成。在一些实施例中,焊料屏蔽层216b可以包括:玻璃纤维223,分散于焊料屏蔽层216b中,以加强焊料屏蔽层216b的强度。
图3为根据本发明一些实施例的半导体封装结构500c的横截面示意图。以下实施例的元件,有相同或类似于先前参考图1已描述了的,出于简洁而不再重复。
半导体封装结构500a(图1)与半导体封装结构500c之间的不同在于:半导体封装结构500c包括:基座250c。另外,没有使用图1和图2中所示的焊料屏蔽层220来制造半导体封装结构500c。换言之,半导体封装结构500c的基座250c可能需要单个焊料屏蔽层(如焊料屏蔽层216a),设置在半导体装置(如半导体装置300)与基座250c之间。在一些实施例中,基座250c包括:核心基板200b,装置垫204,导电插塞结构235以及该焊料屏蔽层216a。在一些实施例中,该基座250c包括:印刷电路板(PCB)。
在一些实施例中,图3也用于示意制造基座250c的方法的一个示例性实施例。
在一些实施例中,如图3所示,提供基座250c的核心基板200b。该核心基板200b包括:装置附着面201和焊料凸块附着面203,其中该装置附着面201以及该焊料凸块附着面203互为相反面。该核心基板200b的装置附着面201用于半导体装置300设置于其上。该核心基板200b的焊料凸块附着面203用于焊料凸块结构226设置于其上。在一些实施例中,核心基板200a由热固性材料形成。在一些实施例中,核心基板200b由树脂基材料形成。例如,核心基板200b可以由纸质酚醛树脂、复合环氧树脂、聚酰亚胺树脂、BT树脂或者PP树脂形成。在一些实施例中,核心基板200b包括:玻璃纤维205,分散于核心基板200b中,从而加强基座250c的强度。在一些实施例中,玻璃纤维205是可选的。
在一些实施例中,如图3所示,沟槽(trench)236形成于核心基板200b的一部分中,并且接近核心基板200b的装置附着面201。沟槽236可以从核心基板200b的装置附着面201向下延伸。在一些实施例中,沟槽236通过激光钻孔工艺或者化学蚀刻工艺,以及接着的清洗工艺(如除污工艺)来形成。
在一些实施例中,如图3所示,在沟槽236形成之后,分别形成基座250c的导电插塞结构235以填充沟槽236。换言之,形成的导电插塞结构235穿过核心基板200b的一部分。另外,装置垫204形成于核心基板200b的装置附着面201上。在一些实施例中,装置垫204与导电插塞结构235同时形成。在一些实施例中,每个导电插塞结构235具有顶部232和连接至该顶部232的底部234。每个导电插塞结构235的顶部232可以形成于核心基板200b的装置附着面201上。每个导电插塞结构235的底部234可以嵌入于基座250c中并且被核心基板200b围绕。在一实施例中,导电插塞结构235与装置垫204通过电镀工艺及接着的图案化工艺来形成。
接着,如图3所示,形成覆盖核心基板200b的装置附着面201的焊料屏蔽层216a。该焊料屏蔽层216a可以覆盖导电插塞结构235。该焊料屏蔽层216a可以防止其下面的导电插塞结构235被氧化。在一些实施例中,焊料屏蔽层216a具有一个或更多的开口218a,以露出装置垫204。另外,焊料屏蔽层216a的开口218a与装置垫204隔开距离D。开口218a与装置垫204隔开以防止装置垫204上设置的半导体装置300的导电结构322与其他导线和装置垫短路。另外,焊料屏蔽层216a的开口218a可以提供位置用于半导体装置300的导电结构322接合于其上。在一些实施例中,焊料屏蔽层216a包括:耐浸焊材料。在一些实施例中,焊料屏蔽层216a可以包括:光固化材料,诸如光可成像焊料屏蔽材料。在一些实施例中,焊料屏蔽层216a可以包括:焊料屏蔽或者绝缘材料,其中绝缘材料包括:聚酰亚胺、ABF、环氧树脂、PMMA树脂、含环氧树脂和PPMA树脂的复合物,或者PP树脂。在一些实施例中,焊料屏蔽层216a和核心基板200b可以由不同材料形成。在一些实施例中,焊料屏蔽层216a可以由涂布、印刷工艺、粘附工艺、层压工艺或另一恰当的工艺来形成。
在其他的一些实施例中,半导体封装结构500c的焊料屏蔽层216a可以由图2中所示的焊料屏蔽层216b替换。在一些实施例中,焊料屏蔽层216b与核心基板200b可以由相同的材料形成。
接着,如图3所示,在形成焊料屏蔽层216a之后,于核心基板200b的一部分中形成沟槽240,并且该沟槽240接近核心基板200b的焊料凸块附着面203。沟槽240与对应的沟槽236对齐。沟槽240可以从核心基板200b的焊料凸块附着面203向上延伸。另外,每个导电插塞结构235的底部234均暴露于对应沟槽240的底部。在一些实施例中,通过激光钻孔工艺或者化学蚀刻工艺,以及接着的清洗工艺(如除污工艺)来形成沟槽240。在执行上述的工艺之后,形成基座250c,如根据本发明实施例的图3所示。
在一些实施例中,通过电镀工艺在装置垫204和每个导电插塞结构235的底部234上形成Ni/Au层结构207。在一些实施例中,该Ni/Au层结构207是可选的。
在一些实施例中,如图1所示,半导体装置300通过接合工艺以其主动面面向基座250c的方式来安装于基座250c的核心基板200b的装置附着面201上。在一些实施例中,焊料凸块结构226形成于对应的导电插塞结构235的底部234上。另外,形成的焊料凸块结构226可以填充核心基板200b的沟槽240,并且电性连接至对应的导电插塞结构235的底部234。因此,导电插塞结构235的底部234可以充当基座250c的凸块垫。在一些实施例中,凸块垫(即导电插塞结构235的底部234)的表面242位于核心基板200b的装置附着面201与焊料凸块结构226之间。由于基座250a的凸块垫为导电插塞结构235的底部234,因此凸块垫(即导电插塞结构235的底部234)的边界233为导电插塞结构235的边界或对齐导电插塞结构235的边界。在一些实施例中,焊料凸块结构226可以通过沉积工艺和图案化工艺,或者印刷工艺/球附着工艺,来形成于对应的导电插塞结构235的底部234上。
在一些实施例中,导电插塞结构235的底部234充当基座250c的凸块垫。形成的焊料凸块结构226(如焊球)可以从焊料凸块附着面203延伸进核心基板200b的一部分,以电性连接至对应的凸块垫(即导电插塞结构235的底部234)。制造半导体封装结构500c的基座250c,而没有在核心基板200b的焊料凸块结构302上形成额外的焊料屏蔽层。因此,半导体封装结构500c可以需要设置在核心基板200b的装置附着面201上的单个焊料屏蔽层(如焊料屏蔽层216a或216b)。在焊料凸块结构与核心基板的焊料凸块附着面上的焊料层之间的界面处形成的破裂问题可以得到避免。
本实施例提供了一种半导体封装结构。该半导体封装结构包括:基座(base),其中该基座包括:核心基板,具有装置附着面和相对于该装置附着面的焊料凸块附着面。该半导体封装结构的基座包括:第一焊料屏蔽层,设置在该焊料凸块附着面上;以及第二焊料屏蔽层,设置在该装置附着面上。在一些实施例中,第一焊料屏蔽层和核心基板由第一材料形成,第二焊料屏蔽层由第二材料形成。在一些实施例中,第一焊料屏蔽层覆盖核心基板的焊料凸块附着面,并且第一焊料屏蔽层的形成材料相同或者类似于核心基板的材料(如热固性材料)。第一焊料屏蔽层有助于平衡由于核心基板与第二焊料屏蔽层之间不匹配的CTE而施加在核心基板上的应力,其中第二焊料屏蔽层设置在该核心基板的装置附着面上。因此,可以改善半导体封装结构的可靠性。另外,在焊料屏蔽层与焊料凸块附着面上的焊料凸块结构之间的界面处形成的破裂问题可以得到避免。
在一些实施例中,核心基板,焊料凸块附着面上的第一焊料屏蔽层,以及装置附着面上的第二焊料屏蔽层可以由相同的材料形成,例如热固性材料。第一焊料屏蔽层与第二焊料屏蔽层可以进一步降低核心基板与分别设置在装置附着面和焊料凸块附着面上的焊料屏蔽层之间的CTE不匹配。因此,可以改善半导体封装结构的热循环可靠性。
在一些实施例中,半导体封装结构的基座包括:导电插塞结构,形成为从核心基板的装置附着面延伸进核心基板的一部分中。导电插塞结构可以具有顶部和连接至该顶部的底部。该导电插塞结构的顶部形成于核心基板的装置附着面上,并且充当导电迹线。导电插塞结构的底部形成为嵌入于核心基板中,并且没有从核心基板突出。在一些实施例中,导电插塞结构的底部,接近核心基板的焊料凸块附着面,充当基座的凸块垫。焊料凸块结构(如焊球)形成为从焊料凸块附着面延伸进核心基板的一部分中,以电性连接对应的凸块垫。因此,半导体封装结构可以需要设置在核心基板的装置附着面上的单个屏蔽层。形成在焊料凸块结构与焊料凸块附着面上的焊料屏蔽层之间的界面处的破裂问题可以得到避免。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (24)
1.一种半导体封装结构,其特征在于,包括:
核心基板,由第一材料形成,并且具有相对的装置附着面与焊料凸块附着面;
凸块垫,设置在该焊料凸块附着面上;
第一焊料屏蔽层,由该第一材料形成,并且覆盖该核心基板的该焊料凸块附着面以及该凸块垫的一部分;以及
第二焊料屏蔽层,覆盖该核心基板的该装置附着面,其中该第二焊料屏蔽层由第二材料形成。
2.如权利要求1所述的半导体封装结构,其特征在于,该第二材料不同于该第一材料。
3.如权利要求2所述的半导体封装结构,其特征在于,该第一材料包括:热固性材料,以及该第二材料包括:光固化材料。
4.如权利要求1所述的半导体封装结构,其特征在于,该第一材料包括:聚丙烯树指或者ABF(Ajinomoto build-up film)树脂。
5.如权利要求1所述的半导体封装结构,其特征在于,该核心基板以及该第一焊料屏蔽层均包括:分散于其中的玻璃纤维。
6.如权利要求1所述的半导体封装结构,其特征在于,该第二材料包括:光可成像焊料屏蔽材料。
7.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:
第一导电迹线,设置在该装置附着面上并且被该第一焊料屏蔽层覆盖;
第二导电迹线,设置在该凸块附着面上并且被该第二焊料屏蔽层覆盖;以及
通孔插塞,穿过该核心基板并电性连接该第一导电迹线与该第二导电迹线。
8.如权利要求1所述的半导体封装结构,其特征在于,该凸块垫从该第一焊料屏蔽层的第一开口中露出,并且该第一开口相邻于该凸块垫。
9.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:
装置垫,设置在该核心基板的该装置附着面上,其中该装置垫从该第二焊料屏蔽层的第二开口中露出并且与该第二开口以一距离隔开。
10.一种半导体封装结构,其特征在于,包括:
核心基板,具有第一表面与相对于该第一表面的第二表面;
第一焊垫,设置在该核心基板的该第一表面上;
焊料屏蔽层,覆盖该核心基板的该第一表面;以及
导电插塞结构,具有顶部和底部,其中该顶部位于该核心基板的该第一表面上,其中该底部位于该第一表面与该第二表面之间。
11.如权利要求10所述的半导体封装结构,其特征在于,该核心基板包括:沟槽,形成为从该核心基板的该第二表面延伸进该核心基板的一部分中,以及该导电插塞结构的底部暴露于该沟槽的底部。
12.如权利要求10所述的半导体封装结构,其特征在于,该导电插塞结构覆盖该核心基板的该第一表面并且延伸进该核心基板内。
13.如权利要求10所述的半导体封装结构,其特征在于,该底部充当接近该第二表面的第二焊垫。
14.如权利要求10所述的半导体封装结构,其特征在于,该核心基板与该焊料屏蔽层由不同或者相同的材料形成。
15.如权利要求10所述的半导体封装结构,其特征在于,形成该核心基板的材料包括:热固性材料,以及形成该焊料屏蔽层的材料包括:光固化材料。
16.如权利要求10所述的半导体封装结构,其特征在于,形成该核心基板的材料包括:聚丙烯树指或者ABF(Ajinomoto build-up film),及/或,该核心基板以及该第一焊料屏蔽层均包括:分散于其中的玻璃纤维。
17.如权利要求10所述的半导体封装结构,其特征在于,形成该焊料屏蔽层的材料包括:光可成像焊料屏蔽材料。
18.一种半导体封装结构,其特征在于,包括:
基座,其中该基座包括:
核心基板,由第一材料形成,并且具有相对的装置附着面与焊料凸块附着面;
第一焊料屏蔽层,由该第一材料形成并且覆盖该核心基板的该焊料凸块附着面;以及
凸块垫,设置在该核心基板的该焊料凸块附着面上,其中该凸块垫从该第一焊料屏蔽层的开口中露出;
以及焊料凸块结构,接触该第一焊料屏蔽层并且电性连接至该凸块垫。
19.如权利要求18所述的半导体封装结构,其特征在于,进一步包括:
半导体装置,设置在该核心基板的该装置附着面上并且电性耦接至该基座的装置垫,其中该装置垫设置在该基座的该装置附着面上。
20.如权利要求19所述的半导体封装结构,其特征在于,该基座包括:第二焊料屏蔽层,覆盖该基座的该装置附着面,并且设置在该半导体装置与该基座之间。
21.如权利要求20所述的半导体封装结构,其特征在于,进一步包括:
第一导电迹线,设置在该装置附着面上并且被该第一焊料屏蔽层覆盖;
第二导电迹线,设置在该凸块附着面上并且被该第二焊料屏蔽层覆盖;以及
通孔插塞,穿过该核心基板,其中该通孔插塞电性连接至该第一导电迹线与该第二导电迹线。
22.如权利要求20所述的半导体封装结构,其特征在于,该第二焊料屏蔽层由不同于该第一材料的第二材料形成。
23.如权利要求22所述的半导体封装结构,其特征在于,该第一材料包括:聚丙烯树指或者ABF(Ajinomoto build-up film),及或,该第一材料包括:分散于其中的玻璃纤维。
24.如权利要求22所述的半导体封装结构,其特征在于,该第二材料包括:光可成像焊料屏蔽材料。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110858571A (zh) * | 2018-08-22 | 2020-03-03 | 三星电子株式会社 | 半导体封装件 |
WO2023130573A1 (zh) * | 2022-01-07 | 2023-07-13 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
Families Citing this family (1)
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US10748857B2 (en) * | 2018-09-11 | 2020-08-18 | Micron Technology, Inc. | Die features for self-alignment during die bonding |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090302485A1 (en) * | 2008-06-05 | 2009-12-10 | Powertech Technology Inc. | Laminate substrate and semiconductor package utilizing the substrate |
CN102157476A (zh) * | 2010-03-04 | 2011-08-17 | 日月光半导体制造股份有限公司 | 具有单侧基板设计的半导体封装及其制造方法 |
US20130251967A1 (en) * | 2012-03-22 | 2013-09-26 | Nvidia Corporation | System, method, and computer program product for controlling warping of a substrate |
US9171739B1 (en) * | 2014-06-24 | 2015-10-27 | Stats Chippac Ltd. | Integrated circuit packaging system with coreless substrate and method of manufacture thereof |
CN105593986A (zh) * | 2013-09-27 | 2016-05-18 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW471148B (en) | 2000-11-21 | 2002-01-01 | Phoenix Prec Technology Corp | Integrated circuit packaging substrate structure and the manufacturing method thereof |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
US6960822B2 (en) | 2002-08-15 | 2005-11-01 | Advanced Semiconductor Engineering, Inc. | Solder mask and structure of a substrate |
TWI304255B (en) | 2006-08-31 | 2008-12-11 | Phoenix Prec Technology Corp | A capacitance element embedded in semiconductor package substrate structure and method for fabricating tme same |
KR100867148B1 (ko) | 2007-09-28 | 2008-11-06 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
TWI370711B (en) | 2009-01-06 | 2012-08-11 | Nan Ya Printed Circuit Board | Fine line structure with improved adhesion and method for fabricating the same |
US8786062B2 (en) | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
KR20150002492A (ko) | 2013-06-28 | 2015-01-07 | 쿄세라 서킷 솔루션즈 가부시키가이샤 | 배선 기판 |
US9521752B2 (en) | 2014-09-19 | 2016-12-13 | Harris Corporation | Method of making an electronic device having a thin film resistor formed on an LCP solder mask and related devices |
TWI554174B (zh) * | 2014-11-04 | 2016-10-11 | 上海兆芯集成電路有限公司 | 線路基板和半導體封裝結構 |
-
2017
- 2017-06-30 US US15/638,472 patent/US10276465B2/en active Active
- 2017-08-30 CN CN201710762051.1A patent/CN107887348A/zh not_active Withdrawn
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- 2017-09-05 EP EP21200916.1A patent/EP3971963A1/en active Pending
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090302485A1 (en) * | 2008-06-05 | 2009-12-10 | Powertech Technology Inc. | Laminate substrate and semiconductor package utilizing the substrate |
CN102157476A (zh) * | 2010-03-04 | 2011-08-17 | 日月光半导体制造股份有限公司 | 具有单侧基板设计的半导体封装及其制造方法 |
US20130251967A1 (en) * | 2012-03-22 | 2013-09-26 | Nvidia Corporation | System, method, and computer program product for controlling warping of a substrate |
CN105593986A (zh) * | 2013-09-27 | 2016-05-18 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
US9171739B1 (en) * | 2014-06-24 | 2015-10-27 | Stats Chippac Ltd. | Integrated circuit packaging system with coreless substrate and method of manufacture thereof |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110858571A (zh) * | 2018-08-22 | 2020-03-03 | 三星电子株式会社 | 半导体封装件 |
CN110858571B (zh) * | 2018-08-22 | 2024-05-17 | 三星电子株式会社 | 半导体封装件 |
WO2023130573A1 (zh) * | 2022-01-07 | 2023-07-13 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
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