CN110858571B - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN110858571B
CN110858571B CN201910097843.0A CN201910097843A CN110858571B CN 110858571 B CN110858571 B CN 110858571B CN 201910097843 A CN201910097843 A CN 201910097843A CN 110858571 B CN110858571 B CN 110858571B
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China
Prior art keywords
layer
connection member
pad
under bump
plating
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CN201910097843.0A
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CN110858571A (zh
Inventor
李在彦
陈韩娜
郑泰成
高永宽
卞贞洙
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本公开提供一种包括有机中介器的半导体封装件，所述包括有机中介器的半导体封装件包括：半导体芯片；连接构件，位于所述半导体芯片上并且包括焊盘层、重新分布层以及绝缘层；结合构件，位于所述半导体芯片和所述焊盘层之间；表面处理层，位于所述焊盘层上并且包括至少一个金属层；以及凸块下金属(UBM)层，嵌入在所述连接构件中。所述UBM层包括：UBM焊盘、位于所述UBM焊盘上的至少一个镀层以及UBM过孔。所述表面处理层仅设置在所述焊盘层的一个表面上，并且所述镀层仅设置在所述UBM焊盘的一个表面上，并且所述镀层的侧表面的至少一部分与所述绝缘层的围绕所述镀层的侧表面间隔开。

Description

半导体封装件
本申请要求于2018年8月22日在韩国知识产权局提交的第10-2018-0097953号韩国专利申请的优先权的权益，该韩国专利申请的公开内容通过引用被全部包含于此。
技术领域
本公开涉及一种包括有机中介器的半导体封装件。
背景技术
随着高端设备和高带宽存储器(HBM)的采用，中介器市场正在增长。目前，硅已被用作中介器中的主要材料，但正在开发用于大规模和低成本制造的玻璃和有机方法。中介器到设备的主板的连接部分称为凸块下金属(UBM)层，并且连接部分的可靠性在很大程度上受这种UBM层的结构影响，因此存在优化这种UMB层的结构的需求。
具体地，已经对这种UBM层进行了各种表面处理以改善结合可靠性。这种表面处理主要使用无电镀覆。在这种情况下，表面处理层设置在焊盘的侧表面上以及焊盘的上表面上，因此，在UBM层结合到焊料之后会发生各种缺陷。
发明内容
本公开的一方面可提供一种包括有机中介器的半导体封装件，该包括有机中介器的半导体封装件能够简化工艺并防止在表面处理层和UBM层中的缺陷的发生。
由本公开提出的解决方案中的一个可通过电解镀覆在连接构件的上部和下部处的焊盘的仅一个表面上分别形成表面处理层和UBM层的镀层，并且可使用逆镀覆法形成UBM层的镀层。
根据本公开的一方面，一种包括有机中介器的半导体封装件可包括半导体芯片、连接构件、结合构件、表面处理层以及凸块下金属层，所述半导体芯片具有其上设置有连接焊盘的有效表面，所述连接构件设置在所述半导体芯片的所述有效表面上并且包括设置在所述连接构件的上表面上的焊盘层、电连接到所述连接焊盘的重新分布层以及绝缘层，所述结合构件设置在所述半导体芯片的所述连接焊盘和所述连接构件的所述焊盘层之间以将所述半导体芯片与所述连接构件连接，所述表面处理层设置在所述连接构件的所述焊盘层的上表面上并且包括至少一个金属层，所述凸块下金属(UBM)层嵌入在所述连接构件中并且电连接到所述连接构件的所述重新分布层。所述UBM层可包括：UBM焊盘，嵌入在所述连接构件的所述绝缘层中；至少一个镀层，设置在所述UBM焊盘上；以及UBM过孔，贯穿所述连接构件的所述绝缘层的至少一部分并且将所述连接构件的所述重新分布层与所述UBM焊盘电连接。所述表面处理层可仅设置在所述焊盘层的面对所述结合构件的一个表面上，并且所述UBM层的所述镀层可仅设置在所述UBM焊盘的与所述UBM过孔相对的一个表面上，并且所述UBM层的所述镀层的侧表面的至少一部分可与所述连接构件的所述绝缘层的围绕所述UBM层的所述镀层的侧表面间隔开。
根据本公开的另一方面，一种半导体封装件可包括：半导体芯片，具有有效表面，所述有效表面上设置有连接焊盘；连接构件，设置在所述半导体芯片的所述有效表面上，并且所述连接构件包括设置在所述连接构件的上表面上的焊盘层、电连接到所述连接焊盘的重新分布层以及绝缘层；结合构件，设置在所述半导体芯片的所述连接焊盘和所述连接构件的所述焊盘层之间，以将所述半导体芯片与所述连接构件连接；表面处理层，设置在所述连接构件的所述焊盘层的上表面上并且包括至少一个金属层；以及凸块下金属(UBM)层，嵌入在所述连接构件中并且电连接到所述连接构件的所述重新分布层，其中，所述凸块下金属层包括：凸块下金属焊盘，嵌入在所述连接构件的所述绝缘层中；至少一个镀层，设置在所述凸块下金属焊盘上；以及凸块下金属过孔，贯穿所述连接构件的所述绝缘层的至少一部分并且将所述连接构件的所述重新分布层与所述凸块下金属焊盘电连接，并且所述表面处理层均仅设置在所述焊盘层的面对所述结合构件的一个表面上并且包括包含金(Au)的第一电解镀层和包含镍(Ni)的第二电解镀层，所述凸块下金属层的所述镀层仅设置在所述凸块下金属焊盘的与所述凸块下金属过孔相对的一个表面上并且包括包含金(Au)的第三电解镀层和包含镍(Ni)的第四电解镀层。
附图说明
通过以下结合附图进行的详细描述，本公开的以上和其他方面、特征及优点将被更清楚地理解，在附图中：
图1是示意性示出电子装置系统的示例的框图；
图2是示意性示出电子装置的示例的透视图；
图3是示意性示出3D BGA封装件安装在电子装置的主板上的情况的截面图；
图4是示意性示出2.5D硅中介器封装件安装在主板上的情况的截面图；
图5是示意性示出2.5D有机中介器封装件安装在主板上的情况的截面图；
图6是示意性示出包括有机中介器的半导体封装件的示例的截面图；
图7是示意性示出包括有机中介器的半导体封装件的另一示例的放大图；
图8A至图8J是示意性示出形成图6的包括有机中介器的半导体封装件的工艺的示例的示图；
图9是示意性示出包括有机中介器的半导体封装件的另一示例的截面图；
图10是示意性示出包括有机中介器的半导体封装件的另一示例的截面图；
图11是示意性示出包括有机中介器的半导体封装件的另一示例的截面图；以及
图12是示意性示出包括有机中介器的半导体封装件的另一示例的截面图。
具体实施方式
现将在下文中参照附图详细描述本公开的示例性实施例。
电子装置
图1是示意性示出电子装置系统的示例的框图。
参照图1，电子装置1000可容纳主板1010。主板1010物理连接和/或电连接到芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件也可通过各种信号线1090结合到将在以下描述的其他组件。
芯片相关组件1020可包括：存储器芯片，诸如易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)和闪存；应用处理器芯片，诸如中央处理器(例如，CPU)、图形处理器(例如，GPU)、数字信号处理器、密码处理器、微处理器和微控制器；以及逻辑芯片，诸如模拟数字转换器和专用集成电路(ASIC)等，但是不仅包括这些组件。因此，不言而喻，可包括其他类型的芯片相关组件。此外，不言而喻，芯片相关组件1020可彼此组合。
网络相关组件1030可包括根据以下协议操作的组件：Wi-Fi(IEEE 802.11族等)、WiMAX(IEEE 802.16族等)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPS、GPRS、CDMA、TDMA、DECT、蓝牙、3G、4G和5G以及被指定为下一代的任何其他无线标准或者协议或者有线标准或者协议，但网络相关组件1030不仅包括这些组件。此外，不言而喻，网络相关组件1030可与芯片相关组件1020组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等，但不仅包括这些组件。因此，其他组件1040可包括用于各种其他目的的无源组件等。此外，不言而喻，其他组件1040可与芯片相关组件1020和/或网络相关组件1030组合。
根据电子装置1000的类型，电子装置1000可包括可物理连接和/或电连接到主板1010或者可不物理连接和/或电连接到主板1010的其他组件。其他组件的示例可包括相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储装置(例如，硬盘驱动器)(未示出)、光盘(CD)(未示出)、数字通用光盘(DVD)(未示出)等，但是其他组件不仅包括这些组件。此外，其他组件1040可根据电子装置1000的类型而包括用于各种其他目的的其他组件等。
电子装置1000可以为智能电话、个人数字助理、数字摄像机、数码相机、网络系统、计算机、监视器、平板电脑、膝上型电脑、上网本、电视机、视频游戏机、智能手表、汽车组件等。然而，电子装置1000可不限于此。除了这些组件外，不言而喻，电子装置1000可以是用于处理数据的任何其他电子装置。
图2是示意性示出电子装置的示例的透视图。
参照图2，半导体封装件应用于如上所述的各种电子装置以用于各种目的。例如，母板1110可容纳在智能电话1100的主体1101中，并且各种组件1120可物理连接和/或电连接到母板1110。此外，可物理连接和/或电连接到母板1110或者可不物理连接和/或电连接到母板1110的其他组件(诸如相机1130)可容纳在主体1101中。组件1120中的一些可以是芯片相关组件，并且组件1120中的一些可以是中介器封装件1121。不言而喻，电子装置不限于智能电话1100，而可以是如上所述的其他电子装置。
包括中介器的半导体封装件
通常，大量微电子电路可被集成在半导体芯片中，但半导体芯片本身可能不能作为半导体的成品，并且可能由于外部的物理或化学冲击而损坏。因此，可能不会按原样使用半导体芯片本身。为此，半导体芯片可被封装并因此已经在封装状态下用于电子装置等。
需要半导体封装的原因是：在电连接方面，半导体芯片和电子装置的主板之间存在电路宽度的差异。具体地，在半导体芯片的情况下，连接焊盘的尺寸和连接焊盘之间的间距非常小。另一方面，在用于电子装置的主板的情况下，组件安装焊盘的尺寸和组件安装焊盘之间的间距可比半导体芯片的连接焊盘的尺寸和连接焊盘之间的间距大得多。因此，由于难以将半导体芯片直接安装在主板上，因此需要存在一种能够缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
在下文中，将参照附图更详细地描述通过这种封装技术制造的包括有机中介器的半导体封装件。
图3是示意性示出3D BGA封装件安装在电子装置的主板上的情况的截面图。
由于诸如半导体芯片的图形处理单元(GPU)的专用集成电路(ASIC)中的每个芯片非常昂贵，因此以高良率进行封装非常重要。为此，在安装半导体芯片之前，可首先制备能够使数千到数十万个连接焊盘重新分布的球栅阵列(BGA)基板2210等，然后，诸如GPU 2220的昂贵的半导体芯片可通过表面安装技术(SMT)等安装在BGA基板2210上并封装，并最终安装在主板2110上。
另一方面，在GPU 2220的情况下，需要大大减小到诸如高带宽存储器(HBM)的存储器的信号路径。为此，诸如HBM 2240的半导体芯片可安装在中介器2230上然后被封装，并且可通过堆叠在封装件上而被使用，其中，GPU 2220以层叠封装(POP)形式安装在该封装件上。然而，在这种情况下，会存在装置的厚度变得太厚并且难以大大地减小信号路径的问题。
图4是示意性示出2.5D硅中介器封装件安装在主板上的情况的截面图。
为了解决上述问题，包括硅中介器的半导体封装件2310可通过将诸如GPU 2220的第一半导体芯片和诸如HBM 2240的第二半导体芯片并排地表面安装在硅中介器2250上并且封装第一半导体芯片和第二半导体芯片的2.5D中介器技术制造。在这种情况下，具有数千至数十万个连接焊盘的GPU 2220和HBM 2240可通过中介器2250重新分布，并且可通过最小路径电连接。如果包括这种硅中介器的半导体封装件2310再次安装在BGA基板2210等上并且分布，半导体封装件2310可最终被安装在主板2110上。然而，在硅中介器2250的情况下，非常难以形成硅通孔(TSV)，并且制造成本也相当大，这对于大规模和低成本制造是不利的。
图5是示意性示出2.5D有机中介器封装件安装在主板上的情况的截面图。
作为用于解决上述问题的方法，可考虑使用有机中介器2260代替硅中介器2250。例如，包括有机中介器的半导体封装件2320可通过将诸如GPU 2220的第一半导体芯片和诸如HBM 2240的第二半导体芯片并排地表面安装在有机中介器2260上并且封装第一半导体芯片和第二半导体芯片的2.5D中介器技术制造。在这种情况下，具有数千至数十万个连接焊盘的GPU 2220和HBM 2240可通过中介器2260重新分布，并且可通过最小路径电连接。如果包括这种有机中介器的半导体封装件2320再次安装在BGA基板2210等上并且分布，半导体封装件2320可最终被安装在主板2110上。另外，这对于大规模和低成本制造是有利的。
另一方面，包括有机中介器的半导体封装件2320通过在中介器2260上安装芯片2220和2240然后将芯片2220和2240模制或密封的封装工艺制造。这是因为，如果不执行模制工艺，中介器2260上的芯片2220和2240不会被处理，并且不会连接到BGA基板2210等。因此，通过模制保持了中介器2260上的芯片2220和2240的刚度。然而，如上所述，当执行模制工艺时，由于中介器2260与芯片2220和2240的密封构件之间的热膨胀系数(CTE)的不匹配等，可能出现诸如发生翘曲、底部填充树脂填充性能劣化以及半导体芯片和密封构件之间发生裂纹的问题。
图6是示意性示出包括有机中介器的半导体封装件的示例的截面图。
参照图6，根据示例的包括有机中介器的半导体封装件100A可包括：半导体芯片111、112和113，均具有其上设置有连接焊盘111P、112P和113P的有效表面；密封构件160，密封半导体芯片111、112和113的至少一些部分；连接构件120，设置在半导体芯片111、112和113的有效表面上并包括重新分布层122、过孔123和绝缘层121，重新分布层122分别电连接到连接焊盘111P、112P和113P，过孔123连接到重新分布层122；结合构件115，设置在半导体芯片111、112和113的连接焊盘111P、112P和113P与连接构件120的焊盘层122c之间，以将半导体芯片111、112和113结合到连接构件120；表面处理层130，设置在连接构件120的焊盘层122c的上表面上；UBM层140，嵌入在连接构件120中并且电连接到连接构件120的重新分布层122；以及电连接结构150，连接到UBM层140。UBM层140可包括UBM焊盘142、UBM过孔143、第一镀层145和第二镀层146以及金属层149，UBM焊盘142嵌入在连接构件120的绝缘层121中，UBM过孔143嵌入在连接构件120的绝缘层121中以将连接构件120的重新分布层122与UBM焊盘142电连接，第一镀层145和第二镀层146嵌入在连接构件120的绝缘层121中并且设置在UBM焊盘142上，金属层149位于第一镀层145和第二镀层146上。
连接构件120可在其上部连接到结合构件115并且在其下部连接到电连接结构150。结合构件115可通过连接构件120的最上面的焊盘层122c连接，并且电连接结构150可通过连接构件120下方的UBM层140连接。表面处理层130可包括第一表面处理层132和第二表面处理层134，第一表面处理层132和第二表面处理层134可分别包括与UBM层140的第一镀层145和第二镀层146相同的电解金属层。即，表面处理层130以及第一镀层145和第二镀层146可包括相同材料的金属层，并且金属层堆叠的结构可相同。例如，第一表面处理层132和第一镀层145可以是金(Au)镀层，并且可防止焊盘层122c和UBM焊盘142的氧化。第二表面处理层134和第二镀层146可均利用与第一表面处理层132和第一镀层145不同的材料形成，并且可以是例如镍(Ni)镀层。第二表面处理层134可防止由于第一表面处理层132和焊盘层122c而形成金属间化合物，并且第二镀层146可防止由于第一镀层145和UBM焊盘142而形成金属间化合物。然而，表面处理层130与第一镀层145和第二镀层146可在平面上具有不同的尺寸或直径。表面处理层130连接到相对小的结合构件115，因此可具有比第一镀层145和第二镀层146小的直径。
焊盘层122c上的表面处理层130以及UBM层140的第一镀层145和第二镀层146中的全部通过电解镀覆形成。因此，与现有的无电镀覆型的结构不同，表面处理层130不延伸至焊盘层122c的侧表面上而是仅设置在焊盘层122c的上表面上，第一镀层145和第二镀层146不延伸至UBM焊盘142的侧表面上而是仅设置在UBM焊盘142的下表面上。因此，可防止出现通过沿着焊盘层122c的侧表面润湿结合构件115和沿着UBM焊盘142的侧表面润湿电连接结构150而形成的诸如柯肯德尔(Kirkendall)空隙和焊料的消耗的缺陷。
此外，在现有的中介器中，执行在载体上形成重新分布层、将裸片附着在重新分布层上并且对裸片进行模制的封装工艺，然后执行将封装件从载体分离、在封装件的接触载体的下表面上形成过孔、执行暴露和镀覆等的工艺，从而形成UBM层。这种常规方法最后形成UBM层，并且通常称为后设UBM层法。在后设UBM层法中，仅由于封装件中的翘曲问题而难以进行该工艺，因此需要使用单独的载体，并且存在构建用于UBM层工艺的专用生产线的负担。此外，由于通过低洁净度封装线的产品必须再次经历高洁净度的暴露和镀覆工艺，因此存在工艺品质和良率降低的风险。通常，当应用后设UBM层法时，UBM焊盘形成在绝缘构件上或绝缘构件上的钝化层上。
另一方面，如将稍后所述的，根据示例的半导体封装件100A通过先设UBM层法制造。也就是说，UBM层140可在形成连接构件120之前首先在形成连接构件120的生产线中形成。因此，可省略用于形成UBM层的专用生产线，并且UBM层可按照面板级形成，因此可简化工艺。具体地，由于首先形成对应于UBM焊盘142的表面处理层的第一镀层145和第二镀层146,这方式通常称为逆镀覆法，因此由于镀覆引线(plating lead line)，可在没有设计约束的情况下形成UBM层140，因此可实现精细的节距。
在根据示例的半导体封装件100A的情况下，UBM过孔143的与连接构件120的重新分布层122接触的上表面的宽度大于UBM过孔143的与UBM焊盘142接触的底表面的宽度。这里，宽度是基于截面图确定的。当如在常规方法中应用后设UBM层法时，UBM过孔的上表面的宽度通常小于其下表面的宽度。另一方面，在根据示例的半导体封装件100A的情况下，应用先设UBM层法，并且UBM过孔143可形成为UBM过孔143的上表面的宽度宽于UBM过孔143的下表面的宽度的所谓的倒梯形形状。另外，与连接构件120的重新分布层122和过孔123相似，可形成UBM焊盘142和UBM过孔143，因此UBM过孔143可以是填充过孔。
在下文中，将更详细地描述根据示例的半导体封装件100A中的每个组件。
例如，半导体芯片111、112和113可以是：处理器芯片，诸如中央处理器(例如，CPU)、图形处理器(例如，GPU)、现场可编程门阵列(FPGA)、数字信号处理器、密码处理器、微处理器和微控制器；逻辑芯片，诸如模数转换器和专用集成电路(ASIC)；或者存储器芯片，诸如易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM、闪存)和高带宽存储器(HBM)。另外，芯片可彼此组合地布置。作为非限制性示例，第一半导体芯片111和第三半导体芯片113可以是诸如HBM的存储器芯片，第二半导体芯片112可以是诸如AP的处理器芯片，但不限于此。半导体芯片111、112和113可通过连接构件120彼此电连接。
半导体芯片111、112和113均可以是数百个至数百万个器件集成在一个芯片中的集成电路(IC)。在这种情况下，可使用硅(Si)、锗(Ge)、砷化镓(GaAs)等作为每个主体的基体材料。可在每个主体中形成各种电路。半导体芯片111、112和113中的每个的连接焊盘111P、112P和113P用于将各个半导体芯片111、112和113电连接到其他组件，并且作为连接焊盘111P、112P和113P的形成材料，可使用诸如铝(Al)的导电材料而没有任何具体限制。可在每个主体上形成钝化膜，并且钝化膜可具有使连接焊盘111P、112P和113P暴露的多个开口。钝化膜可以是氧化物膜、氮化物膜等并且可以是氧化物膜和氮化物膜的双层。绝缘膜等还可设置在需要的位置。如果需要，重新分布层还可形成在半导体芯片111、112和113的有效表面上，并且凸块111B、112B和113B等可分别连接到连接焊盘111P、112P和113P。凸块111B、112B和113B可利用金属或焊料形成。半导体芯片111、112和113可通过连接焊盘111P、112P和113P和/或凸块111B、112B和113B连接到暴露在连接构件120上的焊盘层122c。诸如焊料和微凸块的结合构件115可用于该连接。半导体芯片111、112和113中的每个可使用已知的底部填充树脂170固定在连接构件120上。
连接构件120使半导体芯片111、112和113中的每个的连接焊盘111P、112P和113P重新分布。具有各种功能的半导体芯片111、112和113的数十至数百个连接焊盘111P、112P和113P可通过连接构件120重新分布，并且可根据功能通过电连接结构物理连接和/或电连接到外部。连接构件120包括：绝缘层121；重新分布层122，形成在绝缘层121上或者绝缘层121中；以及过孔123，贯穿绝缘层121并且使形成在不同层上的重新分布层电连接。连接构件120的层数可大于或小于附图中所示的层数。这种类型的连接构件120可用作2.5D型有机中介器。
连接构件120可包括：最下面的第一绝缘层121a；第二绝缘层121b，嵌入有UBM层140；第三绝缘层121c，位于第二绝缘层121b上；第一重新分布层122a，嵌入在第三绝缘层121c中以与UBM过孔143接触；以及第一过孔123a，穿过第三绝缘层121c的至少一部分并且将第一重新分布层122a与第二重新分布层122b电连接。连接构件120可通过重复地堆叠第三绝缘层121c、第二重新分布层122b和第一过孔123a而构成。另外，连接构件120可包括焊盘层122c，焊盘层122c设置在最上面的绝缘层121上并且与密封构件160和/或底部填充树脂170接触。焊盘层122c可对应于重新分布层122的一部分并且可用作用于安装半导体芯片111、112和113的焊盘。此外，最下面的第一绝缘层121a可用作钝化层，并且可包括与根据示例性实施例的第二绝缘层121b和第三绝缘层121c不同的材料。
作为绝缘层121的材料，可使用有机材料，例如，绝缘材料。在这种情况下，作为绝缘材料，可使用诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂或者将热固性树脂或热塑性树脂与无机填料混合的树脂(例如，ABF(Ajinomoto Build-up Film)等。可选地，可使用诸如可光成像电介质(PID)树脂的感光绝缘材料。也就是说，绝缘层121均可以是感光绝缘层。如果绝缘层121具有感光性能，则绝缘层121可形成为更薄并且过孔123的精细的节距可更容易实现。如果绝缘层121形成为多层，则这些材料可彼此相同，或者可根据需要彼此不同。如果绝缘层121形成为多层，则它们可根据工艺进行一体化，因此它们之间的边界可不明显。
重新分布层122可用于使连接焊盘111P、112P和113P基本上重新分布，并且作为重新分布层122的形成材料，可使用诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)和钛(Ti)或它们的合金的导电材料。重新分布层122可根据对应层的设计执行各种功能。例如，重新分布层122可包括接地(GND)图案、电力(PWR)图案、信号(S)图案等。这里，除了接地(GND)图案、电力(PWR)图案等之外，信号(S)图案可包括例如数据信号图案等的各种信号图案。另外，信号(S)图案可包括过孔焊盘、连接端子焊盘等。表面处理层130可形成在重新分布层122中的焊盘层122c的表面上。
过孔123可使形成在不同层上的重新分布层122等电连接，从而在半导体封装件100A中形成电路径。作为过孔123的形成材料，可使用诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)和钛(Ti)或它们的合金的导电材料。过孔123可完全利用导电材料填充，但不限于此。参照附图，过孔123的截面形状可具有基本上倒梯形形状。
表面处理层130包括第一表面处理层132和第二表面处理层134。第一表面处理层132和第二表面处理层134可以是利用不同的材料形成的层，并且第一表面处理层132可设置在上部上，并且第二表面处理层134可设置在第一表面处理层132和焊盘层122c之间。例如，第一表面处理层132可利用金(Au)形成，并且第二表面处理层134可利用镍(Ni)形成。表面处理层130可仅形成在焊盘层122c的上表面上，以暴露焊盘层122c的侧表面。根据示例性实施例，焊盘层122c的从表面处理层130暴露的侧表面可与底部填充树脂170接触，并且焊盘层122c的侧表面的至少一部分可与结合构件115接触。
UBM层140可改善电连接结构150的连接可靠性，从而改善半导体封装件100A的板级可靠性。UBM层140可包括：UBM焊盘142，在连接构件120的下部处嵌入在第二绝缘层121b中；UBM过孔143，嵌入在第二绝缘层121b中，以将连接构件120的重新分布层122与UBM焊盘142电连接；第一镀层145和第二镀层146，嵌入在第二绝缘层121b中，并且设置在UBM焊盘142的一部分上；以及金属层149，设置在第一镀层145和第一绝缘层121a之间。电连接结构150可设置在第一镀层145上并且设置为向第一绝缘层121a的下部突出。
第一镀层145和第二镀层146可对应于UBM焊盘142的表面处理层。作为第一镀层145和第二镀层146的形成材料，可使用诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)和钛(Ti)或它们的合金的导电材料。例如，第一镀层145可以是金(Au)镀层，并且第二镀层146可以是镍(Ni)镀层。然而，构成第一镀层145和第二镀层146的层数不受限制。在该实施例中，第一镀层145和第二镀层146的材料和堆叠结构可与表面处理层130的材料和堆叠结构相同，但不限于此。
金属层149可以是用于形成第一镀层145和第二镀层146的种子层。金属层149可在制造工艺期间在形成用于形成电连接结构150的开口151时被部分地去除，并且可仅保留在覆盖有第一绝缘层121a的区域中。金属层149可包括导电材料，例如，钛(Ti)层和铜(Cu)层。
电连接结构150可设置在开口151(第一绝缘层121a从其被去除)中，以将半导体封装件100A物理连接和/或电连接到外部。例如，半导体封装件100A可通过电连接结构150安装在电子装置的主板上。因此，电连接结构150的尺寸和直径可大于结合构件115的尺寸和直径。此外，电连接结构150可设置在第一镀层145上，并且开口151可形成为小于第一镀层145，以暴露第一镀层145的一部分。电连接结构150可利用导电材料(例如，焊料)形成，但仅是示例，并且其材料没有具体限制于此。电连接结构150可以是焊盘、焊球、引脚等。电连接结构150可利用多层或单层形成。当电连接结构形成为多层时，电连接结构可包括铜柱和焊料。当电连接结构形成为单层时，电连接结构可包括锡-银焊料或铜，但仅是示例并且不限于此。
电连接结构150的数量、间距、布置形式等没有具体限制，并且本领域技术人员可根据设计规范进行充分修改。例如，根据连接焊盘111P、112P和113P的数量，电连接结构150的数量可以是数十至数千个，并且可具有更多或更少的数量。电连接结构150中的一些可设置在扇出区域中。扇出区域可意味着在设置有半导体芯片111、112和113的区域的外部的区域。也就是说，根据示例的半导体封装件100A可以是扇出型半导体封装件。扇出型封装件可比扇入型封装件可靠，并且可实现很多I/O端子并且促进3D互连。此外，封装件可制造为比球栅阵列(BGA)封装件和栅格阵列(LGA)封装件薄，并且价格竞争力可以是优异的。
密封构件160可保护半导体芯片111、112、113等。密封形式没有具体限制，因此可允许任意的密封形式，只要它可包围半导体芯片111、112和113的至少一部分即可。密封构件160的材料没有具体限制。例如，可使用绝缘材料。在这种情况下，作为绝缘材料，可使用诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂或者将热固性树脂或热塑性树脂与无机填料混合的材料(例如，ABF(Ajinomoto Build-up Film)等)。然而，本公开的绝缘材料的示例不限于此，并且也可使用包括玻璃纤维等的半固化片。可选地，也可使用已知的环氧模封料(EMC)等。
底部填充树脂170可将半导体芯片111、112和113固定在连接构件120上。作为底部填充树脂170，可应用包括环氧树脂等的已知的材料。如果需要，可省略底部填充树脂170。尽管在附图中未示出，但是如果需要，可通过在连接构件120上与半导体芯片111、112和113b并排地设置来封装无源组件。
图7是示意性示出包括有机中介器的半导体封装件的另一示例的截面图。
参照图7，示出了对应于图6的放大图的区域。在该实施例中，设置有电连接结构150的开口151被设置为具有与第一镀层145和第二镀层146的尺寸或宽度相同的尺寸或宽度。因此，第一镀层145的整个下表面从第一绝缘层121a和第二绝缘层121b向下暴露，以与电连接结构150接触。因此，与图6的示例性实施例不同，UBM层140a可通过去除设置在第一绝缘层121a和第一镀层145之间的所有金属层149而不包括金属层149。其他构造与根据上述示例的半导体封装件100A中描述的其他构造基本上相同。
图8A至图8J是示意性示出形成图6的包括有机中介器的半导体封装件的工艺的示例的示图。
参照图8A，制备载体210。载体210可包括芯层211和形成在芯层211上的释放层212。芯层211可以是玻璃、绝缘树脂、无机填料和例如包括玻璃纤维的半固化片。释放层212可包括例如金属(诸如铜(Cu)或钛(Ti))，并且可进行表面处理以易于分离。根据示例性实施例，载体210可以是玻璃载体或者可以是典型的分离芯。
参照图8B，可在载体210上顺序地形成第一绝缘层121a和金属层149。第一绝缘层121a可使用诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂或者诸如可光成像电介质(PID)树脂的感光绝缘材料形成。金属层149可通过溅射工艺形成，并且可利用例如钛(Ti)/铜(Cu)的双层形成。
参照图8C，可在金属层149上形成图案层220，然后可顺序地形成第一镀层145和第二镀层146。图案层220可利用光刻胶层或干膜形成。可通过利用电解镀覆工艺填充图案层220之间的空间来形成第一镀层145和第二镀层146。第一镀层145和第二镀层146可形成在作为种子层的金属层149上。具体地，第一镀层145和第二镀层146可通过电解镀覆形成，并且可防止诸如当通过无电镀覆形成时可能发生的围绕图案的毛刺的缺陷。第一镀层145和第二镀层146可形成为具有相同的尺寸和宽度，但不限于此。
参照图8D，可形成UBM焊盘142以覆盖第一镀层145和第二镀层146，并且可去除图案层220。UBM焊盘142可形成在第一镀层145和第二镀层146上。接下来，可去除图案层220下方的金属层149。
参照图8E，可形成第二绝缘层121b并且可将第二绝缘层121b图案化，从而形成连接到UBM焊盘142的过孔143。第二绝缘层121b可通过层压法或涂覆法形成。过孔143可通过由光刻法、机械钻孔和/或激光钻孔等形成通路孔并且利用导电材料掩埋通路孔来形成。结果，可形成UBM层140。此外，可在第二绝缘层121b上形成第一重新分布层122a。
参照图8F，可进一步在第二绝缘层121b和UBM层140上形成除了第一重新分布层122a以外的组件以形成连接构件120。连接构件120和UBM层140可在同一生产线上连续地形成。绝缘层121可通过层压或涂覆PID等的方法形成。重新分布层122和过孔123可通过使用干膜等形成图案然后利用镀覆法填充图案形成。作为镀覆法，可使用减成工艺、加成工艺、半加成工艺(SAP)、改性半加成工艺(MSAP)等，但镀覆法不限于此。在根据另一示例的工艺中，其上形成有UBM焊盘142的载体210可结合到如图8F中所示的制造的连接构件120以执行后续工艺。
参照图8G，可在形成在连接构件120上的焊盘层122c上形成表面处理层130。可首先形成与焊盘层122c接触的第二表面处理层134，并且可在第二表面处理层134上形成第一表面处理层132。可通过电解镀覆工艺形成表面处理层130。具体地，可通过按原样使用用于形成焊盘层122c和连接到焊盘层122c的过孔143的种子层和图案层执行电解镀覆工艺来形成表面处理层130。因此，可不增加单独的电解引线去除工艺。接下来，可按照小于面板级(例如，带级)的单元执行锯切，并且可根据需要执行重新分布层122的四路检查和电检查。因此，表面处理层130以及第一镀层145和第二镀层146中的全部可按照面板级形成，并且可使得工艺有效率。
参照图8H，可在连接构件120上安装半导体芯片111、112和113，以形成用于密封半导体芯片111、112和113的密封构件160。诸如微凸块的结合构件115可用于安装。此后，可利用底部填充树脂170固定半导体芯片111、112和113。可通过层压膜的形式或者通过涂覆并固化液体的形式来形成密封构件160。
参照图8I，将载体210从连接构件120以及半导体芯片111、112和113分离。可通过分离释放层212而分离载体210，并且可通过蚀刻工艺去除剩余的释放层212。结果，可暴露最下面的第一绝缘层121a。
参照图8J，可执行用于去除第一绝缘层121a的一部分的预处理蚀刻工艺，并且可执行用于去除暴露的金属层149的等离子蚀刻工艺。因此，第一镀层145可从第一绝缘层121a暴露。另一方面，如果需要，可使密封构件160经受研磨工艺。半导体芯片111、112和113中的每个的上表面可通过研磨位于相同的高度上。也就是说，半导体芯片111、112和113的厚度可基本相同。然而，研磨工艺可在形成电连接结构150之后进行或可被省略。
接下来，参照图6，可执行附着电连接结构150和使电连接结构150回流的工艺。根据上述示例的半导体封装件100A可通过一系列工艺进行制造。
图9是示意性示出包括有机中介器的半导体封装件的另一示例的截面图。
参照图9，在根据另一示例的包括有机中介器的半导体封装件100B中，UBM层140的第一镀层145的侧表面可与第二绝缘层121b的围绕第一镀层145和第二镀层146的侧表面水平地间隔开。也就是说，与图6的示例性实施例不同，设置有电连接结构150的开口151宽于第一镀层145和第二镀层146，并且可形成为使得第一镀层145的侧表面的一部分或者第一镀层145的侧表面的一部分和第二镀层146的侧表面的一部分暴露。因此，形成开口151的第一绝缘层121a的侧表面和第二绝缘层121b的侧表面可与第一镀层145的侧表面间隔开第一长度D1。第一长度D1可在实施例中进行不同地选择。电连接结构150可填充在第一镀层145的侧表面与第一绝缘层121a和第二绝缘层121b之间。第一镀层145的整个下表面从第一绝缘层121a和第二绝缘层121b向下暴露以与电连接结构150接触。因此，如在图7的示例性实施例中，UBM层140a可通过去除设置在第一绝缘层121a和第一镀层145之间的所有金属层149而不包括金属层149。其他构造与根据上述示例的半导体封装件100A中描述的其他构造基本上相同。
图10是示意性示出包括有机中介器的半导体封装件的另一示例的截面图。
参照图10，示出了对应于图9的放大图的区域。与图9的示例性实施例不同，在该示例性实施例中，电连接结构150a可不填充在第一镀层145的侧表面与第一绝缘层121a和第二绝缘层121b之间。第一镀层145的侧表面与第一绝缘层121a和第二绝缘层121b之间可形成有气隙AG，并且第一镀层145的侧表面可暴露于外部。其他构造与根据上述示例的半导体封装件100A中描述的其他构造基本上相同。
图11是示意性示出包括有机中介器的半导体封装件的另一示例的截面图。
参照图11，在根据另一示例的包括有机中介器的半导体封装件100C中，UBM层140的第一镀层145的侧表面和第二镀层146的侧表面可与第二绝缘层121b的围绕第一镀层145和第二镀层146的侧表面水平地间隔开。也就是说，与图9的示例性实施例不同，设置有电连接结构150的开口151可形成为使得第一镀层145的侧表面和第二镀层146的侧表面完全地暴露。因此，第二绝缘层121b的从第一镀层145和第二镀层146的外周向下暴露的下表面可与第一绝缘层121a的下表面间隔开第二长度D2。另外，形成开口151的第一绝缘层121a的侧表面和第二绝缘层121b的侧表面可与第一镀层145的侧表面间隔开第三长度D3。第二长度D2和第三长度D3可在实施例中进行不同地选择。电连接结构150可填充在第一镀层145的侧表面、第二镀层146的侧表面和UBM焊盘142的侧表面与第一绝缘层121a和第二绝缘层121b之间，或者如在图10的示例性实施例中，电连接结构150可设置为形成气隙。其他构造与根据上述示例的半导体封装件100A和100B中描述的其他构造基本上相同。
图12是示意性示出包括有机中介器的半导体封装件的另一示例的截面图。
参照图12，在根据另一示例的包括有机中介器的半导体封装件100D中，UBM层140的第一镀层145的下表面可与位于第一镀层145的外周的第二绝缘层121b的下表面共面。也就是说，与图9的实施例不同，第一镀层145的侧表面和第二镀层146的侧表面可不暴露，并且可被第二绝缘层121b围绕。此外，设置有电连接结构150的开口151可朝向第一镀层145和第二镀层146的下表面的外部形成为更宽。因此，形成开口151的第一绝缘层121a的侧表面和第二绝缘层121b的侧表面可与第一镀层145的侧表面间隔开第四长度D4。电连接结构150可填充整个开口151，或者可设置为形成如图10的实施例中的气隙。其他构造与根据上述示例的半导体封装件100A和100B中描述的其他构造基本上相同。
如以上所阐述的，本公开的示例性实施例可提供包括有机中介器的半导体封装件，该包括有机中介器的半导体封装件能够简化工艺并防止在表面处理层和UBM层中的缺陷的发生。
尽管以上已经示出并描述了示例性实施例，但是对本领域技术人员将明显的是，在不脱离由所附权利要求限定的本发明的范围的情况下，可做出修改和变型。

Claims (17)

1.一种半导体封装件，所述半导体封装件包括：
半导体芯片，具有有效表面，所述有效表面上设置有连接焊盘；
连接构件，设置在所述半导体芯片的所述有效表面上，并且所述连接构件包括：焊盘层，设置在所述连接构件的上表面上；重新分布层，电连接到所述连接焊盘；以及绝缘层；
结合构件，设置在所述半导体芯片的所述连接焊盘和所述连接构件的所述焊盘层之间，以将所述半导体芯片与所述连接构件连接；
树脂层，在所述半导体芯片和所述连接构件之间围绕所述结合构件；
表面处理层，设置在所述连接构件的所述焊盘层的上表面上并且包括至少一个金属层；以及
凸块下金属层，嵌入在所述连接构件中并且电连接到所述连接构件的所述重新分布层，
其中，所述凸块下金属层包括：凸块下金属焊盘，嵌入在所述连接构件的所述绝缘层中；至少一个镀层，设置在所述凸块下金属焊盘上；以及凸块下金属过孔，贯穿所述连接构件的所述绝缘层的至少一部分并且将所述连接构件的所述重新分布层与所述凸块下金属焊盘电连接，
所述表面处理层仅设置在所述焊盘层的面对所述结合构件的所述上表面上而不延伸至所述焊盘层的侧表面上，并且所述凸块下金属层的所述镀层仅设置在所述凸块下金属焊盘的与所述凸块下金属过孔相对的一个表面上，并且
所述焊盘层的侧表面与所述树脂层接触。
2.根据权利要求1所述的半导体封装件，其中，所述凸块下金属层的所述镀层的侧表面的至少一部分与所述连接构件的所述绝缘层的围绕所述凸块下金属层的所述镀层的侧表面间隔开。
3.根据权利要求1所述的半导体封装件，其中，所述表面处理层和所述凸块下金属层的所述镀层包括相同的电解金属层。
4.根据权利要求3所述的半导体封装件，其中，所述表面处理层包括包含金的第一镀层以及设置在所述焊盘层和所述第一镀层之间并且包含镍的第二镀层，并且
所述凸块下金属层的所述镀层包括包含金的第三镀层以及设置在所述凸块下金属焊盘和所述第一镀层之间并包含镍的第四镀层。
5.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
电连接结构，设置在所述凸块下金属层的所述镀层上。
6.根据权利要求5所述的半导体封装件，其中，所述电连接结构在所述凸块下金属层的所述镀层的侧表面的至少一部分与所述连接构件的所述绝缘层之间延伸。
7.根据权利要求5所述的半导体封装件，其中，在所述凸块下金属层的所述镀层的侧表面的至少一部分与所述连接构件的所述绝缘层之间存在气隙。
8.根据权利要求5所述的半导体封装件，其中，所述凸块下金属层的所述镀层的侧表面的至少一部分与所述电连接结构接触。
9.根据权利要求5所述的半导体封装件，其中，所述电连接结构的直径大于所述结合构件的直径。
10.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
树脂层，围绕所述半导体芯片和所述连接构件之间的所述结合构件，
其中，所述焊盘层的侧表面与所述结合构件或所述树脂层接触，并且所述凸块下金属层的所述镀层的侧表面的至少一部分暴露于外部。
11.根据权利要求1所述的半导体封装件，其中，所述表面处理层的直径小于所述凸块下金属层的所述镀层的直径。
12.根据权利要求1所述的半导体封装件，其中，所述半导体芯片包括处理器芯片和存储器芯片，并且
所述处理器芯片和所述存储器芯片通过所述连接构件电连接。
13.根据权利要求1所述的半导体封装件，其中，所述连接构件的所述绝缘层利用有机材料制成。
14.一种半导体封装件，所述半导体封装件包括：
半导体芯片，具有有效表面，所述有效表面上设置有连接焊盘；
连接构件，设置在所述半导体芯片的所述有效表面上，并且所述连接构件包括：焊盘层，设置在所述连接构件的上表面上；重新分布层，电连接到所述连接焊盘；以及绝缘层；
结合构件，设置在所述半导体芯片的所述连接焊盘和所述连接构件的所述焊盘层之间，以将所述半导体芯片与所述连接构件连接；
表面处理层，设置在所述连接构件的所述焊盘层的上表面上并且包括至少一个金属层；以及
凸块下金属层，嵌入在所述连接构件中并且电连接到所述连接构件的所述重新分布层，
其中，所述凸块下金属层包括：凸块下金属焊盘，嵌入在所述连接构件的所述绝缘层中；至少一个镀层，设置在所述凸块下金属焊盘上；以及凸块下金属过孔，贯穿所述连接构件的所述绝缘层的至少一部分并且将所述连接构件的所述重新分布层与所述凸块下金属焊盘电连接，
所述表面处理层均仅设置在所述焊盘层的面对所述结合构件的一个表面上并且包括包含金的第一电解镀层和包含镍的第二电解镀层，所述凸块下金属层的所述镀层仅设置在所述凸块下金属焊盘的与所述凸块下金属过孔相对的一个表面上并且包括包含金的第三电解镀层和包含镍的第四电解镀层，
所述凸块下金属层的所述镀层的下表面的一部分被所述连接构件的绝缘层覆盖，并且
设置在所述镀层和所述绝缘层之间的金属层设置在所述凸块下金属层的所述镀层的所述下表面上。
15.一种半导体封装件，所述半导体封装件包括：
半导体芯片，具有有效表面，所述有效表面上设置有连接焊盘；
连接构件，设置在所述半导体芯片的所述有效表面上，并且所述连接构件包括：焊盘层，设置在所述连接构件的上表面上；重新分布层，电连接到所述连接焊盘；以及绝缘层；
结合构件，设置在所述半导体芯片的所述连接焊盘和所述连接构件的所述焊盘层之间，以将所述半导体芯片与所述连接构件连接；
表面处理层，设置在所述连接构件的所述焊盘层的上表面上并且包括至少一个金属层；以及
凸块下金属层，嵌入在所述连接构件中并且电连接到所述连接构件的所述重新分布层，
其中，所述凸块下金属层包括：凸块下金属焊盘，嵌入在所述连接构件的所述绝缘层中；至少一个镀层，设置在所述凸块下金属焊盘上；以及凸块下金属过孔，贯穿所述连接构件的所述绝缘层的至少一部分并且将所述连接构件的所述重新分布层与所述凸块下金属焊盘电连接，
所述表面处理层均仅设置在所述焊盘层的面对所述结合构件的一个表面上并且包括包含金的第一电解镀层和包含镍的第二电解镀层，所述凸块下金属层的所述镀层仅设置在所述凸块下金属焊盘的与所述凸块下金属过孔相对的一个表面上并且包括包含金的第三电解镀层和包含镍的第四电解镀层，并且
所述连接构件的所述绝缘层包括在所述凸块下金属层的所述镀层的外周处与所述凸块下金属层的所述镀层的下表面共面的区域。
16.根据权利要求14或15所述的半导体封装件，其中，所述金属层包括钛和铜中的至少一种。
17.根据权利要求14或15所述的半导体封装件，其中，所述连接构件的所述绝缘层利用有机材料制成。
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