TW202010061A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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TW202010061A
TW202010061A TW107143485A TW107143485A TW202010061A TW 202010061 A TW202010061 A TW 202010061A TW 107143485 A TW107143485 A TW 107143485A TW 107143485 A TW107143485 A TW 107143485A TW 202010061 A TW202010061 A TW 202010061A
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Taiwan
Prior art keywords
layer
under
pad
bump
metallurgical
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TW107143485A
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English (en)
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TWI818935B (zh
Inventor
李在彦
陳韓娜
鄭泰成
高永寬
卞貞洙
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南韓商三星電子股份有限公司
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Publication of TW202010061A publication Critical patent/TW202010061A/zh
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

一種包括有機中介層的半導體封裝包括：半導體晶片；連接構件，位於半導體晶片上，且包括接墊層、重佈線層以及絕緣層；接合構件，位於半導體晶片與接墊層之間；表面處理層，位於接墊層上且包括至少一金屬層；以及凸塊下冶金（UBM）層，嵌入連接構件中。凸塊下冶金層包括凸塊下冶金接墊、位於所述凸塊下冶金接墊上的至少一鍍覆層、以及凸塊下冶金通孔。所述表面處理層僅配置於所述接墊層的一表面上，所述鍍覆層僅配置於所述凸塊下冶金接墊的一表面上，且所述鍍覆層的側表面的至少部分與環繞所述鍍覆層的所述絕緣層的側表面間隔開。

Description

半導體封裝
本揭露是有關於一種包括有機中介層的半導體封裝。
隨著高端套組（high-end sets）以及高頻寬記憶體（high bandwidth memory，HBM）的採用，中介層市場正在成長。目前，已使用矽作為中介層中的主材料，但正針對大規模及低成本製造開發玻璃及有機方法。中介層至套組的主板的連接部被稱為凸塊下冶金（under-bump metallurgy，UBM）層，且連接部的可靠性受此種凸塊下冶金層的結構的極大影響，因此需要優化此種凸塊下冶金層的結構。
具體而言，已對此種凸塊下冶金層執行各種表面處理以改善接合可靠性。此類表面處理主要使用無電鍍。在此種情形中，表面處理層被配置於接墊的側表面上以及接墊的上表面上，因此在將凸塊下冶金層接合至焊料之後可出現各種缺陷。
本揭露的態樣可提供一種包括有機中介層的半導體封裝，所述半導體封裝能夠簡化製程並防止在表面處理層以及凸塊下冶金層中出現缺陷。
本揭露提議的一種解決方案可藉由電解鍍覆將表面處理層以及凸塊下冶金層的鍍覆層兩者僅形成於在連接構件的上部及下部處的接墊的一表面上，且可利用反向鍍覆方法形成凸塊下冶金層的鍍覆層。
根據本揭露的態樣，一種包括有機中介層的半導體封裝可包括：半導體晶片，具有上面配置有連接墊的主動面；連接構件，配置於所述半導體晶片的所述主動面上，且包括配置於其上表面上的接墊層、電性連接至所述連接墊的重佈線層、以及絕緣層；接合構件，配置於所述半導體晶片的所述連接墊與所述連接構件的所述接墊層之間以連接所述半導體晶片與所述連接構件；表面處理層，配置於所述連接構件的所述接墊層的上表面上且包括至少一金屬層；以及凸塊下冶金（UBM）層，嵌入所述連接構件中且電性連接至所述連接構件的所述重佈線層。所述凸塊下冶金層可包括嵌入所述連接構件的所述絕緣層中的凸塊下冶金接墊、配置於所述凸塊下冶金接墊上的至少一鍍覆層、以及穿透所述連接構件的所述絕緣層的至少部分並電性連接所述連接構件的所述重佈線層與所述凸塊下冶金接墊的凸塊下冶金通孔。所述表面處理層可僅配置於所述接墊層的面向所述接合構件的一表面上，所述凸塊下冶金層的所述鍍覆層可僅配置於所述凸塊下冶金接墊的與所述凸塊下冶金通孔相對的一表面上，且所述凸塊下冶金層的所述鍍覆層的側表面的至少部分可與所述連接構件的環繞所述凸塊下冶金層的所述鍍覆層的所述絕緣層的側表面間隔開。
在下文中，將參照所附圖式詳細闡述本揭露的例示性實施例。
電子裝置
圖1為示意性示出電子裝置系統的實例的方塊圖。
參照圖1，電子裝置1000可容置主板1010。主板1010物理連接及/或電性連接至晶片相關組件1020、網路相關組件1030或其他組件1040等。該些組件亦可耦合至以下將說明的其他組件，以形成各種訊號線1090。
晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體（例如動態隨機存取記憶體（DRAM））、非揮發性記憶體（例如唯讀記憶體（ROM））以及快閃記憶體；應用處理器晶片，例如中央處理器（例如：中央處理單元（CPU））、圖形處理器（例如：圖形處理單元（GPU））、數位訊號處理器、密碼處理器（cryptographic processor）、微處理器及微控制器；邏輯晶片，例如類比至數位轉換器（analog-to-digital converter）；以及應用專用積體電路（application-specific integrated circuit，ASIC）等，但並非僅包括該些組件。因此，不言而喻，可包括其他類型的晶片相關組件。此外，不言而喻，晶片相關組件1020可與彼此組合。
網路相關組件1030可包括以下協定：無線保真（WiFi）（電氣及電子工程師學會（IEEE）802.11家族等）、全球互通微波存取（WiMAX）（IEEE 802.16家族等）、IEEE 802.20、長期演進（long term evolution，LTE）、僅支援資料的演進（Ev-DO）、高速封包存取+（HSPA+）、高速下行封包存取+（HSDPA+）、高速上行封包存取+（HSUPA+）、增強型資料GSM環境（EDGE）、全球行動通訊系統（GSM）、全球定位系統（GPS）、通用封包無線電服務（GPRS）、分碼多重存取（CDMA）、分時多重存取（TDMA）、數位增強型無線電訊（DECT）、藍芽、3G協定、4G協定、5G協定以及被闡明為下一代的任何其他無線標準或協定或有線標準或協定，但並非僅包括該些組件。此外，不言而喻，網路相關組件1030可與晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器（ferrite inductor）、功率電感器（power inductor）、鐵氧體珠粒（ferrite beads）、低溫共燒陶瓷（low temperature co-fired ceramic，LTCC）、電磁干擾（electromagnetic interference，EMI）濾波器、以及多層陶瓷電容器（multilayer ceramic condenser，MLCC）等，但並非僅包括該些組件。因此，其他組件1040可包括用於各種其他目的的被動組件等。此外，不言而喻，其他組件1040可與晶片相關組件1020及/或網路相關組件1030相組合。
取決於電子裝置1000的類型，電子裝置1000可包括可物理連接至及/或電性連接至主板1010或可不物理連接至及/或不電性連接至主板1010的其他組件。該些其他組件的實例可包括照相機1050、天線1060、顯示器1070、電池1080、音訊編解碼器（圖中未示出）、視訊編解碼器（圖中未示出）、功率放大器（圖中未示出）、羅盤（圖中未示出）、加速度計（圖中未示出）、陀螺儀（圖中未示出）、揚聲器（圖中未示出）、大容量儲存裝置（例如硬碟驅動機）（圖中未示出）、光碟（compact disk，CD）（圖中未示出）、數位多功能光碟（digital versatile disk，DVD）（圖中未示出）等，但所述其他組件並非僅包括該些組件。此外，其他組件可包括根據電子裝置1000的類型用於各種其他目的的其他組件等。
電子裝置1000可為智慧型電話、個人數位助理（personal digital assistant）、數位攝影機、數位照相機（digital still camera）、網路系統、電腦、監視器、平板個人電腦（tablet）、膝上型個人電腦、隨身型易網機（netbook）、電視、視訊遊戲機（video game）、智慧型手錶或汽車等。然而，電子裝置1000可並非僅限於此。除該些組件以外，不言而喻，電子裝置1000可為用於處理資料的任意其他電子裝置。
圖2為示意性示出電子裝置的實例的立體圖。
參照圖2，出於各種目的將半導體封裝應用至如上所述的各種電子裝置。舉例而言，母板1110可容置於智慧型電話1100的本體1101中，且各種組件1120可物理連接至及/或電性連接至母板1110。此外，在本體1101中可容置可物理連接至及/或電性連接至母板1010或可不物理連接至及/或不電性連接至母板1010的其他組件，例如照相機1130。組件1120中的一些組件可為晶片相關組件，且組件1120中的一些組件可為中介層封裝1121。不言而喻，所述電子裝置並非僅限於智慧型電話1100，而是可為如上所述的其他電子裝置。
包括中介層的半導體封裝
一般而言，在半導體晶片中可整合有許多微電子電路，但半導體晶片自身可能無法充當半導體成品，且可能因外部物理性或化學性影響而受損。因此，半導體晶片本身可能無法原樣使用。由於此種原因，半導體晶片可被封裝且因此已以封裝狀態用於電子裝置等。
需要半導體封裝的原因在於：半導體晶片與電子裝置的主板之間存在電性連接方面的電路寬度差異。具體而言，在半導體晶片的情形中，連接墊的尺寸及連接墊之間的間隔極小。另一方面，在用於電子裝置的主板的情形中，組件安裝墊的尺寸及組件安裝墊之間的間隔可遠遠大於半導體晶片的規格。因此，由於難以直接將半導體晶片安裝於主板上，因此需要能夠緩衝半導體晶片與主板之間的電路寬度差的封裝技術。
以下，將參照圖式更詳細地闡述藉由此種封裝技術製造的包括有機中介層的半導體封裝。
圖3為示意性示出三維（3D）BGA封裝安裝於電子裝置的主板上之情形的剖視圖。
由於應用專用積體電路（ASIC）的每一晶片（例如，半導體晶片的圖形處理單元（graphics processing unit，GPU））是極為昂貴的，因此以高良率實行封裝是極為重要的。為此，在安裝半導體晶片之前可首先製備能夠對數千至數十萬的連接墊進行重佈線的球柵陣列（ball grid array，BGA）基板2210等，且然後可將例如圖形處理單元2220等昂貴的半導體晶片藉由表面安裝技術（surface mounting technology，SMT）等安裝於BGA基板2210上並進行封裝，並最終安裝於主板2110上。
另一方面，在圖形處理單元2220的情形中，需要大大縮短至例如高頻寬記憶體（HBM）等記憶體的訊號通路。為此，可將例如高頻寬記憶體2240等半導體晶片安裝於中介層2230上並然後進行封裝，且可藉由以疊層封裝（package on package，POP）形式將所述半導體晶片堆疊於上面安裝有圖形處理單元2220的封裝上而使用所述半導體晶片。然而，在此種情形中，可能存在設備的厚度變得過厚的問題，且難以大大縮短訊號通路。
圖4為示意性示出2.5D矽中介層封裝安裝於主板上之情形的剖視圖。
為解決上述問題，可藉由2.5D中介層技術製造包括矽中介層的半導體封裝2310，所述2.5D中介層技術將例如圖形處理單元2220等第一半導體晶片以及例如高頻寬記憶體2240等第二半導體晶片並排地表面安裝於矽中介層2250上，並封裝所述第一半導體晶片以及所述第二半導體晶片。在此種情形中，具有數千至數十萬個連接墊的圖形處理單元2220與高頻寬記憶體2240可藉由中介層2250進行重佈線，且可以最小通路電性連接。若將包括此種矽中介層的半導體封裝2310再次安裝於BGA基板2210等上並進行重佈線，則半導體封裝2310可最終被安裝於主板2110上。然而，在矽中介層2250的情形中，矽穿孔（through silicon via，TSV）極難形成且製造成本亦相當大，此對大規模及低成本製造而言為不利的。
圖5為示意性示出2.5D有機中介層封裝安裝於主板上之情形的剖視圖。
作為解決上述問題的方法，可考量使用有機中介層2260代替矽中介層2250。舉例而言，可藉由2.5D中介層技術製造包括有機中介層的半導體封裝2320，所述2.5D中介層技術將例如圖形處理單元2220等第一半導體晶片以及例如高頻寬記憶體2240等第二半導體晶片並排地表面安裝於有機中介層2260上，並封裝所述第一半導體晶片以及所述第二半導體晶片。在此種情形中，具有數千至數十萬個連接墊的圖形處理單元2220與高頻寬記憶體2240可藉由中介層2260進行重佈線，且可以最小通路電性連接。若將包括此種有機中介層的半導體封裝2320再次安裝於BGA基板2210等上並進行重佈線，則半導體封裝2310可最終被安裝於主板2110上。此外，此對於大規模及低成本製造而言是有利的。
同時，包括有機中介層的半導體封裝2320是藉由封裝製程製造的，所述封裝製程將晶片2220以及2240安裝於中介層2260上，且然後模製或密封晶片2220及2240。此乃因若不執行模製製程，則中介層2260上的晶片2220以及2240可能無法處理且可能無法連接至BGA基板2210等。因此，中介層2260上的晶片2220以及2240的剛性藉由所述模製得以保持。然而，當執行模製製程時，如上所述，由於中介層2260的熱膨脹係數（coefficient of thermal expansion，CTE）與晶片2220以及2240的密封構件的熱膨脹係數之間的失配等可產生以下問題，例如產生翹曲、底部填充樹脂填充效能劣化、以及在半導體晶片與密封構件之間出現裂隙。
圖6為示意性示出包括有機中介層的半導體封裝的實例的剖視圖。
參照圖6，根據實例包括有機中介層的半導體封裝100A可包括：半導體晶片111、112以及113，各自具有上面配置有連接墊111P、112P以及113P的主動面；密封構件160，密封半導體晶片111、112以及113的至少一些部分；連接構件120，配置於半導體晶片111、112及113的主動面上，且包括分別電性連接至連接墊111P、112P及113P的重佈線層122、連接至重佈線層122的通孔123、以及絕緣層121；接合構件115，配置於半導體晶片111、112及113的連接墊111P、112P及113P與連接構件120的接墊層122c之間以將半導體晶片111、112及113接合至連接構件120；表面處理層130，配置於連接構件120的接墊層122c的上表面上；凸塊下冶金（UBM）層140，嵌入連接構件120中且電性連接至連接構件120的重佈線層122；以及電性連接結構150，連接至凸塊下冶金層140。凸塊下冶金層140可包括：凸塊下冶金接墊142，嵌入連接構件120的絕緣層121中；凸塊下冶金通孔143，嵌入連接構件120的絕緣層121中以電性連接連接構件120的重佈線層122與凸塊下冶金接墊142；第一鍍覆層145以及第二鍍覆層146，嵌入連接構件120的絕緣層121中並配置於凸塊下冶金接墊142上；以及金屬層149，位於第一鍍覆層145以及第二鍍覆層146上。
連接構件120可分別在其上部及下部處連接至接合構件115以及電性連接結構150。接合構件115可藉由連接構件120的最上接墊層122c進行連接，且電性連接結構150可藉由連接構件120下方的凸塊下冶金層140進行連接。表面處理層130可包括第一表面處理層132以及第二表面處理層134，第一表面處理層132以及第二表面處理層134可分別包括與凸塊下冶金層140的第一鍍覆層145以及第二鍍覆層146相同的電解金屬層。亦即，表面處理層130以及第一鍍覆層145及第二鍍覆層146可包括具有相同材料的金屬層，且金屬層進行堆疊的結構可為相同的。舉例而言，第一表面處理層132以及第一鍍覆層145可為金（Au）鍍覆層，且可防止接墊層122c以及凸塊下冶金接墊142的氧化。第二表面處理層134以及第二鍍覆層146可各自由與第一表面處理層132以及第一鍍覆層145的材料不同的材料形成，且可為例如鎳（Ni）鍍覆層。第二表面處理層134以及第二鍍覆層146各自可防止因第一表面處理層132與接墊層122c以及第一鍍覆層145與凸塊下冶金接墊142而形成金屬間化合物。然而，表面處理層130以及第一鍍覆層145及第二鍍覆層146可在平面上具有不同的尺寸或直徑。表面處理層130連接至相對較小的接合構件115，且因此可具有較第一鍍覆層145以及第二鍍覆層146小的直徑。
接墊層122c上的表面處理層130、以及凸塊下冶金層140的第一鍍覆層145及第二鍍覆層146中的所有層皆為藉由電解鍍覆形成的層。因此，不同於現有的無電鍍類型的結構，表面處理層130以及第一鍍覆層145以及第二鍍覆層146並不延伸至接墊層122c以及凸塊下冶金接墊142的側表面上，而是僅配置於接墊層122c的上表面以及凸塊下冶金接墊142的下表面上。因此，可防止發生以下缺陷，例如由沿接墊層122c以及凸塊下冶金接墊142的側表面潤濕接合構件115以及電性連接結構150而形成的柯肯達爾（Kirkendall）空隙以及焊料的消耗。
此外，在現有的中介層中，執行在載體上形成重佈線層、將晶粒貼附於重佈線層上並對其進行模製的封裝製程，然後執行自載體分離封裝、在封裝的接觸載體的下表面上形成通孔、執行曝光及鍍覆等製程，藉此形成凸塊下冶金層。此種傳統方法最後形成凸塊下冶金層，且一般被稱為最後製作凸塊下冶金層方法（UBM layer last method）。在最後製作凸塊下冶金層方法中，由於所述製程僅因在封裝中存在的翹曲問題便難以繼續進行，因此需要使用單獨的載體，且存在針對凸塊下冶金層製程構建專屬產線的負擔。此外，由於穿過低潔淨度封裝線的產品必須再次經歷高潔淨度曝光以及鍍覆製程，因此存在製程品質以及良率降低的風險。一般而言，當應用最後製作凸塊下冶金層方法時，會在絕緣構件上或在絕緣構件的鈍化層上形成凸塊下冶金接墊。
另一方面，如稍後將闡述，根據實例的半導體封裝100A是藉由優先製作凸塊下冶金層方法（UBM layer first method）製造的。亦即，在形成連接構件120之前，可首先在形成連接構件120的線中形成凸塊下冶金層140。因此，可省略用於形成凸塊下冶金層的專用線，且可面板級別上形成凸塊下冶金層，因此可簡化製程。具體而言，由於首先形成對應於凸塊下冶金接墊142的表面處理層的第一鍍覆層145以及第二鍍覆層146，故可在不受由鍍覆引線（plating lead line）導致的設計限制的情形下形成凸塊下冶金層140，因此可實施精密間距。
在根據實例的半導體封裝100A的情形中，凸塊下冶金通孔143的與連接構件120的重佈線層122接觸的上表面的寬度大於凸塊下冶金通孔143的與凸塊下冶金接墊142接觸的底表面的寬度。此處，所述寬度是基於剖視圖確定的。當如在傳統方法中般應用最後製作凸塊下冶金層方法時，凸塊下冶金通孔的上表面的寬度一般小於凸塊下冶金通孔的下表面的寬度。另一方面，在根據實例的半導體封裝100A的情形中，應用優先製作凸塊下冶金層方法，且可以其中凸塊下冶金通孔143的上表面的寬度寬於凸塊下冶金通孔143的下表面的寬度的所謂倒置梯形形狀形成凸塊下冶金通孔143。此外，如同連接構件120的重佈線層122以及通孔123，可形成凸塊下冶金接墊142以及凸塊下冶金通孔143，且因此凸塊下冶金通孔143可為填充通孔。
在下文中，將更詳細地描述根據實例的半導體封裝100A中的每一組件。
半導體晶片111、112及113可為例如：處理器晶片，例如中央處理器（例如：中央處理單元）、圖形處理器（例如：圖形處理單元）、場域可程式化閘陣列（field programmable gate array，FPGA）、數位訊號處理器、密碼處理器、微處理器及微控制器；邏輯晶片，例如類比至數位轉換器；以及應用專用積體電路（ASIC）；或記憶體晶片，例如揮發性記憶體（例如動態隨機存取記憶體）、非揮發性記憶體（例如唯讀記憶體、快閃記憶體）以及高頻寬記憶體（HBM）。此外，晶片可彼此組合地進行排列。作為非限制性實例，第一記憶體晶片111以及第三記憶體晶片113可為例如高頻寬記憶體等記憶體晶片，且第二半導體晶片112可為例如應用處理器等處理器晶片，但並非僅限於此。半導體晶片111、112及113可經由連接構件120電性連接至彼此。
半導體晶片111、112及113各自可為其中數百至數百萬個裝置被整合於一個晶片中的積體電路（integrated circuit，IC）。在此種情形中，可使用矽（Si）、鍺（Ge）、砷化鎵（GaAs）等作為每一本體的基礎材料（basic material）。在每一本體中可形成各種電路。半導體晶片111、112及113中的每一者的連接墊111P、112P以及113P是用於將相應的半導體晶片111、112及113電性連接至其他組件，且作為連接墊111P、112P以及113P的形成材料，可使用例如鋁（Al）等導電材料，對此並無任何特別限制。可在每一本體上形成暴露出連接墊111P、112P以及113P的鈍化膜。所述鈍化膜可為氧化物膜、氮化物膜等，且可為氧化物膜與氮化物膜的雙層。可更在必要的位置處配置絕緣膜等。若有必要，則可更在半導體晶片111、112及113的主動面上形成重佈線層，且凸塊111B、112B及113B等可連接至連接墊111P、112P以及113P。凸塊111B、112B及113B可由金屬或焊料形成。半導體晶片111、112及113可經由連接墊111P、112P及113及/或凸塊111B、112B及113B連接至暴露於連接構件120上的接墊層122c。可使用例如焊料及微凸塊等接合構件115用於連接。半導體晶片111、112及113中的每一者可以習知的底部填充樹脂170固定至連接構件120上。
連接構件120對半導體晶片111、112及113中的每一者的連接墊111P、112P及113P進行重佈線。數十至數百個半導體晶片111、112及113的具有各種功能的連接墊111P、112P及113P可經由連接構件120進行重佈線，且可根據功能經由電性連接結構物理及/或電性連接至外部。連接構件120包括絕緣層121、形成於絕緣層上或形成於絕緣層121中的重佈線層122、以及穿透絕緣層121並電性連接形成於不同層上的重佈線層的通孔123。連接構件120的層數可大於或小於圖式中所示者。此類型的連接構件120可用作2.5D型有機中介層。
連接構件120可包括：最下第一絕緣層121a；第二絕緣層121b，其中嵌入有凸塊下冶金層140；第三絕緣層121c，位於凸塊下冶金層140上；第一重佈線層122a，嵌入於第三絕緣層121c中以與凸塊下冶金通孔143接觸；以及第一通孔123a，穿透第三絕緣層121c的至少部分並電性連接第一重佈線層122a與第二重佈線層122b。可藉由重覆地堆疊第三絕緣層121c、第二重佈線層122b以及第一通孔123a而構成連接構件120。此外，連接構件120可包括接墊層122c，接墊層122c配置於與密封構件160及/或底部填充樹脂170接觸的最上絕緣層121上。接墊層122c可對應於重佈線層122的部分並可充當用於安裝半導體晶片111、112及113的接墊。此外，根據例示性實施例，最下第一絕緣層121a可充當鈍化層，且可包括與第二絕緣層121b及第三絕緣層121c不同的材料。
可使用絕緣材料作為絕緣層121的材料。在此種情形中，作為絕緣材料，可使用熱固性樹脂（例如，環氧樹脂）、熱塑性樹脂（例如，聚醯亞胺）或該些樹脂與無機填料混合的樹脂，例如味之素構成膜（ajinomoto build-up film，ABF）等。作為另一選擇，可使用感光性絕緣材料，例如感光成像介電（photo imageable dielectric，PID）樹脂。亦即，絕緣層121各自可為感光性絕緣層。若絕緣層121具有感光性性質，絕緣層121可被形成為更薄，並可更容易地實現通孔123的精密間距。若絕緣層121被形成為多層，該些材料視需要可彼此相同，抑或可彼此不同。若絕緣層121被形成為多層，所述多層可根據製程進行整合，且因此所述多層之間的界限可不明顯。
重佈線層122可用於對連接墊111P、112P及113P進行實質上重佈線，且作為重佈線層122的形成材料，可使用導電材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）及鈦（Ti）、或其合金。重佈線層122可根據對應層的設計執行各種功能。舉例而言，重佈線層122可包括接地（GND）圖案、電源（PWR）圖案、訊號（S）圖案等。此處，除接地（GND）圖案、電源（PWR）圖案等之外，訊號（S）圖案可包括各種訊號，例如資料訊號等。此外，訊號（S）圖案可包括通孔接墊、連接端子墊等。表面處理層130可形成於重佈線層122中的接墊層122c的表面上。
通孔123可電性連接於形成於不同層上的重佈線層122等之間，藉此在封裝100A中形成電性通路。作為通孔123的形成材料，可使用導電材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）及鈦（Ti）、或其合金。通孔123可被完全填充以導電材料，但並非僅限於此。參照圖式，通孔123的剖面形狀可具有實質上倒置的梯形形狀。
表面處理層130包括第一表面處理層132以及第二表面處理層134。第一表面處理層132以及第二表面處理層134可為由不同材料形成的層，且第一表面處理層132可配置於上部上，且第二表面處理層134可配置於第一表面處理層132與接墊層122c之間。舉例而言，第一表面處理層132可由金（Au）形成，且第二表面處理層134可由鎳（Ni）形成。表面處理層130可僅形成於接墊層122c的上表面上以暴露出接墊層122c的側表面。根據例示性實施例，接墊層122c的自表面處理層130暴露出的側表面可與底部填充樹脂170接觸，且接墊層122c的所述側表面的至少部分可與接合構件115接觸。
凸塊下冶金層140可改善電性連接結構150的連接可靠性，藉此改善封裝100A的板級可靠性。凸塊下冶金層140可包括：凸塊下冶金接墊142，嵌入位於連接構件120的下部處的第二絕緣層121b中；凸塊下冶金通孔143，嵌入第二絕緣層121b中以電性連接連接構件120的重佈線層122與凸塊下冶金接墊142；第一鍍覆層145以及第二鍍覆層146，嵌入第二絕緣層121b中且配置於凸塊下冶金接墊142的部分上；以及金屬層149，配置於第一鍍覆層145與第一絕緣層121a之間。電性連接結構150可配置於第一鍍覆層145上，且被配置成突出至第一絕緣層121a的下部。
第一鍍覆層145以及第二鍍覆層146可對應於凸塊下冶金接墊142的表面處理層。作為第一鍍覆層145以及第二鍍覆層146的形成材料，可使用導電材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）及鈦（Ti）、或其合金。舉例而言，第一鍍覆層145可為金（Au）鍍覆層，且第二鍍覆層146可為鎳（Ni）鍍覆層。然而，構成第一鍍覆層145及第二鍍覆層146的層數並非僅限於此。在此實施例中，第一鍍覆層145以及第二鍍覆層146的材料及堆疊結構可與表面處理層130相同，但並非僅限於此。
金屬層149可為用於形成第一鍍覆層145以及第二鍍覆層146的晶種層。在製程期間形成開口151以形成電性連接結構150時可局部地移除金屬層149，且金屬層149可僅存留於被第一絕緣層121a覆蓋的區域中。金屬層149可包含導電材料，例如鈦（Ti）層及銅（Cu）層。
電性連接結構150可配置於自其移除第一絕緣層121a的開口151中，以將半導體封裝100A物理及/或電性連接至外部。舉例而言，半導體封裝100A可藉由電性連接結構150安裝於電子裝置的主板上。因此，電性連接結構150的尺寸及直徑可大於接合構件115。此外，電性連接結構150可配置於第一鍍覆層145上，且開口151可被形成為小於第一鍍覆層145以暴露出第一鍍覆層145的部分。電性連接結構150可由導電材料（例如，焊料）形成，但此僅為實例且其材料並非特別受限於此。電性連接結構150可為接腳、球或引腳等。電性連接結構150可由多層或單層形成。當電性連接結構被形成為多層時，電性連接結構可包括銅柱及焊料。當電性連接結構被形成為單層時，電性連接結構可包括錫-銀焊料或銅，但此僅為實例且並非僅限於此。
電性連接結構150的數量、間隔、配置形式等不受特別限制，並可由熟習此項技術者根據設計規格而充分修改。舉例而言，電性連接結構150的數目可依據連接墊111P、112P及113P的數目而為數十至數千個，且可具有更多的數目或更少的數目。電性連接結構150中的一些可配置於扇出區域中。扇出區域可意指半導體晶片111、112及113所配置的區域之外的區域。亦即，根據實例的半導體封裝100A可為扇出型半導體封裝。扇出型封裝可較扇入型封裝更可靠，且可實施諸多輸入/輸出端子並有利於三維內連線。此外，所述封裝可被製造成較球柵陣列（BGA）封裝以及接腳柵陣列（land grid array，LGA）更薄，且價格競爭力可為優異的。
密封構件160可保護半導體晶片111、112及113等。密封形式不受特定限制，且因此可容許任意密封形式，只要其可封閉第一半導體晶片112的至少部分即可。密封構件160的材料不受特定限制。舉例而言，可使用絕緣材料。在此種情形中，作為絕緣材料，可使用熱固性樹脂（例如，環氧樹脂）、熱塑性樹脂（例如，聚醯亞胺）或該些樹脂與無機填料混合的材料，例如味之素構成膜（ABF）等。然而，本揭露的絕緣材料的實例並非僅限於此，且亦可使用包括玻璃纖維等的預浸體。作為另一選擇，亦可使用習知的環氧樹脂模製化合物（epoxy molding compound，EMC）等。
底部填充樹脂170可將半導體晶片111、112及113固定於連接構件120上。作為底部填充樹脂170，可應用包括環氧樹脂等的習知材料。若有必要，則可省略底部填充樹脂170。同時，儘管圖式中未示出，但若有必要，則被動組件可藉由與半導體晶片111、112及113平行配置於連接構件120上而進行封裝。
圖7為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。
參照圖7，示出了與圖6所示的放大圖對應的區域。在本實施例中，其中配置有電性連接結構150的開口151被形成為具有與第一鍍覆層145以及第二鍍覆層146相同的尺寸或寬度。因此，第一鍍覆層145的整個下表面向下自第一絕緣層121a及第二絕緣層121b暴露出，以與電性連接結構150接觸。因此，不同於圖6的例示性實施例，藉由移除配置於第一絕緣層121a與第一鍍覆層145之間的所有金屬層149，凸塊下冶金層140a可不包括金屬層149。其他配置與在根據上述實例的半導體封裝100A中闡述的配置實質上相同。
圖8A至圖8J為示意性示出形成圖6所示的包括有機中介層的半導體封裝的製程的實例的圖式。
參照圖8A，可製備載體210。載體210可包括核心層211以及形成於核心層211上的離型層212。核心層211可為玻璃、絕緣樹脂、無機填料、以及例如包括玻璃纖維的預浸體。離型層212可包含例如金屬（例如，銅（Cu）或鈦（Ti）），且可經表面處理以易於分離。根據例示性實施例，載體210可為玻璃載體，抑或可為典型的拆離核心（detach core）。
參照圖8B，可於載體210上依序形成第一絕緣層121a與金屬層149。第一絕緣層121a可利用以下材料形成：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；或感光性絕緣材料，例如感光成像介電（PID）樹脂。金屬層149可藉由濺鍍製程形成，且可由例如鈦（Ti）/銅（CU）構成的雙層形成。
參照圖8C，可於金屬層149上形成圖案層220，且然後可依序形成第一鍍覆層145以及第二鍍覆層146。圖案層220可由光阻層或乾膜形成。可藉由電解鍍覆製程填充圖案層220之間的空間來形成第一鍍覆層145以及第二鍍覆層146。第一鍍覆層145以及第二鍍覆層146可形成於作為晶種層的金屬層149上。具體而言，第一鍍覆層145以及第二鍍覆層146可藉由電解鍍覆形成，且可防止可在藉由無電鍍被形成時發生的缺陷，例如圖案周圍的模糊。第一鍍覆層145以及第二鍍覆層146可被形成為具有相同的尺寸及寬度，但並非僅限於此。
參照圖8D，可形成凸塊下冶金接墊142以覆蓋第一鍍覆層145以及第二鍍覆層146，且可移除圖案層220。凸塊下冶金接墊142可形成於第一鍍覆層145以及第二鍍覆層146上。接下來，可移除位於圖案層220下方的金屬層149。
參照圖8E，可形成第二絕緣層121b，且可圖案化第二絕緣層121b，藉此形成連接至凸塊下冶金接墊142的通孔143。可藉由層疊方法或塗敷方法形成第二絕緣層121b。通孔143可藉由以微影法、機械鑽孔及/或雷射鑽孔等形成通孔孔洞並以導電材料掩蔽所述通孔孔洞而形成。因此，可形成凸塊下冶金層140。
參照圖8F，可於第二絕緣層121b以及凸塊下冶金層140上進一步形成除第一重佈線層122a之外的組件，以形成連接構件120。連接構件120與凸塊下冶金層140可於同一條線中連續形成。可藉由層疊或塗佈PID等的方法而形成絕緣層121。可藉由利用乾膜等形成圖案、然後以鍍覆方法填充所述圖案而形成重佈線層122以及通孔123。作為鍍覆方法，可使用減成製程（subtractive process）、加成製程（additive process）、半加成製程（semi-additive process，SAP）、改良半加成製程（modified semi-additive process，MSAP）等，但所述鍍覆方法並非僅限於此。在根據另一實例的製程中，如在圖8D中所示上面形成有凸塊下冶金接墊142的載體210可被耦合至所製造的連接構件120，以執行後續的製程。
參照圖8G，可在形成於連接構件120上的接墊層122c上形成表面處理層130。可首先形成與接墊層122c接觸的第二表面處理層134，且可在第二表面處理層134上形成第一表面處理層132。可藉由電解鍍覆製程形成表面處理層130。具體而言，可藉由原樣利用用於形成接墊層122c以及連接至接墊層122c的通孔143的圖案層以及晶種層執行電解鍍覆製程而形成表面處理層130。因此，可不添加單獨的電解引入移除製程（electrolytic lead-in removal process）。接下來，可以小於面板級別的單元（例如，條帶級別）執行切割，且必要時可執行重佈線層122的四路檢驗（quad route inspection）以及電性檢驗。因此，可在面板級別下形成表面處理層130以及第一鍍覆層145及第二鍍覆層146中的所有者，且可使製程高效。
參照圖8H，可將半導體晶片111、112以及113安裝於連接構件120上，以形成用於密封半導體晶片111、112以及113的密封構件160。可使用例如微凸塊等接合構件115用於安裝。此後，可以底部填充樹脂170固定半導體晶片111、112及113。密封構件160可藉由層疊膜形式或藉由塗敷並固化液體形式而形成。
參照圖8I，將載體210自連接構件120以及半導體晶片111、112以及113分離。載體210可藉由分離離型層212而被分離，且剩餘的離型層212可藉由蝕刻製程被移除。因此，可暴露出最下第一絕緣層121a。
參照圖8J，可執行用於移除第一絕緣層121a的部分的預處理蝕刻製程（descum etching process），且可執行用於移除被暴露出的金屬層149的電漿蝕刻製程。因此，可自第一絕緣層121a暴露出第一鍍覆層145。另一方面，若有必要，則可使密封構件160經受研磨製程。半導體晶片111、112以及113中的每一者的上表面可藉由研磨而位於同一水平高度上。亦即，半導體晶片111、112以及113的厚度可實質上相同。然而，可在形成電性連接結構150之後執行研磨製程，抑或可省略所述研磨製程。
接下來，參照圖6，可執行貼附並迴焊電性連接結構150的製程。可藉由一系列製程製造根據上述實例的半導體封裝100A。
圖9為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。
參照圖9，在根據另一實例包括有機中介層的半導體封裝100B中，凸塊下冶金層140的第一鍍覆層145的側表面可與環繞第一鍍覆層145以及第二鍍覆層146的第二絕緣層121b的側表面水平間隔開。亦即，不同於圖6所示的例示性實施例，其中配置有電性連接結構150的開口151寬於第一鍍覆層145以及第二鍍覆層146，且可被形成為使得第一鍍覆層145以及第二鍍覆層145的側表面的部分（例如，第一鍍覆層145的側表面）被暴露出。因此，形成開口151的第一絕緣層121a以及第二絕緣層121b的側表面可與第一鍍覆層145的側表面間隔開第一長度D1。在實施例中可以各種方式選擇第一長度D1。電性連接結構150可填充於第一鍍覆層145的側表面與第一絕緣層121a及第二絕緣層121b之間。第一鍍覆層145的整個下表面向下自第一絕緣層121a及第二絕緣層121b暴露出，以與電性連接結構150接觸。因此，如在圖7的例示性實施例中，藉由移除配置於第一絕緣層121a與第一鍍覆層145之間的所有金屬層149，凸塊下冶金層140a可不包括金屬層149。其他配置與在根據上述實例的半導體封裝100A中闡述的配置實質上相同。
圖10為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。
參照圖10，示出了與圖9所示的放大圖對應的區域。不同於圖9所示的例示性實施例，在本例示性實施例中，電性連接結構150a可不填充於第一鍍覆層145的側表面與第一絕緣層121a及第二絕緣層121b之間。可在第一鍍覆層145的側表面與第一絕緣層121a及第二絕緣層121b之間形成氣隙AG，且第一鍍覆層145的側表面可被暴露至外部。其他配置與在根據上述實例的半導體封裝100A中闡述的配置實質上相同。
圖11為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。
參照圖11，在根據另一實例包括有機中介層的半導體封裝100C中，凸塊下冶金層140的第一鍍覆層145的側表面以及第二鍍覆層146的側表面可與環繞第一鍍覆層145以及第二鍍覆層146的第二絕緣層121b的側表面水平間隔開。亦即，不同於圖9所示的例示性實施例，其中配置有電性連接結構150的開口151可被形成為使得第一鍍覆層145的側表面以及第二鍍覆層146的側表面被完全暴露出。因此，第二絕緣層121b的向下自第一鍍覆層145及第二鍍覆層146的周邊暴露出的下表面可與第一絕緣層121a的朝向上部的下表面間隔開第二長度D2。此外，形成開口151的第一絕緣層121a以及第二絕緣層121b的側表面可與第一鍍覆層145的側表面間隔開第三長度D3。在實施例中可以各種方式選擇第二長度D2以及第三長度D3。電性連接結構150可填充於第一鍍覆層145、第二鍍覆層146以及凸塊下冶金接墊142的側表面與第一鍍覆層121a及第二鍍覆層121b之間，抑或如在圖10所示的例示性實施例中，電性連接結構150可被配置成形成氣隙。其他配置與在根據上述實例的半導體封裝100A及100B中闡述的配置實質上相同。
圖12為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。
參照圖12，在根據另一實例包括有機中介層的半導體封裝100D中，凸塊下冶金層140的第一鍍覆層145的下表面可與第二絕緣層121b在第一鍍覆層145的周邊處的下表面共面。亦即，不同於圖9所示的實施例，第一鍍覆層145以及第二鍍覆層146的側表面可不被暴露出，且可被第二絕緣層121b環繞。此外，其中配置有電性連接結構150的開口151可朝向第一鍍覆層145以及第二鍍覆層146的下表面之外廣闊地形成。因此，形成開口151的第一絕緣層121a以及第二絕緣層121b的側表面可與第一鍍覆層145的側表面間隔開第四長度D4。電性連接結構150可填充整個開口151，抑或可如在圖10所示的實施例中被配置成形成氣隙。其他配置與在根據上述實例的半導體封裝100A及100B中闡述的配置實質上相同。
如上所述，本揭露的例示性實施例可提供包括有機中介層的半導體封裝，所述半導體封裝能夠簡化製程並防止在表面處理層以及凸塊下冶金層中出現缺陷。
雖然例示性實施例已顯示及闡述如上，但對於熟習此項技術者而言顯然可在不脫離如由所附的申請專利範圍所定義的本揭露的範圍下進行修改及變化。
100A、100B、100C、100D‧‧‧半導體封裝 111、112、113‧‧‧半導體晶片 111B、112B、113B‧‧‧凸塊 111P、112P、113P‧‧‧連接墊 115‧‧‧接合構件 120‧‧‧連接構件 121‧‧‧絕緣層 121a‧‧‧第一絕緣層 121b‧‧‧第二絕緣層 121c‧‧‧第三絕緣層 122‧‧‧重佈線層 122a‧‧‧第一重佈線層 122b‧‧‧第二重佈線層 122c‧‧‧接墊層 123‧‧‧通孔 123a‧‧‧第一通孔 130‧‧‧表面處理層 132‧‧‧第一表面處理層 134‧‧‧第二表面處理層 140、140a‧‧‧凸塊下冶金（UBM）層 142‧‧‧凸塊下冶金接墊 143‧‧‧凸塊下冶金通孔 145‧‧‧第一鍍覆層 146‧‧‧第二鍍覆層 149‧‧‧金屬層 150、150a‧‧‧電性連接結構 151‧‧‧開口 160‧‧‧密封構件 170‧‧‧底部填充樹脂 210‧‧‧載體 211‧‧‧核心層 212‧‧‧離型層 220‧‧‧圖案層 1000‧‧‧電子裝置 1010‧‧‧主板 1020‧‧‧晶片相關組件 1030‧‧‧網路相關組件 1040‧‧‧其他組件 1050‧‧‧照相機 1060‧‧‧天線 1070‧‧‧顯示器 1080‧‧‧電池 1090‧‧‧訊號線 1100‧‧‧智慧型電話 1101‧‧‧本體 1110‧‧‧母板 1120‧‧‧組件 1121‧‧‧中介層封裝 1130‧‧‧照相機 2110‧‧‧主板 2210‧‧‧球柵陣列（BGA）基板 2220‧‧‧圖形處理單元/晶片 2230‧‧‧中介層 2240‧‧‧高頻寬記憶體/晶片 2250‧‧‧矽中介層 2260‧‧‧有機中介層 2310‧‧‧半導體封裝 2320‧‧‧半導體封裝 AG‧‧‧氣隙 D1‧‧‧第一長度 D2‧‧‧第二長度 D3‧‧‧第三長度 D4‧‧‧第四長度
由以下結合所附圖式的詳細闡述，將更清楚地理解本揭露的上述及其他態樣、特徵及優點，其中： 圖1為示意性示出電子裝置系統的實例的方塊圖。 圖2為示意性示出電子裝置的實例的立體圖。 圖3為示意性示出三維（3D）BGA封裝安裝於電子裝置的主板上之情形的剖視圖。 圖4為示意性示出2.5D矽中介層封裝安裝於主板上之情形的剖視圖。 圖5為示意性示出2.5D有機中介層封裝安裝於主板上之情形的剖視圖。 圖6為示意性示出包括有機中介層的半導體封裝的實例的剖視圖。 圖7為示意性示出包括有機中介層的半導體封裝的另一實例的放大圖。 圖8A至圖8J為示意性示出形成圖6所示的包括有機中介層的半導體封裝的製程的實例的圖式。 圖9為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。 圖10為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。 圖11為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。 圖12為示意性示出包括有機中介層的半導體封裝的另一實例的剖視圖。
100A‧‧‧半導體封裝
111、112、113‧‧‧半導體晶片
111B、112B、113B‧‧‧凸塊
111P、112P、113P‧‧‧連接墊
115‧‧‧接合構件
120‧‧‧連接構件
121‧‧‧絕緣層
121a‧‧‧第一絕緣層
121b‧‧‧第二絕緣層
121c‧‧‧第三絕緣層
122‧‧‧重佈線層
122a‧‧‧第一重佈線層
122b‧‧‧第二重佈線層
122c‧‧‧接墊層
123‧‧‧通孔
123a‧‧‧第一通孔
130‧‧‧表面處理層
132‧‧‧第一表面處理層
134‧‧‧第二表面處理層
140‧‧‧凸塊下冶金(UBM)層
142‧‧‧凸塊下冶金接墊
143‧‧‧凸塊下冶金通孔
145‧‧‧第一鍍覆層
146‧‧‧第二鍍覆層
149‧‧‧金屬層
150‧‧‧電性連接結構
151‧‧‧開口
160‧‧‧密封構件
170‧‧‧底部填充樹脂

Claims (19)

  1. 一種半導體封裝，包括： 半導體晶片，具有上面配置有連接墊的主動面； 連接構件，配置於所述半導體晶片的所述主動面上，且包括配置於其上表面上的接墊層、電性連接至所述連接墊的重佈線層、以及絕緣層； 接合構件，配置於所述半導體晶片的所述連接墊與所述連接構件的所述接墊層之間以連接所述半導體晶片與所述連接構件； 表面處理層，配置於所述連接構件的所述接墊層的上表面上且包括至少一金屬層；以及 凸塊下冶金（UBM）層，嵌入所述連接構件中且電性連接至所述連接構件的所述重佈線層， 其中所述凸塊下冶金層包括嵌入所述連接構件的所述絕緣層中的凸塊下冶金接墊、配置於所述凸塊下冶金接墊上的至少一鍍覆層、以及穿透所述連接構件的所述絕緣層的至少部分並電性連接所述連接構件的所述重佈線層與所述凸塊下冶金接墊的凸塊下冶金通孔，且 所述表面處理層僅配置於所述接墊層的面向所述接合構件的一表面上，且所述凸塊下冶金層的所述鍍覆層僅配置於所述凸塊下冶金接墊的與所述凸塊下冶金通孔相對的一表面上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述凸塊下冶金層的所述鍍覆層的側表面的至少部分與所述連接構件的環繞所述凸塊下冶金層的所述鍍覆層的所述絕緣層的側表面間隔開。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述表面處理層及所述凸塊下冶金層的所述鍍覆層包括相同的電解金屬層。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述表面處理層包括包含金（Au）的第一鍍覆層、以及配置於所述接墊層與所述第一鍍覆層之間並包含鎳（Ni）的第二鍍覆層，且 所述凸塊下冶金層的所述鍍覆層包括包含金（Au）的第三鍍覆層、以及配置於所述凸塊下冶金接墊與所述第一鍍覆層之間並包含鎳（Ni）的第四鍍覆層。
  5. 如申請專利範圍第1項所述的半導體封裝，更包括： 電性連接結構，配置於所述凸塊下冶金層的所述鍍覆層上。
  6. 如申請專利範圍第5項所述的半導體封裝，其中所述電性連接結構在所述凸塊下冶金層的所述鍍覆層的側表面的至少部分與所述連接構件的所述絕緣層之間延伸。
  7. 如申請專利範圍第5項所述的半導體封裝，其中在所述凸塊下冶金層的所述鍍覆層的側表面的至少部分與所述連接構件的所述絕緣層之間存在氣隙。
  8. 如申請專利範圍第5項所述的半導體封裝，更包括： 樹脂層，環繞位於所述半導體晶片與所述連接構件之間的所述接合構件， 其中所述接墊層的側表面與所述樹脂層接觸，且所述凸塊下冶金層的所述鍍覆層的側表面的至少部分與所述電性連接結構接觸。
  9. 如申請專利範圍第5項所述的半導體封裝，其中所述電性連接結構具有較所述接合構件的直徑大的直徑。
  10. 如申請專利範圍第1項所述的半導體封裝，更包括： 樹脂層，環繞位於所述半導體晶片與所述連接構件之間的所述接合構件， 其中所述接墊層的側表面與所述接合構件或所述樹脂層接觸，且所述凸塊下冶金層的所述鍍覆層的側表面的至少部分被暴露至外部。
  11. 如申請專利範圍第1項所述的半導體封裝，其中所述表面處理層具有較所述凸塊下冶金層的所述鍍覆層的直徑小的直徑。
  12. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體晶片包括處理器晶片以及記憶體晶片，且 所述處理器晶片與所述記憶體晶片藉由所述連接構件電性連接。
  13. 如申請專利範圍第1項所述的半導體封裝，其中所述連接構件的所述絕緣層是由有機材料製成的。
  14. 一種半導體封裝，包括： 半導體晶片，具有上面配置有連接墊的主動面； 連接構件，配置於所述半導體晶片的所述主動面上，且包括配置於其上表面上的接墊層、電性連接至所述連接墊的重佈線層、以及絕緣層； 接合構件，配置於所述半導體晶片的所述連接墊與所述連接構件的所述接墊層之間以連接所述半導體晶片與所述連接構件； 表面處理層，配置於所述連接構件的所述接墊層的上表面上且包括至少一金屬層；以及 凸塊下冶金（UBM）層，嵌入所述連接構件中且電性連接至所述連接構件的所述重佈線層， 其中所述凸塊下冶金層包括嵌入所述連接構件的所述絕緣層中的凸塊下冶金接墊、配置於所述凸塊下冶金接墊上的至少一鍍覆層、以及穿透所述連接構件的所述絕緣層的至少部分並電性連接所述連接構件的所述重佈線層與所述凸塊下冶金接墊的凸塊下冶金通孔，且 所述表面處理層各自僅配置於所述接墊層的面向所述接合構件的一表面上且包括包含金（Au）的第一電解鍍覆層以及包含鎳（Ni）的第二電解鍍覆層，且所述凸塊下冶金層的所述鍍覆層僅配置於所述凸塊下冶金接墊的與所述凸塊下冶金通孔相對的一表面上並包括包含金（Au）的第三電解鍍覆層以及包含鎳（Ni）的第四電解鍍覆層。
  15. 如申請專利範圍第14項所述的半導體封裝，其中所述凸塊下冶金層的所述鍍覆層的下表面的部分被所述連接構件的絕緣層覆蓋，且 配置於所述鍍覆層與所述絕緣層之間的金屬層設置於所述凸塊下冶金層的所述鍍覆層的所述下表面上。
  16. 如申請專利範圍第15項所述的半導體封裝，其中所述金屬層包含鈦（Ti）及銅（Cu）中的至少一者。
  17. 如申請專利範圍第14項所述的半導體封裝，其中所述凸塊下冶金層的所述鍍覆層的側表面的至少部分與所述連接構件的所述絕緣層間隔開。
  18. 如申請專利範圍第14項所述的半導體封裝，其中所述連接構件的所述絕緣層在所述凸塊下冶金層的所述鍍覆層的周邊包括與所述凸塊下冶金層的所述鍍覆層的下表面共面的區域。
  19. 如申請專利範圍第14項所述的半導體封裝，其中所述連接構件的所述絕緣層是由有機材料製成的。
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