1304255 九、發明說明： 【發明所屬之技術領域】 及-種電容元件埋人半導體封裝基板結構 :氣作方法’尤指一種適用於改善電容材料漏電現象及 =隙與厚度不均等現象之電容元件埋人半導體封裝基 板結構及其製作方法。 【先前技術】 由於半導體製程之進步，以及半導體晶片上電路功能 H)料斷提升，使得半導體裝置之發展走向高度積集化。惟 +導體褒置之積集化，封裝構造之接腳數目亦隨著增加， 而由於接腳數目與線路佈設之增多，導致雜訊亦隨之增 ^因此，一般為消除雜訊或作電性補償，係於半導體封 裝結構中增加被動元件，如電阻元件、電容材料與電感元 15件，以消除雜訊與穩定電路，藉以使得所封裝之半導體晶 片符合電性特性之要求。 〜在傳統的方法中，係主要將電容元件利用表面黏著技 f (Surface Mount Technology ; SMT)置於基板表面，目 前有許多研究係利用壓合的方式將高介電材料壓合於銅層 2〇 ^再製作線路以形成電容元件。如圖冰示，係為目前利^ 壓合方式形成電容元件的結構剖視圖。其主要提供一内層 電路板11、一高介電材料層12、一外層線路層13、一電鍍 導通孔（Plated Through Hole ; PTH)14、一防焊層 15以及一 焊料錫球16。其中，此内層電路板11係具有一内層線路層 1304255 -lla；高介電材料層12係壓合於内層線路層lla上，接著再 於冋；丨電材料層12表面形成一外層線路層i 3，目此經由此 而形成一電容元件。而電鑛導通孔14係可導通此基板兩側 的線路。接著再繼續進行後續的製程而形成防焊層15以及 5 焊料錫球16。 然而，此種方法利用整片高介電材料壓合的成本相當 的高，但是如果僅僅使用少數面積則會造成材料浪費。另 外，會有填孔性的問題，因為整片高介電材料，其流膠性 很差，故很容易會有孔隙（void)產生以及會有厚度不均的現 10象發生。此外，此種方法仍有另一問題，即會有線路間電 合現象的漏電問題，因整片的高介電材料易發生漏電現象 (current leakage) ’尤其是在高頻上的應用更為嚴重。 【發明内容】 15 鑑於上述習知技術之缺點，本發明提供一種電容元件 埋入半導體封裝基板結構，此結構包括一内層電路板、一 介電層以及一外層線路層。在内層電路板中可具有一内層 線路層。在介電層中可配置於内層電路板的兩側，且介電 層内具有複數個第一導電盲孔，而第一導電盲孔可依序係 20 經由一金屬薄層、一電容材料、一電極層及一黏著層與内 層線路層導通。至於外層線路層則可配置於介電層表面。 其中，此電容材料與電極層可以作為一電容元件。將此種 埋入於半導體封裝基板中之電容元件，可節省材料、無填 孔性問題及無線路間之電容現象之漏電問題。 1304255 :本七明中’介電層内復可包括至少 孔’其係與内層線路層導通。 7本發”介電層巾復可包括―外部電鍍導通孔， 層係導通配置於内層電路板兩側之介電層表面之外層線路 _ 據上述本發明之具有埋入式選擇性電容元件之半導 體封裝基板，例如可由下述但不限於此之步驟製作。 本發明亦提供—種電容元件埋人半導體封裝基板結構 之，M乍方法，其步驟包括：首先，提供-金屬载板，於其 0表面七成複數個I容材料，且電容材料纟面形成一電極 層。接著，於電極層表面形成一黏著I。再將一内層電路 板經由黏著層而與金屬載板連接。然後，將此金屬載板厚 度減薄。接著，移除未與電容材料連接之金屬載板，且與 電谷材料連接之金屬載板則可形成一金屬薄層，此金屬薄 15層、電容材料與電極層因此可形成一電容元件。再於内層 電路板表面兩側分別壓合一介電層，且此介電層内形成複 數個第一盲孔，此第一盲孔可對應於由金屬載板形成的金 屬薄層。最後於第一盲孔及介電層表面分別可形成一第一 導電盲孔及一外層線路層。 20 在本發明中，壓合介電層後，此介電層内復可形成至 少一弟二盲孔’其係對應於内層電路板之線路，並於至少 一第二盲孔内形成一第二導電盲孔。 另在此介電層内復包括形成至少一通孔（through hole)，此通孔係貫穿内層電路板及其兩側之介電層，並於 1304255 • 通孔内形成一外部電鍍導通孔。 在本發明中，内層電路板復包括可形成一内部電鍍導 通孔。此内部電鍍導通孔可經由銅、錫、鎳、鉻、鈦、銅_ 鉻合金或錫-鉛合金以導通内層電路板兩側的線路。較佳地 5可以使用銅金屬。另外，此電鑛導通孔内更可包括一絕緣 樹脂，例如環氧樹脂。 依據上述本發明，第一導電盲孔及第二導電盲孔内係 彳以為填滿或未填滿導電材料，此等導電材料可以為銅、 錫、錄、鉻、鈦、銅.路合金或錫錯合金，較佳地可為銅金 H)屬。此第一導電盲孔及第二導電盲孔係可分別經由電鑛的 方式將導電材料於第一盲孔及第二盲孔内形成。 依據上述本發明，由金屬載板以及由金屬載板所形成 的金屬薄層可以為任何金屬板材，例如為銅、紹或其相關 合金。較佳地可以為銅。 15 轉明所使用的電容材料，其材料係為高介電常數之 材料，較佳地可以為高分子材料、陶究材料、陶变粉末填 ♦ 《之高分子或其類似物之混合物所構成。更佳地係可為欽 酸鎖（BadUm-tianate)、鈦酸純（Lead zire刪心如仙⑹及 無定形氫化碳(Amorphous hydr〇genated _η)所構成群組 20之其中一者散佈於黏結劑（Binder)中所形成。而此電容材 的介電係數其係至少大約4〇以上，較佳可為約4〇〜3〇〇之 間。、同時，在製作電容材料可以利用賤渡、印刷或塗佈的 方式形成’更佳地，可以利用印刷之方式形成。 本發明在電極層中所使用之材料較佳地可為銅膏或銀 8 1304255 膏。且可利用濺渡、印刷或塗佈的方式形成，更佳地，可 以印刷之方式形成。 本發明的黏著層使用之材料較佳可為銅、錫、鎳、鉻、 鈦、銅-鉻合金以及錫-鉛合金中所組成之群組之一者，更佳 5 地可以使用以錫材料做成的錫膏。此黏著層主要的功用在 於作為與内層電路板連接的作用。同時，可以在電極層表 面使用網版印刷（screen printing)的方式形成此黏著層。 另外，本發明使用的介電層係可選自ABF(Ajinomoto Build-up Film )、BCB(Benzocyclo-buthene)、LCP (Liquid 10 Crystal Polymer)、Pl(Poly-imide)、PPE (Poly(phenylene ether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)等感光或非 感光有機樹脂，或亦可混合環氧樹脂與玻璃纖維等材質所 組成之群組之一者。 15 再者，本發明通孔形成的方式係可利用機械鑽孔或雷 射鑽孔，使得以貫通内層電路板及其兩側的介電層，而形 成一外部電鍍導通孔，此外部電鍍導通孔可以導通於内層 電路板兩侧之介電層表面的線路層，且於此外部電鍍導通 孔内更包括一絕緣樹脂，例如環氧樹脂。 20 在上述本發明中，線路層使用之材料較佳地可為銅、 錫、錄、絡、欽、銅·絡合金以及锡-船合金中所組成之群組 之一者。更佳地，則可以使用銅做為線路層。 在本發明所提供的半導體封裝基板中可以直接於外層 表面形成一防焊層（solder mask)以及形成一焊料錫球以與 1304255 曰曰片連接同k亦可做為一核心板，在其兩侧形成一增層 結構，以繼續製造後續製程，與晶片連接。 θ 旦本發明可提升半導體封裝基板内被動元件之佈設數 量，並增加基板線路佈局靈活性，可有效提升基板表面使 用面積u達半導體裝置輕薄短小之目標。 另外’本發明利用在金屬載板上製作選擇性電容元 件再以‘電目孔或通孔導通的方式，不但可以節省材料， 並且不會有孔隙以及厚度不均的問題。同樣的，可 :路間電容現象的漏電問題。並且可以簡化製程，而且摔 作上更為精準。 【實施方式】 15 1下係、藉由特疋的具體實施例說明本發明之實施方 此技藝之人示可由本說明書所揭示之内容輕易地 的==他優點與功效。本發明亦可藉由其他不同 ==施行或應用，本說明書中的各項細節亦 種修飾與㈣應用’在不㈣本發明之精神下進行各 本=之實施例中該等圖式均為簡化之示意圖。惟該 實:m本發明有關之元件，其所顯示支元件非為 例為二:擇η，其實際實施時之元件數目、形狀等比 實施例r之°又计’且其元件佈局型態可能更複雜。 請參考圖2,係為本發明電容元件埋入半導體封裝基板 20 1304255 結構剖視圖。如圖2所示，係包括一内層電路板25、一介電 層26、以及·外層線路層30。在内層電路板2 5中具有一内 層線路層25a，此内層線路層25a係為一銅層，而此内層電 路板25也可包含有一内部電鍍導通孔25b，此内部電鑛導通 5 孔25b又包括一絕緣樹脂25c，且内壁的材料係為銅，以導 通於内層電路板25兩側的内層線路層25a。介電層26則配置 於内層電路板25兩側，其所使用的材料可為ABF(Ajinomoto1304255 IX. Description of the invention: [Technical field of the invention] and a capacitor element embedded in a semiconductor package substrate structure: a gas-making method, especially a capacitor element suitable for improving leakage phenomenon of a capacitor material and unevenness of thickness and thickness A buried semiconductor package substrate structure and a method of fabricating the same. [Prior Art] Due to the advancement of the semiconductor process and the improvement of the circuit function on the semiconductor wafer H), the development of the semiconductor device is highly integrated. However, the accumulation of the + conductors, the number of pins in the package structure also increases, and the number of pins and the number of lines are increased, so that the noise is also increased. Therefore, generally to eliminate noise or power. The compensation is based on the addition of passive components such as resistive components, capacitor materials and inductor elements to the semiconductor package structure to eliminate noise and stabilize the circuit, so that the packaged semiconductor wafer meets the electrical characteristics. ~ In the traditional method, the capacitive element is mainly placed on the surface of the substrate by surface mount technology (SMT). At present, many researches use a press-bonding method to bond the high dielectric material to the copper layer. 〇^ Re-create the circuit to form a capacitive element. As shown in the figure of the ice, it is a cross-sectional view of the structure in which the capacitive element is formed by the current pressing method. It mainly provides an inner circuit board 11, a high dielectric material layer 12, an outer circuit layer 13, a plated through hole (PTH) 14, a solder resist layer 15, and a solder ball 16. The inner circuit board 11 has an inner circuit layer 1304255-lla; the high dielectric material layer 12 is pressed onto the inner circuit layer 11a, and then the enamel; the outer layer 129 is formed on the surface of the enamel material layer 12. 3. Thus, a capacitive element is formed via this. The electric mine via 14 can conduct the lines on both sides of the substrate. Then, the subsequent processes are continued to form the solder resist layer 15 and the solder solder balls 16. However, the cost of this method of pressing a single piece of high dielectric material is quite high, but material waste is caused if only a small area is used. In addition, there is a problem of pore filling, because the entire sheet of high dielectric material has poor flowability, so it is easy to have voids and the occurrence of uneven thickness. In addition, there is still another problem with this method, that is, there is a leakage problem of electrical connection between the lines, because the high dielectric material of the whole piece is prone to current leakage, especially at high frequencies. serious. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the present invention provides a capacitor element embedded in a semiconductor package substrate structure comprising an inner circuit board, a dielectric layer and an outer circuit layer. There may be an inner wiring layer in the inner circuit board. The dielectric layer can be disposed on both sides of the inner circuit board, and the dielectric layer has a plurality of first conductive blind holes, and the first conductive blind holes can be sequentially passed through a thin metal layer, a capacitor material, An electrode layer and an adhesive layer are electrically connected to the inner circuit layer. As for the outer circuit layer, it can be disposed on the surface of the dielectric layer. The capacitor material and the electrode layer can be used as a capacitor element. The capacitor element embedded in the semiconductor package substrate can save material, no hole filling problem, and leakage problem of capacitance between wireless circuits. 1304255: The dielectric layer in the present invention may include at least a hole which is electrically connected to the inner circuit layer. The present invention may include an external plating via, and the layer is electrically connected to the surface of the dielectric layer disposed on both sides of the inner circuit board. The wiring according to the present invention has a buried selective capacitance element. The semiconductor package substrate can be fabricated, for example, by the following steps, but is not limited thereto. The present invention also provides a capacitor element buried in a semiconductor package substrate structure, and the method includes the steps of: firstly, providing a metal carrier board; 0 surface is composed of a plurality of I-capacity materials, and a surface of the capacitor material forms an electrode layer. Then, an adhesion I is formed on the surface of the electrode layer, and then an inner circuit board is connected to the metal carrier via the adhesive layer. The thickness of the metal carrier is reduced. Then, the metal carrier that is not connected to the capacitor material is removed, and the metal carrier connected to the dielectric material can form a thin metal layer, the metal is 15 layers, the capacitor material and the electrode The layer can form a capacitor element, and a dielectric layer is respectively pressed on both sides of the surface of the inner circuit board, and a plurality of first blind holes are formed in the dielectric layer, and the first blind hole can correspond to A metal thin layer formed by the metal carrier plate, and finally a first conductive blind hole and an outer circuit layer respectively formed on the surface of the first blind via and the dielectric layer. 20 In the present invention, after pressing the dielectric layer, the dielectric layer The electric layer can form at least one second blind hole, which corresponds to the circuit of the inner circuit board, and forms a second conductive blind hole in the at least one second blind hole. Further, the dielectric layer is formed in the dielectric layer. At least one through hole penetrating through the inner layer circuit board and the dielectric layers on both sides thereof, and forming an external plating via hole in the through hole in 1304255. In the present invention, the inner layer circuit board includes Forming an internal plating via. The inner plating via may be via copper, tin, nickel, chromium, titanium, copper-chromium alloy or tin-lead alloy to turn on the lines on both sides of the inner circuit board. Preferably, 5 may use copper. In addition, the electric conduction via hole may further comprise an insulating resin, such as an epoxy resin. According to the above invention, the first conductive blind via and the second conductive blind via internal crucible are filled or unfilled with conductive material. , such conductive materials can be Copper, tin, chrome, titanium, copper, road alloy or tin alloy, preferably copper (H) genus. The first conductive blind hole and the second conductive blind hole can be respectively passed through the electric ore The conductive material is formed in the first blind hole and the second blind hole. According to the invention, the metal thin plate formed by the metal carrier and the metal carrier can be any metal plate, such as copper, or related The alloy may preferably be copper. 15 The capacitor material used in the transfer is a material having a high dielectric constant, preferably a polymer material, a ceramic material, or a ceramic powder. It is composed of a mixture of molecules or the like, and more preferably can be composed of BadUm-tianate, pure titanic acid (Lead zire) and amorphous carbon hydride (Amorphous hydr〇genated _η). One of the groups 20 is formed by being dispersed in a binder. The capacitance of the capacitor is at least about 4 Å, preferably between about 4 〇 and 3 。. At the same time, the capacitor material can be formed by means of crossing, printing or coating. More preferably, it can be formed by printing. The material used in the electrode layer of the present invention may preferably be a copper paste or a silver 8 1304255 paste. Further, it may be formed by means of splashing, printing or coating, and more preferably, it may be formed by printing. The material used for the adhesive layer of the present invention may preferably be one of a group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy and tin-lead alloy. More preferably, the tin material may be used. Made of solder paste. The main function of this adhesive layer is to act as a connection to the inner circuit board. At the same time, the adhesive layer can be formed by screen printing on the surface of the electrode layer. In addition, the dielectric layer used in the present invention may be selected from ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid 10 Crystal Polymer), Pl (Poly-imide), PPE (Poly (phenyleether) )), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide) and other photosensitive or non-photosensitive organic resin, or may be composed of epoxy resin and glass fiber One of the groups. Further, the through hole of the present invention can be formed by mechanical drilling or laser drilling so as to penetrate an inner layer circuit board and dielectric layers on both sides thereof to form an external plating via hole, and the external plating is turned on. The holes may be connected to the circuit layer on the surface of the dielectric layer on both sides of the inner circuit board, and the outer plating via hole further includes an insulating resin such as an epoxy resin. In the above invention, the material used for the wiring layer is preferably one of a group consisting of copper, tin, lanthanum, lanthanum, lanthanum, copper alloy and tin-boat alloy. More preferably, copper can be used as the circuit layer. In the semiconductor package substrate provided by the present invention, a solder mask can be formed directly on the surface of the outer layer and a solder ball can be formed to be connected with the 1304255 chip. The k can also be used as a core plate. The side forms a build-up structure to continue manufacturing subsequent processes for bonding to the wafer. θ The present invention can improve the number of passive components disposed in the semiconductor package substrate, and increase the layout flexibility of the substrate, thereby effectively improving the surface area of the substrate to a light and thin semiconductor device. Further, the present invention utilizes a method of forming a selective capacitance element on a metal carrier and then conducting the "electrical hole or the through hole", thereby not only saving material but also having problems of voids and uneven thickness. The same can be: the leakage problem of the capacitance phenomenon between the roads. It also simplifies the process and makes it more accurate. [Embodiment] The embodiments of the present invention are described by way of specific embodiments of the present invention. The person skilled in the art can easily == his advantages and effects by the contents disclosed in the present specification. The present invention may also be implemented or applied by other different ==, the details in the specification are also modified and (4) the application is carried out in the embodiment of the present invention. A simplified schematic. However, it is true that: m is a component related to the invention, and the component to be displayed is not exemplified by two: η, and the number and shape of components in actual implementation are inferior to those of the embodiment r and the component layout type It may be more complicated. Please refer to FIG. 2, which is a cross-sectional view showing the structure of the capacitor element embedded in the semiconductor package substrate 20 1304255 of the present invention. As shown in Fig. 2, an inner circuit board 25, a dielectric layer 26, and an outer wiring layer 30 are included. The inner circuit board 25 has an inner circuit layer 25a, and the inner circuit layer 25a is a copper layer. The inner circuit board 25 can also include an inner plating via 25b. The internal electric current is electrically connected to the 5 hole 25b. An insulating resin 25c is included, and the material of the inner wall is copper to conduct the inner wiring layer 25a on both sides of the inner circuit board 25. The dielectric layer 26 is disposed on both sides of the inner circuit board 25, and the material used may be ABF (Ajinomoto).
Build-up Film )、BCB (Benzocyclo-buthene)、LCP (Liquid Crystal Polymer)、Pl(Poly-imide)、PPE (Poly(phenylene 10 ether))、PTFE(Poly (tetra-fluoroethylene))、FR4、FR5、 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)等感光或非 感光有機樹脂，或亦可混合環氧樹脂與玻璃纖維等材質所 組成之群組其中之一者，而本實施例則使用ABF。另介電 層26内具有第一導電盲孔31a及第二導電盲孔3lb，第一導 15 電盲孔3 la依序係經由一金屬薄層21a、一電容材料22、一 電極層23及一黏著層24與内層線路層25a導通。第二導電盲 孔3lb係與内層線路層25a導通。在此，第一導電盲孔31a及 务'一導電盲孔使用的材料為銅、錫、錄、絡、欽、銅_ 鉻合金或錫-鉛合金，本實施例則使用銅金屬，且未填滿於 20 第一導電盲孔31 a及第二導電盲孔31b中。而金屬薄層21 a可 以使用的材料例如為銅、鋁或其相關合金，本實施例則使 用銅。電容材料22在本實施例中則使用陶瓷材料。電極層 23則使用銅膏或銀膏。黏著層24則使用以錫作為材料的錫 膏。又，電容材料22與電極層23可以形成一被動元件，即 11 1304255 電容元件。 接著，介電層26表面可配置有一外層線路層3〇，且在 此結構中亦可配置一外部電鍍導通孔32,其係可導通配置 於内層電路板25兩側之介電層26表面之外層線路層30。其 5中外層線路層30與外部電链導通孔32所需導通的材料係 可為銅、錫、鎳、鉻、鈦、銅-鉻合金或錫省合金，本實施 例則使用銅金屬。 實施例2 清參考圖3,係為本發明電容元件埋入半導體封裝基板 1〇 :構^視圖°如圖3所示’其結構與實施例2的結構大致相 同，但不同的是，本實施例的第—導電盲孔仏及第二導電 盲孔31d係填滿材料，即填滿鋼金屬。 實施例3 夺只靶例使用的材料係可如實施例丨的材料相同。本實 15加例係主要在於製作的方法，請參考圖4A至4『，係為具有 埋入式選擇性電容元件之半導體封裝基板的製作方法 視圖。 如圖4八所示，首先，提供一金屬載板Μ，此金屬載板 21使用的材料可為鋼板，於其表面選擇性地利 用塗佈或印 2〇刷的方式形成複數個電容材料22，再於這些電容材料22表 面乂同樣的方式形成一電極層23，經過高溫燒結後可形成 一電容元件。 接著’如圖4B所示’於電極層23上利用網版印刷形成 可溶金屬之黏著層24。再如圖4c所示，經由此黏著層Μ 12 1304255 .而將電容元件迴焊至内層電路板25的内層線路層仏上。 然後，如圖4D所示，利用餘刻的方式將金屬載板㈣ 薄。再繼續如圖4Ε所示，再利用银刻的方式將未與電容材 料22連接的金屬載板21移除，即僅剩下與電容材⑽連接 5 的部分，因而形成一金屬薄層2U。 再如圖4F所示，於㈣層電路妨兩側分別壓合一介電 層26或背膠銅箱（Resign c崎d c〇pper，未圖示），於介電層 或背膠銅箱内利用雷射鑽孔而形成第一盲孔遍以及第二 盲孔26b，經由雷射鑽孔或機械鑽孔直接貫穿介電層26(或 1〇 f膠銅箱）及内層電路板25,而形成一通孔26c。然後，於此 、。構表面及第一目孔26a、第二盲孔施以及通孔26c之内 土利用無t電鑛的方式形成一導電層㈣以一叫27，此 導電層27係主要作為後續製程所需之電流傳導路徑。其使 用的材料例如可為銅。 15 接著，如圖4G所示，於前述結構的表面，即於導電層 27上可以電鑛的方式形成_金屬層28，並且於具有金屬層 28之通孔26e填人絕緣樹脂29而得到—外部電鐘導通孔 32其中，電鍍導通孔32係主要為導通介電層加表面的線 路之用再如圖4H所不，於介電層26表面的金屬層28，利 20用蝕刻之方式使其形成一線路層30。 电此外，亦可使用半加成法，如圖，所示，於導電層W a面幵圖案化之阻層5卜此阻層可為乾膜練態光阻 、-有複數個開口 52並且亦顯露出通孔26〇、第一盲孔施 以及第二盲孔鳥，於開口 52内以電鍍的方式形成金屬層 13 1304255 28,再如圖4H’所示，於具有金屬層28之通孔26c填入絕緣 樹脂29而得到一外部電鍍導通孔32,舞阻層51及其所覆 蓋之導電層27。即於介電層26表面形成線路層％。 在此，本實施例僅簡單例示上述此二種類型而已。事實 5上，不論是由圖扣之直接電鍍金屬層28或是由圖扣，中使用 半加成法而得之金屬層28，均可在第-盲孔26a及第二盲孔 26b中得到如圖4H所示之未填滿金屬層28而之第—導電盲 孔31a及第二導電盲孔31b，當然，亦可依製程需要形成如 圖中為填滿金屬層28的第—導'電盲孔31c及第二導電盲 10 孔 31d〇 因此’可得到本發明電容元件埋入半導體封裝基板結構 20a，20b。 再者，如圖41及41’所示’此半導體封裝基板結構 術，勘，可於其表面塗覆—層防焊層41，以及形成凸塊❿ 15 而可經由凸塊42與晶片43連接。 綜上所述，由於一般習知技術中，係將被動元件，例 • #電容元件等，安置於基板上未被半導體晶片所佔據之多 餘佈局面積上。然而，此種佈局方法需要較大尺寸的基板 來實施。雖然也有研究以壓合的方式將電容元件拔埋至基 20板中’然而，利用整片高介電材料壓合，其成本很高，如 僅使用少數面積，會造成材料浪費。同時會有孔隙以及漏 電的問題。本發明之電容元件埋入半導體封裝基板結構， 利用在承載板上製作電容元件再以導電盲孔或通孔導通的 方式解決了前述的問題。同時，可提升半導體裝置内被動 14 1304255 元件之佈設數量，並增加基板線路佈局的靈活性，可有效 提升基板表面使用面積，以達半導體裝置輕薄短小之目 標，提升電子產品之電性功能，而又不致影響其線路佈局 性。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 10 圖1係習知之壓合式電容元件之半導體封裝基板結構 剖視圖。 圖2及圖3係本發明較佳實施例之電容元件埋入半導體 封裝基板結構剖視圖。 圖4A至4H’係本發明一較佳實施例之電容元件埋入半 15導體封裝基板結構製作流程剖視圖。 圖41及4Γ係本發明一較佳實施例之與晶片連接之半導 體封裝基板結構剖視圖。 【主要元件符號說明】 11,25 内層電路板 12 高介電材料層 14 導通孔 16 焊料錫球 21 金屬載板 lla，25a内層線路層 13 外層線路層 15,41 防焊層 20a，20b半導體封裝基板結構 21a 金屬薄層 15 1304255 22 電容材料 23 電極層 24 黏著層 25b 内部電鍍導通孔 25c，29 絕緣樹脂 26a 第一盲孔 26b 第二盲孔 26c 通孔 27 導電層 28 金屬層 30 外層線路層 31a 第一導電盲孔 31b 第二導電盲孔 32 外部電鍍導通孔 43 晶片 42 凸塊 51 阻層 52 開口 16Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), Pl (Poly-imide), PPE (Poly (phenylene 10 ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5 A photosensitive or non-photosensitive organic resin such as BT (Bismaleimide Triazine) or aromatic polyamide (Aramide), or a group of materials such as epoxy resin and glass fiber may be mixed, and in this embodiment, ABF is used. The dielectric layer 26 has a first conductive blind via 31a and a second conductive blind via 31b. The first conductive via 34b is sequentially passed through a thin metal layer 21a, a capacitor material 22, an electrode layer 23, and An adhesive layer 24 is electrically connected to the inner wiring layer 25a. The second conductive blind via 31b is electrically connected to the inner wiring layer 25a. Here, the material used for the first conductive blind via 31a and the conductive via is copper, tin, ruthenium, complex, chin, copper chrome or tin-lead alloy. In this embodiment, copper metal is used, and Filled in 20 first conductive blind holes 31 a and second conductive blind holes 31 b. The material in which the thin metal layer 21a can be used is, for example, copper, aluminum or a related alloy thereof, and copper is used in this embodiment. The capacitor material 22 is a ceramic material in this embodiment. The electrode layer 23 is made of a copper paste or a silver paste. The adhesive layer 24 uses a tin paste as a material. Further, the capacitor material 22 and the electrode layer 23 can form a passive component, that is, a capacitor of 11 1304255. Then, the outer surface of the dielectric layer 26 may be disposed with an outer layer of the wiring layer 3, and an externally-plated via 32 may be disposed in the surface of the dielectric layer 26 to be electrically connected to the surface of the dielectric layer 26 disposed on both sides of the inner circuit board 25. Outer circuit layer 30. The material required to conduct the outer layer circuit layer 30 and the outer electric chain via 32 may be copper, tin, nickel, chromium, titanium, copper-chromium alloy or tin alloy. In this embodiment, copper metal is used. Embodiment 2 Referring to FIG. 3, the capacitor element of the present invention is embedded in a semiconductor package substrate. The structure is substantially the same as that of Embodiment 2, but the difference is that the present embodiment is different. The first conductive via hole and the second conductive blind hole 31d are filled with material, that is, filled with steel metal. Example 3 The material used for the target example was the same as that of the example. The present invention is mainly for the method of fabrication. Please refer to FIG. 4A to FIG. 4, which is a view of a method for fabricating a semiconductor package substrate having a buried selective capacitance element. As shown in FIG. 4, first, a metal carrier plate is provided. The metal carrier plate 21 may be made of a steel plate, and a plurality of capacitor materials 22 are selectively formed on the surface by coating or printing. An electrode layer 23 is formed in the same manner as the surface of the capacitor material 22, and a capacitor element is formed after high-temperature sintering. Next, as shown in Fig. 4B, an adhesive layer 24 of a soluble metal is formed by screen printing on the electrode layer 23. Further, as shown in FIG. 4c, the capacitive element is reflowed to the inner layer layer of the inner layer circuit board 25 via the adhesive layer 12 1304255. Then, as shown in Fig. 4D, the metal carrier (4) is thinned by means of a residual. Further, as shown in Fig. 4A, the metal carrier 21 not connected to the capacitor material 22 is removed by silver etching, that is, only the portion connected to the capacitor member (10) is left, thereby forming a thin metal layer 2U. As shown in FIG. 4F, a dielectric layer 26 or a backing copper box (Resign c dc 〇pper, not shown) is respectively laminated on both sides of the (four) layer circuit, in the dielectric layer or the backing copper box. The first blind via and the second blind via 26b are formed by laser drilling, and the dielectric layer 26 (or 1 〇f copper copper box) and the inner circuit board 25 are directly penetrated through the laser drilling or mechanical drilling. A through hole 26c is formed. Then, here, . The surface of the structure and the first hole 26a, the second blind hole and the inner hole of the through hole 26c form a conductive layer (4) by means of no electric ore, and the conductive layer 27 is mainly used as a subsequent process. Current conduction path. The material used may be, for example, copper. 15 Next, as shown in FIG. 4G, a metal layer 28 may be formed on the surface of the foregoing structure, that is, on the conductive layer 27, and the insulating layer 29 may be filled in the through hole 26e having the metal layer 28. The external electric clock via 32 is formed by electrically etching the via 32 to the surface of the dielectric layer plus the surface. The metal layer 28 on the surface of the dielectric layer 26 is etched by etching. It forms a wiring layer 30. In addition, a semi-additive method may also be used. As shown in the figure, the resist layer 5 is patterned on the surface of the conductive layer Wa, and the resist layer may be a dry film smoothing photoresist, and has a plurality of openings 52 and The through hole 26〇, the first blind hole and the second blind hole bird are also exposed, and the metal layer 13 1304255 28 is formed in the opening 52 by electroplating, and then the metal layer 28 is connected as shown in FIG. 4H′. The hole 26c is filled with the insulating resin 29 to obtain an external plating via 32, the dance resist layer 51 and the conductive layer 27 covered thereon. That is, the circuit layer % is formed on the surface of the dielectric layer 26. Here, the present embodiment simply exemplifies the above two types. In fact 5, whether the metal layer 28 is directly plated by the button or the metal layer 28 obtained by the semi-addition method can be obtained in the first blind hole 26a and the second blind hole 26b. As shown in FIG. 4H, the first conductive via 31a and the second conductive via 31b, which are not filled with the metal layer 28, may of course be formed as shown in the figure to fill the metal layer 28 as shown in the figure. The electric blind hole 31c and the second conductive blind 10 hole 31d can thus be obtained by embedding the capacitive element of the present invention in the semiconductor package substrate structure 20a, 20b. Furthermore, as shown in FIGS. 41 and 41', the semiconductor package substrate structure can be coated with a solder resist layer 41 and a bump 15 can be formed to be connected to the wafer 43 via bumps 42. . In summary, in the conventional art, passive components, such as #capacitor components, are disposed on a substrate that is not occupied by a semiconductor wafer. However, such a layout method requires a larger-sized substrate to be implemented. Although it has been studied to bury the capacitor element into the base plate in a press-fit manner, however, the cost of pressing the entire piece of high dielectric material is high, and if only a small area is used, material waste is caused. At the same time, there are problems with pores and leakage. The capacitor element of the present invention is embedded in the semiconductor package substrate structure, and the above problem is solved by fabricating the capacitor element on the carrier board and conducting the conductive via hole or via hole. At the same time, the number of passive 14 1304255 components in the semiconductor device can be increased, and the flexibility of the layout of the substrate can be increased, and the surface area of the substrate can be effectively improved to achieve the goal of thin and thin semiconductor devices, thereby improving the electrical functions of the electronic products. It does not affect the layout of the line. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing the structure of a semiconductor package substrate of a conventional pressure-sensitive capacitive element. 2 and 3 are cross-sectional views showing the structure of a capacitor element embedded in a semiconductor package substrate in accordance with a preferred embodiment of the present invention. 4A to 4H are cross-sectional views showing a manufacturing process of a capacitor-embedded half-conductor package substrate according to a preferred embodiment of the present invention. 41 and 4 are cross-sectional views showing the structure of a semiconductor package substrate to which a wafer is bonded in accordance with a preferred embodiment of the present invention. [Main component symbol description] 11,25 inner layer circuit board 12 high dielectric material layer 14 via hole 16 solder ball 21 metal carrier board 11a, 25a inner layer circuit layer 13 outer layer layer 15, 41 solder resist layer 20a, 20b semiconductor package Substrate structure 21a Metal thin layer 15 1304255 22 Capacitor material 23 Electrode layer 24 Adhesive layer 25b Internal plating via 25c, 29 Insulating resin 26a First blind hole 26b Second blind hole 26c Via hole 27 Conductive layer 28 Metal layer 30 Outer layer 31a first conductive blind hole 31b second conductive blind hole 32 external plating via 43 wafer 42 bump 51 resist layer 52 opening 16