CN107871786A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107871786A
CN107871786A CN201710883116.8A CN201710883116A CN107871786A CN 107871786 A CN107871786 A CN 107871786A CN 201710883116 A CN201710883116 A CN 201710883116A CN 107871786 A CN107871786 A CN 107871786A
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drift region
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CN107871786B (zh
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大川峰司
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Denso Corp
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Toyota Motor Corp
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Abstract

本发明提供一种半导体装置，在具有纵型漂移区域(即，JFET区域)的半导体装置中，改善存在于耐压与接通电阻之间的此消彼长的关系。半导体装置(1)具备在氮化物半导体层(20)的表面上的一部分设置的P型半导体区域(42)。P型半导体区域(42)与纵型漂移区域(21b)向氮化物半导体层(20)的表面露出的范围的至少一部分对向。

Description

半导体装置
技术领域
本说明书公开的技术涉及半导体装置。
背景技术
图4所示的以往的半导体装置100具备N型的半导体基板110、层叠在半导体基板110上的半导体层120、将半导体基板110的背面覆盖的漏电极132、将半导体层120的表面覆盖的源电极134、及在半导体层120的表面上的一部分设置的绝缘栅极部136。半导体层120具有N型的漂移区域121、P型的体区域123、P型的接触区域124及N型的源极区域125。漂移区域121由横型漂移区域121a和纵型漂移区域121b构成，该纵型漂移区域121b向半导体层120的表面露出。在本说明书中，有时也将纵型漂移区域121b特别称为JFET区域。
体区域123配置在与纵型漂移区域121b相邻的位置，且向半导体层120的表面露出。接触区域124向半导体层120的表面露出，且与源电极134电连接。源极区域125被体区域123从纵型漂移区域121b隔开，向半导体层120的表面露出，且与源电极134电连接。绝缘栅极部136的栅电极136b隔着栅极绝缘膜136a与将纵型漂移区域121b和源极区域125隔开的部分的体区域123对向。绝缘栅极部136的栅电极136b通过层间绝缘膜152而从源电极134绝缘分离。
在该半导体装置100接通(on)时，通过栅电极136b的电位而在将纵型漂移区域121b和源极区域125隔开的部分的体区域123形成反转层，经由该反转层从源极区域125向纵型漂移区域121b流入电子。流入到纵型漂移区域121b的电子在纵型漂移区域121b中沿着纵向流动而前往漏电极132。由此，漏电极132与源电极134导通。
在半导体装置100断开(off)时，耗尽层从体区域123向纵型漂移区域121b内延伸。纵型漂移区域121b被设计成，在半导体装置100断开时，通过从两侧延伸的耗尽层相连而成为夹断的状态。通过纵型漂移区域121b夹断，向绝缘栅极部136的栅极绝缘膜136a施加的电场得到缓和，栅极绝缘膜136a的绝缘破坏受到抑制，半导体装置100的耐压提高。需要说明的是，当半导体装置100接通时，纵型漂移区域121b与体区域123的电位变成大致相等，耗尽层消失。由N型的纵型漂移区域121b和P型的体区域123构成了JFET构造。专利文献1公开了具有纵型漂移区域(即，JFET区域)的半导体装置的一例。
在先技术文献
专利文献
专利文献1：日本特开2015-041719号公报
发明内容
发明要解决的课题
为了使纵型漂移区域121b良好地夹断而抑制栅极绝缘膜136a的绝缘破坏，优选将纵型漂移区域121b的杂质浓度设定得淡。然而，当纵型漂移区域121b的杂质浓度淡时，纵型漂移区域121b的电阻升高，半导体装置100的接通电阻增加。
这样，在具有纵型漂移区域的半导体装置中，在耐压与接通电阻之间存在此消彼长的关系。因此，在具有纵型漂移区域的半导体装置中，希望开发出一种改善这样的此消彼长关系的技术。
用于解决课题的方案
本说明书公开的半导体装置具备半导体层、在半导体层的一个主面上的一部分设置的绝缘栅极部、及在半导体层的所述主面上的另外的一部分设置的第一导电型半导体区域。半导体层具有第二导电型的纵型漂移区域、第一导电型的体区域及第二导电型的源极区域。纵型漂移区域向半导体层的所述主面露出。体区域与纵型漂移区域相邻，且向半导体层的所述主面露出。源极区域被体区域从纵型漂移区域隔开，且向半导体层的所述主面露出。绝缘栅极部与将纵型漂移区域和源极区域隔开的体区域对向。第一导电型半导体区域与纵型漂移区域向半导体层的所述主面露出的范围的至少一部分对向。
在上述半导体装置断开时，耗尽层从第一导电型半导体区域向纵型漂移区域内延伸。由此，在上述半导体装置中，能够良好地对纵型漂移区域的表面部进行耗尽化，因此能够缓和向在纵型漂移区域的表面部附近配置的绝缘栅极部的栅极绝缘膜施加的电场。换言之，在上述半导体装置中，即使纵型漂移区域的杂质浓度被设定得浓，也能够缓和向绝缘栅极部的栅极绝缘膜施加的电场。这样，上述半导体装置能够改善耐压与接通电阻之间的此消彼长关系。
附图说明
图1示意性地示出半导体装置的主要部分剖视图。
图2示意性地示出变形例1的半导体装置的主要部分剖视图。
图3示意性地示出变形例2的半导体装置的主要部分剖视图。
图4示意性地示出以往的半导体装置的主要部分剖视图。
具体实施方式
如图1所示，半导体装置1具备N型的半导体基板10、层叠在半导体基板10上的半导体层20、在半导体层20的表面上的一部分层叠的P型半导体区域42、覆盖半导体基板10的背面的漏电极32、覆盖半导体层20的表面的源电极34、及在半导体层20的表面上的一部分设置的绝缘栅极部36。半导体层20具有N型的漂移区域21、P型的体区域(body region)23、P型的接触区域24及N型的源极区域25。漂移区域21由横型漂移区域21a和纵型漂移区域21b构成，该纵型漂移区域21b向半导体层20的表面露出。P型半导体区域42不是半导体层20的一部分，而是在半导体层20的上侧的主面的一部分形成。
半导体基板10以包含高浓度的N型杂质的碳化硅(SiC)为材料。漏电极32与半导体基板10的背面整体进行欧姆接触。半导体基板10是用于供半导体层20进行外延生长的基底基板。
半导体层20在半导体基板10上进行外延生长而堆积。半导体层20以包含浓度比半导体基板10低的N型杂质的碳化硅(SiC)为材料。在半导体层20形成有后述的多个种类的扩散区域。
漂移区域21构成为在半导体层20形成了多个种类的半导体区域后的剩余部，具有横型漂移区域21a及纵型漂移区域21b。横型漂移区域21a配置在半导体基板10上。纵型漂移区域21b以具有从横型漂移区域21a突出的凸状的形态的方式配置在横型漂移区域21a上，并向半导体层20的表面的一部分露出。在从与半导体层20的表面正交的方向(纸面上下方向)观察时，纵型漂移区域21b沿着长度方向(纸面向里方向)呈直线状地延伸。
体区域23配置在横型漂移区域21a上，配置在纵型漂移区域21b的两侧，并且向半导体层20的表面露出。体区域23包含低浓度的P型杂质。体区域23通过利用离子注入技术朝向半导体层20的表面照射氮或铝而形成。
接触区域24配置在体区域23上，向半导体层20的表面露出。接触区域24包含高浓度的P型杂质，与源电极34进行欧姆接触。接触区域24通过利用离子注入技术朝向半导体层20的表面照射氮或铝而形成。
源极区域25配置在体区域23上，被体区域23从漂移区域21隔开，并且向半导体层20的表面露出。源极区域25包含高浓度的N型杂质，与源电极34进行欧姆接触。源极区域25通过利用离子注入技术朝向半导体层20的表面照射磷而形成。
P型半导体区域42层叠设置于半导体层20的表面上的一部分。准确地说，P型半导体区域42以与纵型漂移区域21b向半导体层20的表面露出的范围的一部分接触的方式设置，被纵型漂移区域21b从体区域23隔开。P型半导体区域42的厚度比绝缘栅极部36的栅极绝缘膜36a的厚度厚。P型半导体区域42以P型的碳化硅(SiC)为材料。P型半导体区域42通过在利用外延生长技术堆积在半导体层20的表面上之后利用蚀刻技术进行图案化来形成。P型半导体区域42经由贯通层间绝缘膜52及绝缘栅极部36的贯通孔而与源电极34进行欧姆接触。
绝缘栅极部36设置在半导体层20的表面上的一部分，具有氧化硅的栅极绝缘膜36a及多晶硅的栅电极36b。详细而言，栅极绝缘膜36a覆盖将纵型漂移区域21b和源极区域25隔开的部分的体区域23的表面、P型半导体区域42与体区域23之间的纵型漂移区域21b的表面、P型半导体区域42的侧面、及P型半导体区域42的表面的一部分。栅电极36b隔着栅极绝缘膜36a与将纵型漂移区域21b和源极区域25隔开的部分的体区域23对向，并且隔着栅极绝缘膜36a也与P型半导体区域42和体区域23之间的纵型漂移区域21b的表面对向。栅电极36b通过层间绝缘膜52而从源电极34绝缘分离。
接下来，说明半导体装置1的动作。在使用时，向漏电极32施加正电压，将源电极34接地。当向栅电极36b施加比栅极阈值高的正电压时，在将纵型漂移区域21b和源极区域25隔开的部分的体区域23形成反转层，半导体装置1开启。此时，经由反转层从源极区域25向纵型漂移区域21b流入电子。流入到纵型漂移区域21b的电子在该纵型漂移区域21b中沿着纵向流动而前往漏电极32。由此，漏电极32与源电极34导通。
当将栅电极36b接地时，反转层消失，半导体装置1关闭。此时，耗尽层从体区域23向纵型漂移区域21b内延伸。除此之外，P型半导体区域42与纵型漂移区域21b之间的接合面也被反向偏置，因此耗尽层从P型半导体区域42向纵型漂移区域21b内延伸。由此，在半导体装置1中，能够良好地对纵型漂移区域21b的表面部进行耗尽化，因此能够缓和向在纵型漂移区域21b的表面部附近配置的绝缘栅极部36的栅极绝缘膜36a施加的电场。尤其是，在半导体装置1中，在纵型漂移区域21b的表面上也配设有绝缘栅极部36，向该部分的栅极绝缘膜36a施加的电场良好地得到缓和。因此，绝缘栅极部36的栅极绝缘膜36a的绝缘破坏受到抑制，半导体装置1能够具有高的耐压。
在半导体装置1中，为了减小纵型漂移区域21b的JFET电阻，纵型漂移区域21b的杂质浓度浓。在这样的情况下，在半导体装置1断开时，从体区域23向纵型漂移区域21b内延伸的耗尽层相连而成为夹断的状态的动作受到抑制，可能会向绝缘栅极部36的栅极绝缘膜36a施加高电场。然而，在半导体装置1中，如上所述，在纵型漂移区域21b夹断之前通过从P型半导体区域42延伸的耗尽层对纵型漂移区域21b的表面部进行了耗尽化，向绝缘栅极部36的栅极绝缘膜36a施加的电场得到了缓和。即，即使为了形成为低的接通电阻而将纵型漂移区域21b的杂质浓度设定得浓，也能抑制绝缘栅极部36的栅极绝缘膜36a的绝缘破坏，半导体装置1能够具有高的耐压。其结果是，半导体装置1能够改善耐压与接通电阻之间的此消彼长(trade-off)关系。
另外，在半导体装置1中，P型半导体区域42设置在半导体层20的表面上。换言之，P型半导体区域42没有配置在纵型漂移区域21b内。因此，在半导体装置1接通时，不会缩窄电子的移动路径，因此接通电阻不会增大。
另外，在半导体装置1中，由于P型半导体区域42与源电极34电连接，因此在开启时对P型半导体区域42内的耗尽层快速地供给空穴。因此，在开启时纵型漂移区域21b内的耗尽层快速地消失。其结果是，抑制了电子的移动路径被从P型半导体区域42与纵型漂移区域21b之间的接合面向纵型漂移区域21b内延伸的耗尽层缩窄的事态，抑制了开启损失的增加。
另外，半导体装置1以碳化硅为材料而构成。使用了碳化硅的半导体装置1为了充分地发挥碳化硅具有的高绝缘破坏电场这一特性而将半导体层20的厚度设计得比较薄，在向栅极绝缘膜36a施加高电场这样的条件下使用。由于向栅极绝缘膜36a施加的电场得到缓和，因此半导体装置1能够充分地发挥碳化硅具有的高绝缘破坏电场这一特性而进行动作。需要说明的是，即便取代碳化硅而使用氮化物半导体作为材料也是同样，半导体装置1能够充分地发挥氮化物半导体具有的高绝缘破坏电场这一特性而进行动作。
(变形例1)
图2所示的变形例的半导体装置2的特征在于，P型半导体区域42与绝缘栅极部36的栅电极36b进行欧姆接触。在该变形例中，在半导体装置2接通时，P型半导体区域42与纵型漂移区域21b之间的接合面被正向偏置，从P型半导体区域42向漂移区域21内注入空穴。由此，在漂移区域21内发生电导率调制(conductivity modulation)，因此漂移电阻下降。半导体装置2能够具有低的接通电阻。
另外，在半导体装置2中，P型半导体区域42也与栅电极36b电连接，因此在打开时也对P型半导体区域42内的耗尽层快速地供给空穴。由此，在半导体装置2中也抑制了开启损失的增加。
(变形例2)
图3所示的变形例的半导体装置3的特征在于，具备设置在P型半导体区域42与纵型漂移区域21b之间的N型或I型的中间半导体区域44。在此，在半导体装置3中，半导体基板10、半导体层20及P型半导体区域42以氮化镓(GaN)为材料，中间半导体区域44以氮化铝镓(AlGaN)为材料。因此，中间半导体区域44与纵型漂移区域21b进行异质接合，在半导体装置3接通时，在纵型漂移区域21b的表面部生成二维电子气体。由于在二维电子气体中存在高密度的电子载流子，因此纵型漂移区域21b的表面部的电阻大幅下降。由此，半导体装置3的接通电阻下降。
中间半导体区域44的厚度及杂质浓度被调整成，在半导体装置3断开时，从P型半导体区域42延伸的耗尽层超过中间半导体区域44而也在纵型漂移区域21b内形成。因此，在半导体装置3中，也由从P型半导体区域42延伸的耗尽层对纵型漂移区域21b的表面部进行了耗尽化，向绝缘栅极部36的栅极绝缘膜36a施加的电场也得到了缓和。
需要说明的是，在半导体装置3中，中间半导体区域44也可以设置成与纵型漂移区域21b向半导体层20的表面露出的整个范围接触。此外，P型半导体区域42也可以设置成与纵型漂移区域21b向半导体层20的表面露出的整个范围对向。这种情况下，在纵型漂移区域21b的表面部的大范围内生成二维电子气体，因此半导体装置3能够具有更低的接通电阻。
以下，对本说明书公开的技术特征进行整理。需要说明的是，以下记载的技术要素是分别独立的技术要素，以单独或各种组合的形式来发挥技术有用性，不限定于申请时权利要求记载的组合。
本说明书公开的半导体装置可以具备半导体层、在半导体层的一个主面上的一部分设置的绝缘栅极部、及在半导体层的所述主面上的另外的一部分设置的第一导电型区域。半导体层可以具有第二导电型的漂移区域、第一导电型的体区域及第二导电型的源极区域。漂移区域具有向半导体层的所述主面露出的纵型漂移区域。体区域以将纵型漂移区域置于中间的方式配置(配置在纵型漂移区域的相邻的位置)，向半导体层的所述主面露出。源极区域被体区域从纵型漂移区域隔开，向半导体层的所述主面露出。绝缘栅极部与将纵型漂移区域和源极区域隔开的体区域对向。在绝缘栅极部与半导体层之间也可以存在其他的层。第一导电型半导体区域与纵型漂移区域向半导体层的所述主面露出的范围的至少一部分对向。在第一导电型半导体区域与半导体层之间也可以存在其他的层。
在上述半导体装置中，第一导电型半导体区域与纵型漂移区域向半导体层的所述主面露出的范围的一部分接触，被纵型漂移区域从体区域隔开。由于第一导电型半导体区域与纵型漂移区域直接接触，因此通过从第一导电型半导体区域延伸的耗尽层能够良好地对纵型漂移区域的表面部进行耗尽化，能够良好地缓和向绝缘栅极部的栅极绝缘膜施加的电场。
上述半导体装置可以还具备源电极，该源电极覆盖半导体层的所述主面，并与源极区域电连接。此外，第一导电型半导体区域可以与源电极电连接。这种情况下，在半导体装置开启了时，从第一导电型半导体区域向纵型漂移区域内延伸的耗尽层快速地消失，因此能够抑制半导体装置的开启损失的增加。
在上述半导体装置中，第一导电型半导体区域可以与绝缘栅极部的栅电极电连接。这种情况下，在半导体装置接通时，从第一导电型半导体区域向纵型漂移区域注入载流子，在漂移区域发生电导率调制。该半导体装置能够具有低的接通电阻。
在上述半导体装置中，半导体层可以是碳化硅或氮化物半导体。半导体装置能够缓和向绝缘栅极部的栅极绝缘膜施加的电场，因此能够充分地发挥碳化硅或氮化物半导体具有的高绝缘破坏电场这一特性而进行动作。
以上，虽然详细地说明了本发明的具体例，但它们只不过是例示，不对权利要求书进行限定。权利要求书记载的技术包括对以上例示的具体例进行各种变形、变更后的技术。而且，本说明书或附图说明的技术要素以单独或各种组合的形式发挥技术有用性，不限定于申请时权利要求记载的组合。而且，本说明书或附图例示的技术能够同时实现多个目的，实现其中一个目的自身就具有技术有用性。
标号说明
1：半导体装置
10：半导体基板
20：半导体层
21：漂移区域
21a：横型漂移区域
21b：纵型漂移区域
23：体区域
24：接触区域
25：源极区域
32：漏电极
34：源电极
36：绝缘栅极部
36a：栅极绝缘膜
36b：栅电极
42：P型半导体区域
52：层间绝缘膜

Claims (5)

1.一种半导体装置，具备：
半导体层；
绝缘栅极部，设置于所述半导体层的一个主面上的一部分；及
第一导电型半导体区域，设置于所述半导体层的所述主面上的另外的一部分，
所述半导体层具有：
第二导电型的纵型漂移区域，向所述主面露出；
第一导电型的体区域，与所述纵型漂移区域相邻，且向所述主面露出；及
第二导电型的源极区域，被所述体区域从所述纵型漂移区域隔开，且向所述主面露出，
所述绝缘栅极部与将所述纵型漂移区域和所述源极区域隔开的所述体区域对向，
所述第一导电型半导体区域与所述纵型漂移区域向所述半导体层的所述主面露出的范围的至少一部分对向。
2.根据权利要求1所述的半导体装置，
所述第一导电型半导体区域与所述纵型漂移区域向所述半导体层的所述主面露出的范围的一部分接触，且被所述纵型漂移区域从所述体区域隔开。
3.根据权利要求1或2所述的半导体装置，
还具备源电极，该源电极覆盖所述半导体层的所述主面，并且与所述源极区域电连接，
所述第一导电型半导体区域与所述源电极电连接。
4.根据权利要求1或2所述的半导体装置，
所述第一导电型半导体区域与所述绝缘栅极部的栅电极电连接。
5.根据权利要求1～4中任一项所述的半导体装置，
所述半导体层是碳化硅或氮化物半导体。
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