CN107797050B - Method for positioning abnormal power-on time sequence state of server mainboard - Google Patents
Method for positioning abnormal power-on time sequence state of server mainboard Download PDFInfo
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Abstract
The invention provides a method for positioning abnormal power-on time sequence state of a server mainboard, which is characterized in that a power-on signal is sent to a first power module of the server mainboard, and whether the power-on of the first power module is normal or not is judged; after the first power supply module is normally powered on, sending a power-on signal to a second power supply module of the server mainboard; judging whether the second power supply module is normally powered on; after the second power supply module is powered on normally, sending a power-on signal to a third power supply module of the server mainboard, and judging whether the third power supply module is powered on normally; and after the third power supply module is normally powered on, repeating the steps until all the power supply modules of the server mainboard are normally powered on. Need not use the universal meter again to measuration one by one power module, improved mainboard test process's work efficiency, also avoided the repetitive work when testing the mainboard anomaly.
Description
Technical Field
The invention relates to the field of servers, in particular to a method for positioning abnormal power-on time sequence states of a server mainboard.
Background
The total of aux electricity and core electricity on the server mainboard is more than ten, the logic design of the mainboard has strict requirements on the power-on and power-off sequence of each power, and during the design of the mainboard, some design errors always occur to cause that the power-on or power-off time sequence can not normally run, thereby causing that the mainboard can not be normally turned on and off and affecting the functions of the whole mainboard.
Therefore, this point should be considered during the design of the motherboard, so that when the power-on and power-off are abnormal, the abnormal power can be quickly located, and the bug can be quickly solved.
In the conventional main board power design, when power-on abnormality occurs, a universal meter is generally used for measuring an enable signal and a powergood signal of each power, and the abnormal powers are checked one by one according to time sequence logic.
When abnormality occurs, repeated operation is carried out, and the pin position information of the enable signal and the powergood signal of each power on the mainboard needs to be searched, so that a great deal of time and energy are consumed.
When power-on abnormal powers are positioned, whether each power is abnormal needs to be checked one by one according to time sequence logic, and the pin positions of each power signal need to be searched. And when the same problem occurs to a plurality of mainboards, the workload is multiplied. This can seriously affect the efficiency of the work and slow down the progress of the whole project.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a method for positioning abnormal power-on time sequence state of a server mainboard, which comprises the following steps:
sending a power-on signal to a first power module of a server mainboard, and judging whether the power-on of the first power module is normal or not;
after the first power supply module is normally powered on, sending a power-on signal to a second power supply module of the server mainboard;
judging whether the second power supply module is normally powered on;
after the second power supply module is powered on normally, sending a power-on signal to a third power supply module of the server mainboard, and judging whether the third power supply module is powered on normally;
and after the third power supply module is normally powered on, repeating the steps until all the power supply modules of the server mainboard are normally powered on.
Preferably, when the first power module is powered on abnormally for the first time, the power-on signal is sent to the first power module again, and whether the first power module is powered on normally is judged;
if the first power supply module is electrified normally, sending an electrifying signal to a second power supply module of the server mainboard, and judging whether the second power supply module is electrified normally;
after the second power supply module is powered on normally, sending a power-on signal to a third power supply module of the server mainboard, and judging whether the third power supply module is powered on normally;
and the rest is done in sequence until all power modules of the server mainboard are powered on normally.
Preferably, when the first power module is powered on abnormally for the first time, the power-on signal is sent to the first power module again, and whether the first power module is powered on normally is judged;
if the first power supply module is abnormal in power-on, judging whether the first power supply module reaches a preset power-on frequency or not;
when the preset power-on times are not reached, sending power-on signals of the preset times to the first power module again, and judging whether the power-on of the first power module is normal or not;
and when the preset power-on times are reached, sending out the fault information of the first power module.
Preferably, when the second power module is powered on abnormally for the first time, the power-on signal is sent to the second power module again, and whether the second power module is powered on normally is judged;
if the second power supply module is abnormal in power-on, judging whether the second power supply module reaches a preset power-on frequency or not;
when the preset power-on times are not reached, sending power-on signals of the preset times to the second power supply module again, and judging whether the power-on of the second power supply module is normal or not;
and when the preset power-on times are reached, sending out the fault information of the second power module.
Preferably, a first power module first power-on normal value of the state machine register is defined as a first preset normal value of the first power module;
defining a second power-on normal value of a first power module of the state machine register as a second preset normal value of the first power module;
defining the Nth power-on normal value of the first power module of the state machine register as the Nth preset normal value of the first power module;
defining a first power module first power-on abnormal value of a state machine register as a first preset abnormal value of a first power module;
defining a second power-on abnormal value of the first power module of the state machine register as a second preset abnormal value of the first power module;
defining an Nth power-on abnormal value of a first power module of a state machine register as an Nth preset abnormal value of the first power module;
after the first power supply module is normally powered on for the first time, the system outputs a first preset normal value of the first power supply module;
after the first power supply module is normally powered on for the second time, the system outputs a second preset normal value of the first power supply module;
after the first power supply module is normally powered on for the Nth time, the system outputs an Nth preset normal value of the first power supply module;
after the first power supply module is powered on abnormally for the first time, the system outputs a first preset abnormal value of the first power supply module;
after the first power supply module is powered on abnormally for the second time, the system outputs a second preset abnormal value of the first power supply module;
after the first power supply module is abnormally powered on for the Nth time, the system outputs the Nth preset abnormal value of the first power supply module.
Preferably, a first power-on normal value of a second power module of the state machine register is defined as a first preset normal value of the second power module;
defining a second power module power-on normal value of the state machine register as a second preset normal value of the second power module;
defining the Nth power-on normal value of a second power module of the state machine register as the Nth preset normal value of the second power module;
defining a first power-on abnormal value of a second power module of the state machine register as a first preset abnormal value of the second power module;
defining a second power module second power-on abnormal value of the state machine register as a second preset abnormal value of the second power module;
defining an Nth power-on abnormal value of a second power module of the state machine register as an Nth preset abnormal value of the second power module;
after the second power supply module is normally powered on for the first time, the system outputs a first preset normal value of the second power supply module;
after the second power supply module is powered on normally for the second time, the system outputs a second preset normal value of the second power supply module;
after the second power supply module is normally powered on for the Nth time, the system outputs an Nth preset normal value of the second power supply module;
after the second power supply module is powered on abnormally for the first time, the system outputs a first preset abnormal value of the second power supply module;
after the second power supply module is powered on abnormally for the second time, the system outputs a second preset abnormal value of the second power supply module;
and after the second power supply module is abnormally powered on for the Nth time, the system outputs the Nth preset abnormal value of the second power supply module.
Preferably, each power module is correspondingly connected with a power status indicator lamp, and the power status indicator lamp is used for indicating the power-on abnormality or normality of the power module.
Preferably, the main board is provided with a plurality of LED lamps and a memory which are arranged according to a preset sequence;
the LED lamps arranged according to the preset sequence are used for displaying the value of the current state machine register through the on and off of the LED lamps;
the memory is used for storing normal values and abnormal values defined by each power supply module and storing the current state information of the power supply module in real time.
According to the technical scheme, the invention has the following advantages:
the method for positioning the abnormal state of the power-on time sequence of the server mainboard tests the power module on the server mainboard according to a preset test sequence, and when the power module fails, a failure prompt can be sent. Based on the electricity takes place unusually about the mainboard, through the bright circumstances of going out of LED lamp just can accurately judge current unusual and normal, need not use the universal meter to measuration one by one power module again, improved mainboard test process's work efficiency, also avoided the repetitive work when testing the mainboard unusually.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a flowchart of a method for locating abnormal power-on timing status of a server motherboard;
fig. 2 is a flowchart of an embodiment of a method for locating abnormal power-on timing status of a server motherboard.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments and drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of protection of this patent.
The present embodiment provides a method for locating abnormal power-on timing status of a server motherboard, as shown in fig. 1, the method includes:
sending a power-on signal to a first power module of a server mainboard, and judging whether the power-on of the first power module is normal or not;
after the first power supply module is normally powered on, sending a power-on signal to a second power supply module of the server mainboard;
judging whether the second power supply module is normally powered on;
after the second power supply module is powered on normally, sending a power-on signal to a third power supply module of the server mainboard, and judging whether the third power supply module is powered on normally;
and after the third power supply module is normally powered on, repeating the steps until all the power supply modules of the server mainboard are normally powered on.
In particular, the method comprises the following steps of,
s1, sending a power-on signal to a first power module of the server mainboard;
S1A, judging whether the first power module is normally powered on;
after the first power supply module is normally powered on;
s2, sending a power-on signal to a second power module of the server mainboard;
when the first power supply module is powered on abnormally for the first time,
S1B, sending the power-on signal to the first power supply module again;
S1C, judging whether the first power module is normally powered on;
after the first power supply module is normally powered on, sending a power-on signal to a second power supply module of the server mainboard;
if the first power supply module is electrified again, the abnormality is caused;
S1D, judging whether the first power module reaches a preset power-on frequency or not;
when the preset power-on times are reached,
and S1E, sending out fault information of the first power supply module.
The specific power-on times can be set according to the test requirements, and are not limited herein. And if the first power supply module is normally powered on within the preset power-on times, sending a power-on signal to a second power supply module of the server mainboard.
S2A, judging whether the second power supply module is normally powered on;
after the second power supply module is normally powered on;
s3, sending a power-on signal to a third power module of the server mainboard;
and S4, after the third power supply module is normally powered on, repeating the steps until all the power supply modules of the server mainboard are normally powered on.
When the second power module is powered on abnormally for the first time,
S2B, sending the power-on signal to the second power supply module again;
S2C, judging whether the second power supply module is normally powered on;
after the second power supply module is powered on normally, a power-on signal is sent to a third power supply module of the server mainboard;
if the second power supply module is electrified again, the abnormality is caused;
S2D, judging whether the second power module reaches the preset power-on times;
when the preset power-on times are reached,
and S2E, sending out fault information of the second power supply module.
The specific power-on times can be set according to the test requirements, and are not limited herein. And if the second power supply module is normally powered on within the preset power-on times, sending a power-on signal to a third power supply module of the server mainboard.
The power-on sequence of each power module of the mainboard is as described above, and whether the power modules are powered on successfully or not is judged one by one. The power-on sequence of the power modules on the main board is set by the needs of the server, and is not limited herein.
In this embodiment, a first power module power-on normal value of the state machine register is defined as a first preset normal value of the first power module;
defining a second power-on normal value of a first power module of the state machine register as a second preset normal value of the first power module; defining the Nth power-on normal value of the first power module of the state machine register as the Nth preset normal value of the first power module; defining a first power module first power-on abnormal value of a state machine register as a first preset abnormal value of a first power module; defining a second power-on abnormal value of the first power module of the state machine register as a second preset abnormal value of the first power module; defining an Nth power-on abnormal value of a first power module of a state machine register as an Nth preset abnormal value of the first power module; after the first power supply module is normally powered on for the first time, the system outputs a first preset normal value of the first power supply module; after the first power supply module is normally powered on for the second time, the system outputs a second preset normal value of the first power supply module; after the first power supply module is normally powered on for the Nth time, the system outputs an Nth preset normal value of the first power supply module; after the first power supply module is powered on abnormally for the first time, the system outputs a first preset abnormal value of the first power supply module; after the first power supply module is powered on abnormally for the second time, the system outputs a second preset abnormal value of the first power supply module; after the first power supply module is abnormally powered on for the Nth time, the system outputs the Nth preset abnormal value of the first power supply module.
Defining a first power-on normal value of a second power module of the state machine register as a first preset normal value of the second power module; defining a second power module power-on normal value of the state machine register as a second preset normal value of the second power module; defining the Nth power-on normal value of a second power module of the state machine register as the Nth preset normal value of the second power module; defining a first power-on abnormal value of a second power module of the state machine register as a first preset abnormal value of the second power module; defining a second power module second power-on abnormal value of the state machine register as a second preset abnormal value of the second power module; defining an Nth power-on abnormal value of a second power module of the state machine register as an Nth preset abnormal value of the second power module; after the second power supply module is normally powered on for the first time, the system outputs a first preset normal value of the second power supply module; after the second power supply module is powered on normally for the second time, the system outputs a second preset normal value of the second power supply module; after the second power supply module is normally powered on for the Nth time, the system outputs an Nth preset normal value of the second power supply module; after the second power supply module is powered on abnormally for the first time, the system outputs a first preset abnormal value of the second power supply module; after the second power supply module is powered on abnormally for the second time, the system outputs a second preset abnormal value of the second power supply module; and after the second power supply module is abnormally powered on for the Nth time, the system outputs the Nth preset abnormal value of the second power supply module.
And by analogy, each power supply module is defined by an Nth power-on normal value and an Nth preset abnormal value which are defined by a state machine register.
Therefore, a tester can more intuitively observe the period of time when the internal logic is down when the power-on is abnormal. The size of the status register value can also be directly displayed through the on-off condition of an on-board LED lamp.
Specifically, each power module is correspondingly connected with a power state indicator lamp, and the power state indicator lamp is used for indicating the power-on abnormity or normality of the power module.
The main board is provided with a plurality of LED lamps and a memory which are arranged according to a preset sequence; the LED lamps arranged according to the preset sequence are used for displaying the value of the current state machine register through the on and off of the LED lamps; the memory is used for storing normal values and abnormal values defined by each power supply module and storing the current state information of the power supply module in real time.
The invention also provides a specific embodiment, which specifically comprises the following steps:
in the design of a server mainboard, a CPLD is often adopted to control the time sequence, and after receiving a powergood signal of a power of a previous stage, the CPLD can give an enable signal of the power of a next stage according to a certain time sequence requirement. Therefore, by means of logic implementation in the CPLD, the power signal with abnormal power-on can be quickly positioned by judging the delay stage of the abnormal power-on process according to whether the power at different stages is effective or not and displaying the delay stage in an LED lamp mode.
The power signal is controlled electrically in a power-on and power-off manner by adopting a state machine in the internal logic design of the CPLD, and referring to a flow chart in FIG. 2, a method for detecting abnormal power is described by taking a P5V power module and a P3V3 power module as examples;
in the logic design inside the CPLD, the control of each power is realized by using a state machine, when the PowerGood at the previous stage of the P5V power module satisfies the condition, the logic inside the CPLD outputs an enable signal (enable) of the P5V power module, the enable signal drives the VR chip of the P5V power module on the circuit board to perform voltage conversion, so as to generate the voltage of the P5V power module, and when the generated voltage of the P5V power module is stable, the VR chip sends out the PowerGood signal of the P5V power module.
If the voltage of the P5V power module is in an unstable stage all the time, the Powergood signal of the P5V power module is not sent out, and at the moment, the CPLD waits for the P5V power module to send out the Powergood signal all the time; after only the powerGood signal of the P5V power module is active, the CPLD internal logic sends an enable signal to the P3V3 power module.
If the power-on of the P5V power module is abnormal, judging whether the power-on of the P5V power module reaches the preset power-on times; when the power module P5V does not reach the preset power-on times, sending the power-on signals of the preset times to the power module P5V again, and judging whether the power module P5V is normally powered on; when the P5V power module reaches the preset power-on times, the fault information of the P5V power module is sent out.
Meanwhile, in order to more intuitively observe the stage of the internal logic of the CPLD during the abnormal power-on, a register needs to be defined in the CPLD to represent the state of the state machine, and the value of the state register is directly displayed through the on-off condition of an onboard LED lamp.
When powergood of the P5V power module is enabled, the value of the status register is defined as 10, and the on-off status of the on-board LED lamp is 1010 (where "1" represents on and "0" represents off); when the powergood signal of the P3V3 power module is active, the value of the status register is defined as 11, and the on/off status of the on-board LED lamp is 1011.
Therefore, when the value of the status register is determined to be 10 according to the on/off status of the LED lamp, it can be quickly determined that the power of the previous stage of the P5V power module is normal, but the P5V power module is not normally valid. At this time, only the signals related to the P5V power module need to be put on to further judge the reason of the abnormal power-on.
In the embodiment, an enable signal and a powergood signal of the mainboard power are respectively connected to the mainboard CPLD, and 4 LED lamps are reserved on the mainboard for displaying the value of the current state register;
in the internal logic design of the CPLD, the power-on and power-off sequential logic of each power of the mainboard is realized by using a state machine, the power-on and power-off sequential logic is designed according to the standard time sequence of the mainboard in sequence, and the enable signal of the next stage can be output only after the powergood signal of the previous stage is effective;
when power-on and power-off are abnormal, the value of the status register is judged according to the value of the LED lamp, so that the current abnormal power is accurately deduced, other signals of the current abnormal power are analyzed, and related bugs are removed in time.
When electricity took place unusually about the mainboard, only need bright the circumstances of going out through board year LED lamp just can accurately judge current unusual power and normal power, need not use the universal meter to measuration by power one by one again, improved the work efficiency of mainboard debug process, also avoided the repetitive work when a large amount of mainboards are unusual.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (1)
1. A method for positioning abnormal state of a power-on time sequence of a server mainboard is characterized by comprising the following steps:
in the design of a server mainboard, a CPLD is adopted to control the time sequence, and after receiving a powergood signal of a power of the previous stage, the CPLD can give an enabling signal of the power of the next stage according to a certain time sequence requirement;
judging the stage of the abnormal power-on process according to whether the powers in different stages are effective or not, and displaying the stage in an LED lamp mode to realize the rapid positioning of the power signal with the abnormal power-on;
the power-on control of the power signal is realized by adopting a state machine mode in the internal logic design of the CPLD, and the method for detecting abnormal power by using the P5V power module and the P3V3 power module comprises the following steps:
in the logic design inside the CPLD, the control of each power is realized by using a state machine, when the powergood at the previous stage of the P5V power module meets the condition, the logic inside the CPLD outputs an enable signal of the P5V power module, the enable signal drives a VR chip of the P5V power module on a circuit board to perform voltage conversion, the voltage of the P5V power module is generated, and when the generated voltage of the P5V power module is stable, the VR chip sends out the powergood signal of the P5V power module;
if the voltage of the P5V power module is in an unstable stage all the time, the Powergood signal of the P5V power module will not be sent out, and at this time, the CPLD will wait for the P5V power module to send out the Powergood signal all the time; after the powergood signal of the P5V power supply module is valid, the CPLD internal logic sends an enabling signal to the P3V3 power supply module;
if the power-on of the P5V power module is abnormal, judging whether the power-on of the P5V power module reaches the preset power-on times; when the power module P5V does not reach the preset power-on times, sending the power-on signals of the preset times to the power module P5V again, and judging whether the power module P5V is normally powered on; when the P5V power module reaches the preset power-on times, sending out fault information of the P5V power module;
defining a register in the CPLD for representing the state of a state machine and directly displaying the value of the register according to the on-off condition of an onboard LED lamp;
after the powergood of the P5V power module is enabled, the value of the register is defined as 10, and the on-off condition of the on-board LED lamp is 1010;
after the powergood signal of the P3V3 power module is valid, the value of the register is defined to be 11, and the on-off condition of the onboard LED lamp is 1011;
when the value of the register is judged to be 10 according to the on-off condition of the LED lamp, the power of the previous stage of the P5V power module is judged to be normal;
respectively connecting an enabling signal and a powergood signal of the mainboard power to the mainboard CPLD, and reserving 4 LED lamps on the mainboard for displaying the value of the current register;
in the internal logic design of the CPLD, the power-on sequential logic of each power of the mainboard is realized by using a state machine, the power-on sequential logic is designed according to the standard time sequence of the mainboard, and the enable signal of the next stage can be output only after the powergood signal is effective;
when power-on abnormality occurs, the value of the register is judged according to the value of the LED lamp, the current abnormal power is obtained, other signals of the current abnormal power are analyzed in a repeated manner, and related bugs are removed in time;
when the mainboard is electrified to be abnormal, the current abnormal power and the normal power are accurately judged according to the on-off condition of the onboard LED lamps.
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