CN103197998B - PMU electrifying timing sequence testing device and method - Google Patents
PMU electrifying timing sequence testing device and method Download PDFInfo
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- CN103197998B CN103197998B CN201310088753.8A CN201310088753A CN103197998B CN 103197998 B CN103197998 B CN 103197998B CN 201310088753 A CN201310088753 A CN 201310088753A CN 103197998 B CN103197998 B CN 103197998B
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Abstract
PMU electrifying timing sequence testing device and method, including PMU to be measured and for the SOC tested, two power supply output pins of described PMU to be measured are connected to two interruption detection feet of described SOC respectively by a level sensitive circuit；SOC judges corresponding sequential by the change in voltage detecting described NPN transistor collector respectively, described SOC receives interruption, then in interrupting call back function, record system time when each road is interrupted, it is stored in record array, array data is compared after being carried out by all interruptions with preset data, it is judged that the correctness of described PMU electrifying timing sequence to be measured.The present invention utilizes the interrupt pin of test board processor to detect the power supply output timing of PMU to be measured, while testing efficiency is greatly improved, also ensure that the accuracy of test.
Description
[technical field]
The present invention relates to the test devices and methods therefor of a kind of computer motherboard, specifically refer to PMU when powering on
Sequence test device and method.
[background technology]
PMU(power management unit), Power Management Unit, is a kind of highly integrated, pin
Power management scheme to portable use, if will Ganlei's Power Management Devices of traditional discrete be incorporated into
Within single encapsulation, so can realize higher power supply conversion efficiency and more low-power consumption, and less group
Number of packages is to adapt to the plate level space reduced.The electrifying timing sequence of PMU CPU to be coordinated (system level chip),
The electric sequence of some voltage and between time interval have precedence relationship and time requirement.
At present, mainly observation oscilloscope is used to detect the power supply (powering on) of PMU chip by test man
Sequential, efficiency is the lowest, and accuracy also difficulty is guaranteed.
In view of this, the present inventor furthers investigate for the defect of prior art, and has this case to produce.
[summary of the invention]
One of the technical problem to be solved is to provide a kind of simple efficient PMU electrifying timing sequence
Test device.
The two of the technical problem to be solved are to provide a kind of simple efficient PMU electrifying timing sequence
Method of testing.
The present invention solves one of above-mentioned technical problem by the following technical programs:
PMU electrifying timing sequence testing device, including PMU to be measured and for the SOC tested, described in treat
Two the power supply output pins surveying PMU are connected to the two of described SOC respectively by a level sensitive circuit
Individual interruption detects foot；
Described level sensitive circuit includes one first resistance, one second resistance, one the 3rd resistance, a NPN
Audion；Each power supply output pin of described PMU to be measured connects described first resistance, described first electricity
The resistance other end divides two-way, and a road is connected to the base stage of described NPN audion, and another road connects described second
Resistance, described second resistance other end ground connection；The grounded emitter of described NPN audion, described NPN
The colelctor electrode of audion divides two-way, and a road is connected to the interruption detection foot of described SOC, and another road is connected to
Described 3rd resistance, the described 3rd resistance other end is connected to power supply；
Described SOC, is judged by the change in voltage detecting described NPN transistor collector respectively accordingly
Sequential, described SOC receives interruption, then records in call back function when each road is interrupted interrupting
System time, is stored in record array, all interruptions be carried out after by array data and preset data ratio
Relatively, it is judged that the correctness of described PMU electrifying timing sequence to be measured.
The present invention solves the two of above-mentioned technical problem by the following technical programs:
Use the electrifying timing sequence method of testing of above-mentioned PMU electrifying timing sequence testing device, comprise the steps:
Step 1: the GPIO of SOC is set to fracture in trailing edge, interrupt counter count clear 0, time
Between record array timeDate [] clear 0；
Step 2: power on to PMU to be measured；
Step 3: time delay 1 microsecond, time++；
Step 4: judge Count >=to be measured need to survey power supply number n？It is to proceed to step 5, no, proceed to
Step 6；
Step 5: compare timeDate [] whether in set point, be then to proceed to step 7, no, then
Proceed to step 8；
Step 6: judge time > timeouts value？It is to proceed to step 8, no, forward step 3 to；
Step 7:PMU electrifying timing sequence is qualified, and ret=SUCCESS proceeds to step 9；
Step 8:PMU electrifying timing sequence is defective, and ret=ERROR proceeds to step 9；
Step 9: terminate test.
It is an advantage of the current invention that: utilize the interrupt pin of test board processor to detect the electricity of PMU to be measured
Source output timing, while testing efficiency is greatly improved, also ensure that the accuracy of test.
[accompanying drawing explanation]
The invention will be further described the most in conjunction with the embodiments.
Fig. 1 is the hardware architecture diagram that the present invention tests device.
Fig. 2 is method of testing schematic flow sheet of the present invention.
[detailed description of the invention]
As it is shown in figure 1, PMU electrifying timing sequence testing device, including PMU to be measured and for testing
Two power supply output pins of SOC, PMU are detected by the first level sensitive circuit, second electrical level respectively
Circuit is connected to two interruption detection feet of SOC.
First level sensitive circuit includes resistance R1, R2, R3, NPN audion Q1；Its of PMU
In power supply output pin connect resistance R1, the resistance R1 other end divides two-way, and a road is connected to NPN
The base stage of audion Q1, another road connects resistance R3, resistance R3 other end ground connection；NPN audion
The grounded emitter of Q1, the colelctor electrode of NPN audion Q1 divides two-way, and a road is connected in SOC
Disconnected detection foot, another road is connected to resistance R2, and the resistance R2 other end is connected to power supply.
Second electrical level testing circuit includes resistance R4, R5, R6, NPN audion Q2；Its of PMU
In power supply output pin connect resistance R4, the resistance R4 other end divides two-way, and a road is connected to NPN
The base stage of audion Q2, another road connects resistance R6, resistance R6 other end ground connection；NPN audion
The grounded emitter of Q2, the colelctor electrode of NPN audion Q2 divides two-way, and a road is connected in SOC
Disconnected detection foot, another road is connected to resistance R5, and the resistance R5 other end is connected to power supply.
When SOC judges corresponding by the change in voltage detecting described NPN transistor collector respectively
Sequence, described SOC receives interruption, then records system when each road is interrupted in interrupting call back function
Time, being stored in record array, array data is compared after being carried out by all interruptions with preset data,
Judge the correctness of described PMU electrifying timing sequence to be measured.
Concrete PMU electrifying timing sequence method of testing is as in figure 2 it is shown, comprise the steps:
Step 1: the GPIO of SOC is set to fracture in trailing edge, interrupt counter count clear 0, time
Between record array timeDate [] clear 0；
Step 2: power on to PMU to be measured；
Step 3: time delay 1 microsecond, time++；
Step 4: judge Count >=to be measured need to survey power supply number n？It is to proceed to step 5, no, proceed to
Step 6；
Step 5: compare timeDate [] whether in set point, be then to proceed to step 7, no, then
Proceed to step 8；
Step 6: judge time > timeouts value？It is to proceed to step 8, no, forward step 3 to；
Step 7:PMU electrifying timing sequence is qualified, and ret=SUCCESS proceeds to step 9；
Step 8:PMU electrifying timing sequence is defective, and ret=ERROR proceeds to step 9；
Step 9: terminate test.
The present invention utilize the interrupt pin of test board processor to detect the power supply output timing of PMU to be measured,
While testing efficiency is greatly improved, also ensure that the accuracy of test.
The foregoing is only the present invention preferably implements use-case, is not intended to limit the protection of the present invention
Scope.All within the spirit and principles in the present invention, any amendment, equivalent and the improvement made
Deng, should be included within the scope of the present invention.
Claims (1)
1.PMU electrifying timing sequence testing device, it is characterised in that: include PMU to be measured and for surveying
Two power supply output pins of the SOC, PMU of examination are respectively by the first level sensitive circuit, second electrical level
Testing circuit is connected to two interruption detection feet of SOC；
Described first level sensitive circuit includes resistance R1, R2, R3, NPN audion Q1；PMU
One of them power supply output pin connect resistance R1, the resistance R1 other end divides two-way, and a road is connected to
The base stage of NPN audion Q1, another road connects resistance R3, resistance R3 other end ground connection；NPN tri-
The grounded emitter of pole pipe Q1, the colelctor electrode of NPN audion Q1 divides two-way, and a road is connected to SOC
Interruption detection foot, another road is connected to resistance R2, and the resistance R2 other end is connected to power supply；
Described second electrical level testing circuit includes resistance R4, R5, R6, NPN audion Q2；PMU
One of them power supply output pin connect resistance R4, the resistance R4 other end divides two-way, and a road is connected to
The base stage of NPN audion Q2, another road connects resistance R6, resistance R6 other end ground connection；NPN tri-
The grounded emitter of pole pipe Q2, the colelctor electrode of NPN audion Q2 divides two-way, and a road is connected to SOC
Interruption detection foot, another road is connected to resistance R5, and the resistance R5 other end is connected to power supply；
Described SOC, is judged by the change in voltage detecting described NPN transistor collector respectively accordingly
Sequential, described SOC receives interruption, then records in call back function when each road is interrupted interrupting
System time, is stored in record array, all interruptions be carried out after by array data and preset data ratio
Relatively, it is judged that the correctness of described PMU electrifying timing sequence to be measured.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310088753.8A CN103197998B (en) | 2013-03-19 | 2013-03-19 | PMU electrifying timing sequence testing device and method |
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| CN201310088753.8A CN103197998B (en) | 2013-03-19 | 2013-03-19 | PMU electrifying timing sequence testing device and method |
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| CN103197998A CN103197998A (en) | 2013-07-10 |
| CN103197998B true CN103197998B (en) | 2016-09-14 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375915A (en) * | 2014-12-16 | 2015-02-25 | 浪潮电子信息产业股份有限公司 | Method for interactively and quickly diagnosing mainboard time sequence by utilizing BMC (baseboard management controller) and CPLD (complex programmable logic device) |
| CN106647928A (en) * | 2016-12-30 | 2017-05-10 | 杭州宏杉科技股份有限公司 | Abnormal time sequence locating method and apparatus, and mainboard |
| WO2019056192A1 (en) | 2017-09-19 | 2019-03-28 | 深圳市汇顶科技股份有限公司 | Method and system for measuring power-on reset time |
| CN107703462B (en) * | 2017-10-18 | 2020-11-24 | 苏州浪潮智能科技有限公司 | Controller |
| CN107797050B (en) * | 2017-10-20 | 2021-07-02 | 郑州云海信息技术有限公司 | Method for positioning abnormal power-on time sequence state of server mainboard |
| CN109828167A (en) * | 2018-12-28 | 2019-05-31 | 曙光信息产业(北京)有限公司 | A kind of method and apparatus positioning Intel Platform Server electrifying timing sequence exception |
Citations (3)
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|---|---|---|---|---|
| US5903767A (en) * | 1988-12-09 | 1999-05-11 | Dallas Semiconductor Corporation | Integrated circuit for providing supervisory functions to a microprocessor |
| CN1971528A (en) * | 2005-11-25 | 2007-05-30 | 鸿富锦精密工业（深圳）有限公司 | Automated computer on-off operation testing device and method |
| CN204009457U (en) * | 2014-08-06 | 2014-12-10 | 青岛歌尔声学科技有限公司 | On/off circuit based on PMU and electronic equipment |
-
2013
- 2013-03-19 CN CN201310088753.8A patent/CN103197998B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903767A (en) * | 1988-12-09 | 1999-05-11 | Dallas Semiconductor Corporation | Integrated circuit for providing supervisory functions to a microprocessor |
| CN1971528A (en) * | 2005-11-25 | 2007-05-30 | 鸿富锦精密工业（深圳）有限公司 | Automated computer on-off operation testing device and method |
| CN204009457U (en) * | 2014-08-06 | 2014-12-10 | 青岛歌尔声学科技有限公司 | On/off circuit based on PMU and electronic equipment |
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| CN103197998A (en) | 2013-07-10 |
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Address after: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Applicant after: FUZHOU ROCKCHIP ELECTRONICS CO., LTD. Address before: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Applicant before: Fuzhou Rockchip Semiconductor Co., Ltd. |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |
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