CN104750583A - Mainboard power-on sequence diagnostic circuit - Google Patents
Mainboard power-on sequence diagnostic circuit Download PDFInfo
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- CN104750583A CN104750583A CN201310742824.1A CN201310742824A CN104750583A CN 104750583 A CN104750583 A CN 104750583A CN 201310742824 A CN201310742824 A CN 201310742824A CN 104750583 A CN104750583 A CN 104750583A
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- mainboard
- pin
- diagnostic circuit
- timing sequence
- electrical voltage
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Abstract
A mainboard power-on sequence diagnostic circuit comprises a mainboard, a control chip connected to the mainboard and a plurality of indicating lamps connected to the control chip. The mainboard comprises a plurality of voltage points arranged according to a decimal number, the control chip comprises a plurality of first pins connected to the voltage pins respectively, the first pins are used for receiving decimal signal data of the voltage points, the control chip is capable of converting the decimal signal data received by the first pins into binary signal data and sending the binary signal data to the indicating lamps, and the indicating lamps are capable of displaying the voltage points not generated on the mainboard according to the received binary signal data.
Description
Technical field
The present invention relates to a kind of mainboard electrifying timing sequence diagnostic circuit.
Background technology
Power electric pressure point on computer motherboard has tens more than and each electrical voltage point has the precedence relationship of respective electrifying timing sequence, the electrifying timing sequence of this complexity often makes when mainboard occurs not starting shooting (electrifying timing sequence does not all complete), and it is which or which electrical voltage point does not produce and the reason that causes that tester is difficult to find out.A kind of software debug method is used at present: the debug information of outwards being lost electrifying timing sequence by the com port of computing machine on EC.This Measures compare can find the electrical voltage point specifically gone wrong rapidly, but all will revise EC program when shortcoming is to lose Debug information at every turn, and also needs the other computing machine of erection to lose for receiving EC the debug information from com port, cumbersome.
Summary of the invention
In view of above content, be necessary to provide a kind of mainboard electrifying timing sequence diagnostic circuit conveniently can finding out the electrical voltage point do not produced.
A kind of mainboard electrifying timing sequence diagnostic circuit, include a mainboard, control chip on the described mainboard of one connection and multiple pilot lamp being connected to described control chip, described mainboard includes multiple electrical voltage point, described multiple electrical voltage point arranges according to decimal number, described control chip includes multiple the first pin being connected to each electrical voltage point, described first pin is in order to receive the decadic signaling data of described multiple electrical voltage point, the decadic signaling data that first pin receives can be converted to binary signal data and be sent to described multiple pilot lamp by described control chip, described multiple pilot lamp can demonstrate the electrical voltage point do not produced on mainboard according to the described binary signal data received.
Further, described mainboard also includes a first node, and each electrical voltage point is connected to described first pin by a first node.
Further, each electrical voltage point is connected to described first node by one first resistance, and described first node is by one second resistance eutral grounding.
Further, described mainboard also includes an electric capacity, and one end of described electric capacity is connected to described first node, other end ground connection.
Further, described control chip also includes multiple second pin, and each second pin is connected to each pilot lamp, and the binary signal data after described control chip conversion transfer to each pilot lamp described by described second pin.
Further, described mainboard electrifying timing sequence diagnostic circuit also includes a power supply, and each pilot lamp described is connected to described power supply by one the 3rd resistance.
Further, described first pin is a pin ADC0/GP1O (3_X).
Further, described first pin is an analog to digital conversion pin.
Further, described second pin is a pin PWMO/GPAO (UP).
Compared with prior art, multiple electrical voltage points on mainboard in above-mentioned mainboard electrifying timing sequence diagnostic circuit are connected on the first pin of described control chip, first pin can receive the decadic signaling data of described multiple electrical voltage point, after decadic signaling data are converted to binary signal data by described control chip, described multiple pilot lamp just can demonstrate the electrical voltage point do not produced on mainboard according to the described binary signal data received.Like this, just can find out by pilot lamp the position that described electrical voltage point do not produce exactly, very convenient.
Accompanying drawing explanation
Fig. 1 is a circuit diagram of a better embodiment of mainboard electrifying timing sequence diagnostic circuit of the present invention.
Fig. 2 is another circuit diagram of mainboard electrifying timing sequence diagnostic circuit of the present invention.
Main element symbol description
| Mainboard | 10 |
| First electrical voltage point | 11 |
| Second electrical voltage point | 12 |
| Control chip | 20 |
| First pin | 21 |
| Second pin | 22 |
| 3rd pin | 23 |
| Pilot lamp | 30 |
| Power supply | 40 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1 and Fig. 2, in a better embodiment of the present invention, a mainboard electrifying timing sequence diagnostic circuit comprises a mainboard 10, and connects the control chip 20 of described mainboard 10 and the pilot lamp 30 of the described control chip 20 of some connections.In one embodiment, described control chip 20 is an embedded controller, includes multiple pin for connecting.
Described mainboard 10 includes multiple electrical voltage point, in figure, only shows two, comprise one first electrical voltage point 11 and one second electrical voltage point 12.Described first electrical voltage point 11 is connected with one first resistance R1, and is connected to one first pin 21 of described control chip 20 by a first node 13.Described first node 13 is by one second resistance R2 ground connection.Described second electrical voltage point 12 is connected with one the 3rd resistance R3, and is connected to one second pin 22 of described control chip 20 by a Section Point 14.Described Section Point 14 is connected with an electric capacity C1.One end of described electric capacity C1 connects described first node 13, other end ground connection.In one embodiment, described first pin 21 is a pin ADC0/GP1O (3_X); Described second pin 22 is a pin ADC1/GP1O (3_X).In addition, described first pin 21 or the second pin 22 also can be an analog to digital conversion pin.As the first electrical voltage point 11 is the same with the second electrical voltage point 12, each electrical voltage point on described mainboard 10 can be connected on each pin of described control chip 20 according to described first electrical voltage point 11 and the second electrical voltage point 12.
Each pilot lamp 30 is connected on one the 3rd pin 23 of described control chip 20 and (only shows 5 pilot lamp 30 in figure).Refer to Fig. 2, one end of each pilot lamp 30 is connected to described 3rd pin 23, and the other end is connected to a power supply 40 by one the 4th resistance R4.Total at an embodiment He, each the 3rd pin 23 is a pin PWMO/GPAO (UP).
Several pilot lamp 30 described can adopt binary light on and off method to indicate and not produce the name placement of electrical voltage point in electrifying timing sequence.As, there are 5 pilot lamp 30 in figure, 32 electrical voltage points on mainboard 10 can be represented, i.e. 5 powers of 2.Such as, 32 electrical voltage points on described mainboard 10 are expressed as 1 with decimal number respectively, 2,3,4 ... 31,32, and control chip 20 as described in by the pin of class as the first pin 21, second pin 22 decadic signaling data being transferred to, described decadic signaling data are converted to binary signal data by described control chip 20 again, and by class as described in the pin of the 3rd pin 23 transfer to as described in pilot lamp 30, thus to be shown by described 5 pilot lamp 30.Four pilot lamp 30 go out before in described 5 pilot lamp 30, when the 5th pilot lamp is bright, are (00001) with binary representation, then the 1st electrical voltage point be expressed as on mainboard 10 does not produce.Three pilot lamp 30 go out before in described 5 pilot lamp 30, and the 4th pilot lamp 30 is bright, when the 5th pilot lamp 30 goes out, is (00010) with binary representation, then the 2nd electrical voltage point be expressed as on mainboard 10 does not produce.When first and third, five pilot lamp 30 in described 5 pilot lamp 30 go out, when second, four pilot lamp 30 are bright, be (01010) with binary representation, then the 10th electrical voltage point be expressed as on mainboard 10 does not produce.When first and third pilot lamp 30 in described 5 pilot lamp 30 goes out, when second, four, five pilot lamp 30 are bright, be (01011) with binary representation, then the 11st electrical voltage point be expressed as on mainboard 10 does not produce.When all pilot lamp 30 in described 5 pilot lamp 30 all do not work, then represent that all electrical voltage points on described mainboard 10 all create, then represent that electrifying timing sequence completes.
So, according to the method described above, can prepare and find out rapidly by the display packing of described pilot lamp 30 particular location that electrical voltage point do not produce.In addition, the number of described pilot lamp 30 can also be increased and decreased according to the number of the electrical voltage point on described mainboard 10.
Claims (9)
1. a mainboard electrifying timing sequence diagnostic circuit, include the control chip on a mainboard and the described mainboard of a connection, described mainboard includes multiple electrical voltage point, described multiple electrical voltage point arranges according to decimal number, it is characterized in that: described mainboard electrifying timing sequence diagnostic circuit also includes multiple pilot lamp being connected to described control chip, described control chip includes multiple the first pin being connected to each electrical voltage point, described first pin is in order to receive the decadic signaling data of described multiple electrical voltage point, the decadic signaling data that first pin receives can be converted to binary signal data and be sent to described multiple pilot lamp by described control chip, described multiple pilot lamp can demonstrate the electrical voltage point do not produced on mainboard according to the described binary signal data received.
2. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 1, it is characterized in that: described mainboard also includes a first node, each electrical voltage point is connected to described first pin by a first node.
3. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 2, is characterized in that: each electrical voltage point is connected to described first node by one first resistance, and described first node is by one second resistance eutral grounding.
4. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 2, it is characterized in that: described mainboard also includes an electric capacity, one end of described electric capacity is connected to described first node, other end ground connection.
5. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 1, it is characterized in that: described control chip also includes multiple second pin, each second pin is connected to each pilot lamp, and the binary signal data after described control chip conversion transfer to each pilot lamp described by described second pin.
6. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 1, it is characterized in that: described mainboard electrifying timing sequence diagnostic circuit also includes a power supply, each pilot lamp described is connected to described power supply by one the 3rd resistance.
7. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 1, is characterized in that: described first pin is a pin ADC0/GP1O (3_X).
8. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 1, is characterized in that: described first pin is an analog to digital conversion pin.
9. mainboard electrifying timing sequence diagnostic circuit as claimed in claim 5, is characterized in that: described second pin is a pin PWMO/GPAO (UP).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310742824.1A CN104750583A (en) | 2013-12-30 | 2013-12-30 | Mainboard power-on sequence diagnostic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310742824.1A CN104750583A (en) | 2013-12-30 | 2013-12-30 | Mainboard power-on sequence diagnostic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104750583A true CN104750583A (en) | 2015-07-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310742824.1A Pending CN104750583A (en) | 2013-12-30 | 2013-12-30 | Mainboard power-on sequence diagnostic circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104750583A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107797050A (en) * | 2017-10-20 | 2018-03-13 | 郑州云海信息技术有限公司 | A kind of method of location-server mainboard electrifying timing sequence abnormal state |
| CN108874388A (en) * | 2018-06-08 | 2018-11-23 | 山东超越数控电子股份有限公司 | A set of code supports multiple mainboards to realize the encryption method of resource-sharing |
| CN108920317A (en) * | 2018-07-06 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of method and apparatus of diagnostic module external-connection displayer part and the multiplexing of PORT80 display device |
-
2013
- 2013-12-30 CN CN201310742824.1A patent/CN104750583A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107797050A (en) * | 2017-10-20 | 2018-03-13 | 郑州云海信息技术有限公司 | A kind of method of location-server mainboard electrifying timing sequence abnormal state |
| CN108874388A (en) * | 2018-06-08 | 2018-11-23 | 山东超越数控电子股份有限公司 | A set of code supports multiple mainboards to realize the encryption method of resource-sharing |
| CN108920317A (en) * | 2018-07-06 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of method and apparatus of diagnostic module external-connection displayer part and the multiplexing of PORT80 display device |
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| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
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Application publication date: 20150701 |