CN108984368A - A kind of method and device based on CPLD quick lock in server master board problem power supply - Google Patents
A kind of method and device based on CPLD quick lock in server master board problem power supply Download PDFInfo
- Publication number
- CN108984368A CN108984368A CN201810751358.6A CN201810751358A CN108984368A CN 108984368 A CN108984368 A CN 108984368A CN 201810751358 A CN201810751358 A CN 201810751358A CN 108984368 A CN108984368 A CN 108984368A
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- China
- Prior art keywords
- cpld
- power supply
- master board
- server master
- display device
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3031—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a motherboard or an expansion card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
Abstract
The embodiment of the invention discloses a kind of methods based on CPLD quick lock in server master board problem power supply, this method comprises: server master board is accessed CPLD in relation to the signal of electrifying timing sequence；CPLD shows the state course of timing operating status machine by exterior display device；Judge whether to detect abnormality；If it is not, then continuing to test；Otherwise, operation is performed the next step；State machine keeps the abnormality constant；According to exterior display device orientation problem power supply.It further include a kind of device based on CPLD quick lock in server master board problem power supply.Where need to only checking that exterior display device state can find power issue, convenient for the debugging of server master board.This method can quick and precisely find server master board power issue, improve diagnosis debugging efficiency.Lead to the risk of server power supply short circuit when also reduction multimeter point is surveyed.
Description
Technical field
The present invention relates to the technical fields for searching server problem power supply, specifically a kind of to be based on CPLD quick lock in
The method and device of server master board problem power supply.
Background technique
With the continuous development of server technology, from the multicore multi -CPU of the monokaryon list CPU of early stage till now, service
The performance of device has obtained great promotion, at the same time, since system becomes increasingly complex, also brings to the Debugging of system
Challenge.
Early stage, server is mostly one or two CPU, and the power supply on mainboard is less, when plank has powered on it is abnormal when,
We can go measurement out of joint to find out specifically which electricity one by one with multimeter.
But present server becomes increasingly complex, and measures the waste plenty of time one by one in this way, is more difficult when mainboard is in cabinet
Measurement can also survey a little improper caused short-circuit risks, largely effect on the progress of diagnosis debugging.
Summary of the invention
A kind of method based on CPLD quick lock in server master board problem power supply is provided in the embodiment of the present invention, with solution
Certainly current server master board diagnosis debugging efficiency is low, if fruit dot surveys improper, the problem of will lead to short-circuit risks.
In order to solve the above-mentioned technical problem, the embodiment of the invention discloses following technical solutions:
First aspect present invention provides a kind of method based on CPLD quick lock in server master board problem power supply, the party
Method includes:
Server master board is accessed into CPLD in relation to the signal of electrifying timing sequence；
CPLD shows the state course of timing operating status machine by exterior display device；
Judge whether to detect abnormality；If it is not, then continuing to test；Otherwise, operation is performed the next step；
State machine keeps the abnormality constant；
According to exterior display device orientation problem power supply.
With reference to first aspect, in a first possible implementation of that first aspect, the premise of the above method includes: described
CPLD also with a ROM communicate to connect.
With reference to first aspect, in a second possible implementation of that first aspect, be stored in the ROM including
The software code information of CPLD operation, predefined state machine information；With each VR's grabbed when server master board powers on
Power Good signal and platform reset signal.
With reference to first aspect, in first aspect in the third possible implementation, the timing operating status machine is
The presetting electrifying timing sequence state of the software code information of CPLD operation.
With reference to first aspect, in the 4th kind of possible implementation of first aspect, the state machine information includes power supply
Signal and display information；The electric potential signal and display information corresponds.
With reference to first aspect, in the 5th kind of possible implementation of first aspect, judge whether to detect abnormality
Standard be:
Whether real-time state and preset electrifying timing sequence state are consistent, if it is inconsistent, indicating abnormality.
With reference to first aspect, described fixed according to exterior display device in the 6th kind of possible implementation of first aspect
Position problem power supply is exterior display device display problem power supply, is specifically included:
Display information corresponding to exterior display device display problem power supply.
Second aspect of the present invention provides a kind of device based on CPLD quick lock in server master board problem power supply, the dress
It sets including CPLD；With,
Exterior display device, the position of power supply the problem of for display server mainboard；The CPLD and external display fill
It sets connected.
In conjunction with second aspect, in second aspect in the first possible implementation, device further includes memory module, is used for
Store software code information, the predefined state machine information that CPLD is run；With each VR's grabbed when server master board powers on
Power Good signal and platform reset signal.
By above technical scheme as it can be seen that the present invention does not have to take out mainboard, only it need to check that exterior display device state can look for
Where to power issue, convenient for the debugging of server master board.This method can quick and precisely find server master board power issue,
Improve diagnosis debugging efficiency.Lead to the risk of server power supply short circuit when also reduction multimeter point is surveyed.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without creative efforts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of method flow schematic diagram based on CPLD quick lock in server master board problem power supply.
Fig. 2 is a kind of dress based on CPLD quick lock in server master board problem power supply applied by the embodiment of the present invention one
Set structural schematic diagram；
Fig. 3 is a kind of dress based on CPLD quick lock in server master board problem power supply applied by the embodiment of the present invention two
Set structural schematic diagram.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
As shown in Figure 1, a kind of method based on CPLD quick lock in server master board problem power supply, this method comprises:
S1, server master board power on；
S2, CPLD (Complex Programmable Logic Device, Complex Programmable Logic Devices) crawl service
The Power Good signal and platform reset signal for each VR that device mainboard grabs when powering on are saved to memory；
S3, server master board is accessed into CPLD in relation to the signal of electrifying timing sequence；
S4, CPLD show the state course of timing operating status machine by exterior display device；
S5, judge whether to detect abnormality；If it is not, then continuing to test；Otherwise, operation is performed the next step；
S6, state machine keep the abnormality constant；
S7, according to exterior display device orientation problem power supply.
Be stored in memory including CPLD operation software code information, predefined state machine information；With service
The Power Good signal and platform for each VR (Voltage Regulator, voltage adjuster) that device mainboard grabs when powering on
Reset signal.
Timing operating status machine is the presetting electrifying timing sequence state of the software code information of CPLD operation, such as: if it is
5V is first gone up, then 3.3V, then 2V, here it is electrifying timing sequences.
When the electricity of 5V gets up, the electricity of 3.3V does not get up, and can be defined as state 1；When 5V and 3.3V get up, 2V is not risen
Come, state 2 can be defined as；When three electricity all get up to be defined as state 3.
After CPLD receives the power good signal of 3.3V, the enable signal of 2V is issued, then the electricity of 2V rises
Come, just gone to state 3 from state 2, this just cries the operation for wanting state machine, that is, reaches some condition, goes to another definition
State.
State machine information includes power supply signal and display information；The electric potential signal and display information corresponds.Electricity
Position signal can be as shown in the table with display information corresponding relationship,
Judge whether to detect that the standard of abnormality is in S5 operation:
Whether real-time state and preset electrifying timing sequence state are consistent, if it is inconsistent, indicating abnormality.
It according to exterior display device orientation problem power supply is exterior display device display problem power supply in S7 operation, it is specific to wrap
It includes:
Display information corresponding to exterior display device display problem power supply.
A kind of device based on CPLD quick lock in server master board problem power supply, which includes CPLD；With outside is aobvious
Showing device, the position of power supply the problem of for display server mainboard；The CPLD is connected with exterior display device.Device also wraps
Memory module is included, for storing software code information, the predefined state machine information that CPLD is run；With on server master board
The Power Good signal and platform reset signal of each VR grabbed when electric.
As shown in Fig. 2, exterior display device is 8 LED, 8 LED are arranged in order from 0 to 7, can pass through 8421 yards
Mode go to read.Lamp is bright to indicate 1, and lamp goes out expression 0, for example, the state of 8 lamps be successively go out go out it is bright, as
00000011,8421 yard of reading is 03, this electricity of corresponding P5V illustrates that this electricity is problematic, can emphasis check the VR of P5V
Chip.
As shown in figure 3, exterior display device may be display charactron, more intuitive and convenient is shown in this way, is not required to again
It goes to read by way of 8421 yards, the effect of generation is easily facilitated and checked as with 8 LED reading being also.For example, number
Code pipe is shown as 08, problematic by PVCCIO_PG known to table, can emphasis check this VR of PVCCIO.
The above is only a specific embodiment of the invention, is made skilled artisans appreciate that or realizing this hair
It is bright.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (9)
1. a kind of method based on CPLD quick lock in server master board problem power supply, characterized in that this method comprises:
Server master board is accessed into CPLD in relation to the signal of electrifying timing sequence；
CPLD shows the state course of timing operating status machine by exterior display device；
Judge whether to detect abnormality；If it is not, then continuing to test；Otherwise, operation is performed the next step；
State machine keeps the abnormality constant；
According to exterior display device orientation problem power supply.
2. according to the method described in claim 1, it is characterized in that, the premise of the above method includes: that the CPLD is also deposited with one
Reservoir communication connection.
3. according to the method described in claim 2, it is characterized in that, be stored in the memory including CPLD operation software
Code information, predefined state machine information；With the Power Good signal peace of each VR grabbed when server master board powers on
Platform reset signal.
4. according to the method described in claim 3, it is characterized in that, the timing operating status machine be CPLD operation software code
The presetting electrifying timing sequence state of information.
5. according to the method described in claim 3, it is characterized in that, the state machine information include power supply signal and display information；
The electric potential signal and display information corresponds.
6. according to the method described in claim 1, it is characterized in that, judge whether to detect that the standard of abnormality is:
Whether real-time state and preset electrifying timing sequence state are consistent, if it is inconsistent, indicating abnormality.
7. according to the method described in claim 1, it is characterized in that, it is described according to exterior display device orientation problem power supply be outside
Display device display problem power supply, specifically includes:
Display information corresponding to exterior display device display problem power supply.
8. a kind of device based on CPLD quick lock in server master board problem power supply, -7 any one institute according to claim 1
The method stated, characterized in that including CPLD；With,
Exterior display device, the position of power supply the problem of for display server mainboard；The CPLD and exterior display device phase
Even.
9. device according to claim 8, characterized in that device further includes memory module, for storing CPLD operation
Software code information, predefined state machine information；With the Power Good signal of each VR grabbed when server master board powers on
With platform reset signal.
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| CN201810751358.6A CN108984368A (en) | 2018-07-10 | 2018-07-10 | A kind of method and device based on CPLD quick lock in server master board problem power supply |
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| CN201810751358.6A CN108984368A (en) | 2018-07-10 | 2018-07-10 | A kind of method and device based on CPLD quick lock in server master board problem power supply |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109918138A (en) * | 2019-03-06 | 2019-06-21 | 苏州浪潮智能科技有限公司 | A kind of server sequential control method and device |
| US11579673B2 (en) * | 2021-04-28 | 2023-02-14 | Quanta Compter Inc. | Systems and methods for storing FSM state data for a power control system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708686A (en) * | 2017-03-07 | 2017-05-24 | 济南浪潮高新科技投资发展有限公司 | Mainboard power supply debugging and maintenance method for multichannel server |
| CN107797050A (en) * | 2017-10-20 | 2018-03-13 | 郑州云海信息技术有限公司 | A kind of method of location-server mainboard electrifying timing sequence abnormal state |
-
2018
- 2018-07-10 CN CN201810751358.6A patent/CN108984368A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106708686A (en) * | 2017-03-07 | 2017-05-24 | 济南浪潮高新科技投资发展有限公司 | Mainboard power supply debugging and maintenance method for multichannel server |
| CN107797050A (en) * | 2017-10-20 | 2018-03-13 | 郑州云海信息技术有限公司 | A kind of method of location-server mainboard electrifying timing sequence abnormal state |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109918138A (en) * | 2019-03-06 | 2019-06-21 | 苏州浪潮智能科技有限公司 | A kind of server sequential control method and device |
| US11579673B2 (en) * | 2021-04-28 | 2023-02-14 | Quanta Compter Inc. | Systems and methods for storing FSM state data for a power control system |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181211 |
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| RJ01 | Rejection of invention patent application after publication |