CN108318831A - A method of passing through Debug card debugging server power supply - Google Patents
A method of passing through Debug card debugging server power supply Download PDFInfo
- Publication number
- CN108318831A CN108318831A CN201810050878.4A CN201810050878A CN108318831A CN 108318831 A CN108318831 A CN 108318831A CN 201810050878 A CN201810050878 A CN 201810050878A CN 108318831 A CN108318831 A CN 108318831A
- Authority
- CN
- China
- Prior art keywords
- power supply
- debug card
- mainboard
- cpld
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
Abstract
A kind of method by Debug card debugging server power supply of the present application, this method connect a Debug card on the mainboard of server, and the CPLD on mainboard receives each signal of interest in electric sequential；The information that FPGA in Debug card is obtained by the status information in I2C signal acquisitions CPLD and decoding, compiling, the power state information of mainboard is shown finally by display device external FPGA；FPGA could alternatively be band I2C interface and decode compiler.By the Debug test charts can quickly and easily orientation problem power supply position, substantially increase debugging efficiency.
Description
Technical field
The present invention relates to server power supply testing fields, and in particular to a kind of by Debug card debugging server power supply
Method.
Background technology
The server of early stage is mostly one or two CPU (Central Processing Unit, central processings
Device), the function that can be done is less, therefore the power supply on server master board is also fewer, when power supply occurs on server master board
Which when abnormal, can go to measure one by one using multimeter to there is a problem to find out specifically supply terminals.But with service
The hardware of device is more and more, and performance is higher and higher, and the structure of server also becomes increasingly complex, for example, server four road mainboards just
The problem of having tens supply terminals, and the closeness of server master board is also higher and higher, causing in this way is, as server master
When the power supply of plate occurs abnormal, taken a long time if going to measure supply terminals needs one by one again, if mainboard is in cabinet
Then measure it is more difficult, can also exist point survey it is improper caused by short-circuit risks, this leverage server test and debugging
Efficiency.
In view of the above-mentioned problems, quick and precisely for the debugging of server master board power supply, the present application one kind passing through Debug
The method of card debugging server power supply connects a server power supply debugging Debug card on the mainboard of server, passes through the tune
Examination card can quickly and easily orientation problem power supply position, substantially increase debugging efficiency.
Invention content
The present invention provides a kind of method by Debug card debugging server power supply, and this method is on the mainboard of server
One server power supply of connection debugs Debug card.Specific working mode is：CPLD (Complex on mainboard
Programmable Logic Device, Complex Programmable Logic Devices) receive each signal of interest in mainboard electrifying timing sequence；
Debug card is connected to the Debug header on mainboard by cable, then by CPLD on I2C signal acquisition mainboards about
The status information of these signals；Later, the information that FPGA decodings, the compiling in Debug card obtain；It is external finally by FPGA
Display device shows the power state information of mainboard.
Specifically, a kind of method by Debug card debugging server power supply is claimed in the application, which is characterized in that
This method specifically includes：
CPLD on server master board obtains signal in mainboard electrifying timing sequence, and the state of these signals is stored in posting for CPLD
In storage；
It is arranged on the CPLD on the header1 on one group of I2C signal to mainboard；
Header2, FPGA, charactron are set in Debug card；
The Header2 is connect with the Debug header1 on mainboard；
The FPGA connect the register information in CPLD on crawl mainboard with Header2；
The register information that FPGA decoding compilings obtain, then passes through numeral method motherboard power supply signal condition.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, on server master board
CPLD obtains the Power Good signals that signal in mainboard electrifying timing sequence includes PCH signals, platform reset signals and each VR.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, which is
4pin forms, including clock lines, data lines, GND lines and the power lines to Debug card power supply.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, Header2 passes through
Cable is connected with header1.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, Header2 can be with
It is connected with header1 by Scan Chain buses.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, it is also set in Debug card
A ROM is set, FPGA includes the software code information of FPGA operations and the power supply of definition by the spi bus ROM, the ROM
Status information, if wherein some signal has exception, charactron that will show corresponding information.
Specifically, a kind of method by Debug card debugging server power supply is claimed in the application, which is characterized in that
This method specifically includes：
CPLD on server master board obtains signal in mainboard electrifying timing sequence, and the state of these signals is stored in posting for CPLD
In storage；
It is arranged on the CPLD on the header1 on one group of I2C signal to mainboard；
Header2, band I2C interface decoding compiler, Light-Emitting Diode are set in Debug card；
This decodes compiler with I2C interface and connect the register information captured on mainboard in CPLD with Header2；
The register information obtained with I2C interface decoding compiler decoding compiling, then passes through diode displaying
Motherboard power supply signal condition.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, on server master board
CPLD obtains the Power Good signals that signal in mainboard electrifying timing sequence includes PCH signals, platform reset signals and each VR.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, which is
4pin forms, including clock lines, data lines, GND lines and the power lines to Debug card power supply.
As described above by the method for Debug card debugging server power supply, it is further characterized in that, Header2 passes through
Cable is connected with header1.
Description of the drawings
The work flow diagram of Fig. 1, the present invention
The circuit diagram that Debug card is connect with mainboard in Fig. 2, embodiment 1
The circuit diagram that Debug card is connect with mainboard in Fig. 3, embodiment 2
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment to the present invention
It does and is further described in detail：
One, embodiment one
It is the embodiment of the present invention one shown in attached drawing 2.
1, the CPLD on server master board obtains the signal of interest in mainboard electrifying timing sequence, these signals include PCH
DSW_PWROK signals that (Platform Controller Hub, platform management center south bridge) is sent out, platform reset signals with
And the Power Good signals etc. of each VR (Voltage Regulator, voltage adjuster), the state of these signals can preserve
In the register of CPLD.
2, one group of I2C (Inter-Integrated Circuit, twin wire universal serial bus) signal is arranged on CPLD to arrive
On header1 on mainboard, this header1 is 4pin forms, including clock lines, data lines, GND lines and Debug card is given to supply
The power lines of electricity.
3, Debug card is connect by cable with the Debug header on mainboard.It is provided in Debug card and header1
Identical header2 is defined, header1 is connected with header2 by cable.The connection of plate intercard communication can also walk Scan
Other buses such as Chain buses, as long as it is unimpeded to meet communication.
4, the signal on the Header2 in Debug card is connected to the FPGA (Field-Programmable in Debug card
Gate Array, field programmable gate array), then FPGA can capture the register on mainboard in CPLD by this I2C signal
Information.
5, the information that the FPGA decoding compilings in Debug card obtain, then passes through numeral method motherboard power supply state.
FPGA in Debug card has hung a ROM (Read-only Memory, read-only storage below by spi bus
Device), this ROM includes the software code information of FPGA operations and the power state information of definition.If wherein some signal has
Abnormal, charactron will show corresponding information.Specific example is as shown in the table：
Table 1
Two, embodiment two
It is the embodiment of the present invention two shown in attached drawing 3.Compared with embodiment one, embodiment is second is that by Debug boards
FPGA has changed the general decoding compiler with I2C interface into, while changing charactron into 8 light emitting diodes, in this way can be with
Reduce the cost of board；On the other hand, display device is become into the connection of 8 lines from 14 lines, easily facilitates compiling.8 light-emitting diodes
Pipe can go to read by way of 8421 yards, and the effect of generation only needs to read by 8421 yards as charactron
It takes.For example, lamp is bright to indicate 1, the go out state of 0,8 lamps of expression of lamp is that go out light on and off of going out are bright successively, as 0,000 0101,
8421 yards of reading is 05, may determine that it is that corresponding P3V3_PG is problematic by table 1.
The entire workflow and embodiment one of example two are identical.
It should be evident that two specific implementation modes of the only present invention illustrated above, for the common skill in this field
For art personnel, without creative efforts, other technical solutions can also be obtained according to above-described embodiment,
And the equivalent variations made within the protection scope of the present invention should all be fallen within the scope of protection of the present invention, and belong to the present invention
The range of protection.
Method of the present invention by Debug card debugging server power supply does not have to when server is in cabinet
Mainboard is taken out, need to only be inserted into external Debug boards can find power issue place, be convenient for the debugging of server master board, also drop
The low risk for leading to server power supply short circuit when being surveyed with multimeter point.Meanwhile, it is capable to show abort situation, therefore can be quickly accurate
Server master board power issue is really found, debugging efficiency is improved.
The present invention can not also design individual Debug boards, but directly be designed in the case where motherboard space allows
It is shown on to mainboard, does not have to additional corresponding FPGA and decoding compiler.
Claims (10)
1. a kind of method by Debug card debugging server power supply, which is characterized in that this method specifically includes：
CPLD on server master board obtains signal in mainboard electrifying timing sequence, and the state of these signals is stored in the register of CPLD
In；
It is arranged on the CPLD on the header1 on one group of I2C signal to mainboard；
Header2, FPGA, charactron are set in Debug card；
The Header2 is connect with the Debug header1 on mainboard；
The FPGA connect the register information in CPLD on crawl mainboard with Header2；
The register information that FPGA decoding compilings obtain, then passes through numeral method motherboard power supply signal condition.
2. as described in claim 1 by the method for Debug card debugging server power supply, it is further characterized in that, server master
CPLD on plate obtains the Power Good that signal in mainboard electrifying timing sequence includes PCH signals, platform reset signals and each VR
Signal.
3. as claimed in claim 2 by the method for Debug card debugging server power supply, it is further characterized in that, the header1
For 4pin forms, including clock lines, data lines, GND lines and the power lines to Debug card power supply.
4. as claimed in claim 3 by the method for Debug card debugging server power supply, it is further characterized in that, Header2 is logical
Cable is crossed with header1 to be connected.
5. as claimed in claim 2 by the method for Debug card debugging server power supply, it is further characterized in that, Header2 is also
It can be connected with header1 by Scan Chain buses.
6. as claimed in claim 4 by the method for Debug card debugging server power supply, it is further characterized in that, in Debug card
A ROM is also set up, FPGA passes through software code information and the definition that the spi bus ROM, the ROM include FPGA operations
Power state information, if wherein some signal has exception, charactron that will show corresponding information.
7. a kind of method by Debug card debugging server power supply, which is characterized in that this method specifically includes：
CPLD on server master board obtains signal in mainboard electrifying timing sequence, and the state of these signals is stored in the register of CPLD
In；
It is arranged on the CPLD on the header1 on one group of I2C signal to mainboard；
Header2, band I2C interface decoding compiler, Light-Emitting Diode are set in Debug card；
This decodes compiler with I2C interface and connect the register information captured on mainboard in CPLD with Header2；
The register information obtained with I2C interface decoding compiler decoding compiling, then passes through diode displaying mainboard
Power supply signal state.
8. as claimed in claim 7 by the method for Debug card debugging server power supply, it is further characterized in that, server master
CPLD on plate obtains the Power Good that signal in mainboard electrifying timing sequence includes PCH signals, platform reset signals and each VR
Signal.
9. as claimed in claim 8 by the method for Debug card debugging server power supply, it is further characterized in that, the header1
For 4pin forms, including clock lines, data lines, GND lines and the power lines to Debug card power supply.
10. as claimed in claim 9 by the method for Debug card debugging server power supply, it is further characterized in that, Header2
It is connected with header1 by cable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810050878.4A CN108318831A (en) | 2018-01-18 | 2018-01-18 | A method of passing through Debug card debugging server power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810050878.4A CN108318831A (en) | 2018-01-18 | 2018-01-18 | A method of passing through Debug card debugging server power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108318831A true CN108318831A (en) | 2018-07-24 |
Family
ID=62894743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201810050878.4A Pending CN108318831A (en) | 2018-01-18 | 2018-01-18 | A method of passing through Debug card debugging server power supply |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113341907A (en) * | 2021-04-20 | 2021-09-03 | 深圳市创智成科技股份有限公司 | System and debugging method for universal Debug card |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103092740A (en) * | 2013-01-22 | 2013-05-08 | 浪潮电子信息产业股份有限公司 | Method of realizing hardware status indication |
| CN104268053A (en) * | 2014-10-21 | 2015-01-07 | 浪潮电子信息产业股份有限公司 | Design method of novel server debugging card |
| CN106708686A (en) * | 2017-03-07 | 2017-05-24 | 济南浪潮高新科技投资发展有限公司 | Mainboard power supply debugging and maintenance method for multichannel server |
-
2018
- 2018-01-18 CN CN201810050878.4A patent/CN108318831A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103092740A (en) * | 2013-01-22 | 2013-05-08 | 浪潮电子信息产业股份有限公司 | Method of realizing hardware status indication |
| CN104268053A (en) * | 2014-10-21 | 2015-01-07 | 浪潮电子信息产业股份有限公司 | Design method of novel server debugging card |
| CN106708686A (en) * | 2017-03-07 | 2017-05-24 | 济南浪潮高新科技投资发展有限公司 | Mainboard power supply debugging and maintenance method for multichannel server |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113341907A (en) * | 2021-04-20 | 2021-09-03 | 深圳市创智成科技股份有限公司 | System and debugging method for universal Debug card |
| CN113341907B (en) * | 2021-04-20 | 2024-04-12 | 深圳市创智成科技股份有限公司 | System and debugging method of general Debug card |
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Application publication date: 20180724 |