CN100435107C - Electrifying timing sequence testing device and method thereof - Google Patents

Electrifying timing sequence testing device and method thereof Download PDF

Info

Publication number
CN100435107C
CN100435107C CNB2006100087886A CN200610008788A CN100435107C CN 100435107 C CN100435107 C CN 100435107C CN B2006100087886 A CNB2006100087886 A CN B2006100087886A CN 200610008788 A CN200610008788 A CN 200610008788A CN 100435107 C CN100435107 C CN 100435107C
Authority
CN
China
Prior art keywords
time difference
display
timing sequence
signal
cpld
Prior art date
Application number
CNB2006100087886A
Other languages
Chinese (zh)
Other versions
CN101017455A (en
Inventor
张能军
Original Assignee
深圳市顶星数码网络技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市顶星数码网络技术有限公司 filed Critical 深圳市顶星数码网络技术有限公司
Priority to CNB2006100087886A priority Critical patent/CN100435107C/en
Publication of CN101017455A publication Critical patent/CN101017455A/en
Application granted granted Critical
Publication of CN100435107C publication Critical patent/CN100435107C/en

Links

Abstract

This invention discloses one electricity sequence test device, which comprises complex programmable logic parts connected to clock generation circuit and parallel single machine, wherein, the single machine is connected with control device and display device and the complex programmable logic part is composed of register. This invention also discloses one test method, which comprises the following steps: through plug or board to lead out test signal; the logic par collects test signals jump with first one as reference point and using reference clock generated by the impulse to compute other signal with first jump signals time difference value; then storing the time difference into the register.

Description

Electrifying timing sequence testing device and method
Technical field
The present invention relates to a kind of proving installation and method of computer motherboard, refer in particular to a kind of electrifying timing sequence testing device and method that is used for main board for notebook computer.
Technical background
In the notebook computer development, we need some signals on the testing host (as+V5AL, RSMRST#, powering on and power-off sequential SLP_S3# etc.), because logic analyser is somewhat expensive, way is to reserve test point to these signals preferably at present, select a signal for referencial use with oscillograph, triggering is done on variation edge with it, measure the waveform of these several signals, the sequential chart thereby the mistiming of reading two edges between the signal then draws, this method is subjected to the restriction of channel oscilloscope number, and all must go to look on the mainboard test point when running into problem of start-up at every turn, need a lot of times of waste.
Summary of the invention
The object of the present invention is to provide a kind of proving installation that can succinctly and efficiently test the power or power-down sequential of some signals on the main board for notebook computer.
Another object of the present invention is to provide a kind of method of succinctly and efficiently testing the power or power-down sequential of some signals on the main board for notebook computer.
The technical scheme that the present invention is adopted for its purpose of realization is: electrifying timing sequence testing device comprises CPLD, and it connects clock generation circuit and parallel single-chip microcomputer respectively, and this parallel single-chip microcomputer also connects control device and display device respectively.This CPLD includes register.
The technical scheme that the present invention is adopted for its another purpose of realization is: utilize the electrifying timing sequence method of above-mentioned electrifying timing sequence testing device may further comprise the steps:
(1) draws test signal by slot or plate from mainboard;
(2) CPLD is gathered the hopping edge of signal to be tested, and be reference point with first hopping edge, the pulse that produces with clock generation circuit is as the reference clock, calculate other signal hopping edges and first has the time difference of the hopping edge of hopping edge signal, then this time difference is existed in its register;
(3) parallel single-chip microcomputer reads the time difference in the register, and the output condition of setting by control device exports display device to, and the display format that the driving display device is set by control device shows this time difference.
Compared with prior art, the present invention can by host slot or plate promptly can testing host on the power or power-down sequential of some signals, easy to operate, and low cost product.
Description of drawings
The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings:
Fig. 1 is the principle schematic of electrifying timing sequence testing device of the present invention.
Embodiment
See also Fig. 1, electrifying timing sequence testing device of the present invention comprises a CPLD (Complex Programmable Logic Device, CPLD) 10, it connects clock generation circuit 20 and parallel single-chip microcomputer 30 respectively, and this parallel single-chip microcomputer 30 also connects control device 40 and display device 50 respectively.
CPLD 10 comprises register 12.This CPLD 10 is used to gather the hopping edge of signal to be tested, and be reference point with first hopping edge, the pulse that produces with clock generation circuit 20 is as the reference clock, calculate other signal hopping edges and first has the time difference of the hopping edge of hopping edge signal, then this time difference is existed in its register 12.Because the least unit that the electrifying timing sequence of the signal on the main board for notebook computer requires is microsecond (μ s),, the Tpd of the CPLD that selects for use of the present invention (pin-to-pin delay: pin is to the pin time-delay) just can meet the demands so being less than or equal to 10ns.Clock generation circuit 20 can adopt active crystal oscillator etc.Parallel single-chip microcomputer 30 is used for reading the time difference of the register 12 of CPLD 10, and drives display device 50 and show.The single-chip microcomputer 30 that should walk abreast can adopt the 16F87X series monolithic among 51 series monolithics or the PIC.Control device 40 can be used for the displaying contents of the display format of setting-up time difference, the output condition of setting parallel single-chip microcomputer 30, adjustment display device 50 etc.Display device 50 can with of the present invention other partly integrated to a PCB (Printed Circuit Board: printed circuit board (PCB)), also can be external.This display device 50 can be with common 7 sections charactrons or small LCD (Liquid CrystalDisplay: liquid crystal display) display.
During test, draw test signal by slot or plate 60 from mainboard, the hopping edge that CPLD 10 gathers signal to be tested, and be reference point with first hopping edge, the pulse that produces with clock generation circuit 20 is as the reference clock, calculate other signal hopping edges and first has the time difference of the hopping edge of hopping edge signal, this time difference is existed in its register 12 then, parallel single-chip microcomputer 30 reads the time difference in the register 12, the output condition of setting by control device 40 exports display device 50 to, and the display format that driving display device 50 is set by control device 40 shows this time difference.When display device 50 can not show the All Time difference, can switch content displayed by control device 40.
The present invention can make the card of pegging graft, during use by host slot or plate can testing host on the power or power-down sequential of some signals, easy to operate, and low cost product.

Claims (7)

1. electrifying timing sequence testing device, it is characterized in that: it comprises CPLD (10), it connects clock generation circuit (20) and parallel single-chip microcomputer (30) respectively, should also connect control device (40) and display device (50) respectively by parallel single-chip microcomputer (30), this CPLD (10) comprises register, the hopping edge that CPLD (10) is used to gather signal to be tested, with first hopping edge is reference point, the pulse that produces with clock generation circuit (20) is as the reference clock, calculate other signal hopping edges and first has the time difference of the hopping edge of hopping edge signal, and this time difference existed in its register, parallel then single-chip microcomputer (30) reads the time difference in the register of CPLD (10), the output condition of the parallel single-chip microcomputer of setting according to control device (40) (30) exports display device (50) to, and drives display device (50) and show this time difference by the display format of the time difference of control device (40) setting.
2. electrifying timing sequence testing device according to claim 1 is characterized in that: the Tpd of described CPLD (10) is less than or equal to 10ns.
3. electrifying timing sequence testing device according to claim 1 is characterized in that: described clock generation circuit (20) is active crystal oscillator.
4. electrifying timing sequence testing device according to claim 1 is characterized in that: described parallel single-chip microcomputer (30) is the 16F87X series monolithic among 51 series monolithics or the PIC.
5. electrifying timing sequence testing device according to claim 1 is characterized in that: described display device (50) is integrated into a PCB with CPLD (10), clock generation circuit (20), parallel single-chip microcomputer (30) and control device (40).
6. electrifying timing sequence testing device according to claim 1 is characterized in that: described display device (50) is 7 sections charactrons or LCD display.
7. electrifying timing sequence method of testing of using one of any described electrifying timing sequence testing device of claim 1 to 6, it may further comprise the steps:
(1) draws test signal by slot or plate from mainboard;
(2) CPLD (10) is gathered the hopping edge of signal to be tested, and be reference point with first hopping edge, the pulse that produces with clock generation circuit (20) is as the reference clock, calculate other signal hopping edges and first has the time difference of the hopping edge of hopping edge signal, this time difference is existed in its register (12) then;
(3) parallel single-chip microcomputer (30) reads the time difference in the register (12), and the output condition of setting by control device (40) exports display device (50) to, and the display format that driving display device (50) is set by control device (40) shows this time difference.
CNB2006100087886A 2006-02-11 2006-02-11 Electrifying timing sequence testing device and method thereof CN100435107C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006100087886A CN100435107C (en) 2006-02-11 2006-02-11 Electrifying timing sequence testing device and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006100087886A CN100435107C (en) 2006-02-11 2006-02-11 Electrifying timing sequence testing device and method thereof

Publications (2)

Publication Number Publication Date
CN101017455A CN101017455A (en) 2007-08-15
CN100435107C true CN100435107C (en) 2008-11-19

Family

ID=38726479

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100087886A CN100435107C (en) 2006-02-11 2006-02-11 Electrifying timing sequence testing device and method thereof

Country Status (1)

Country Link
CN (1) CN100435107C (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102253357B (en) * 2011-04-01 2013-07-31 青岛乾程电子科技有限公司 Pulse collector for mass watt-hour meter
CN102768633A (en) * 2012-06-29 2012-11-07 浪潮电子信息产业股份有限公司 Method for testing start and stop of server mainboard based on time series monitoring
CN103200423A (en) * 2013-04-12 2013-07-10 江苏北方湖光光电有限公司 Delayed detection device of video picture processing system
CN103744769A (en) * 2014-01-18 2014-04-23 浪潮电子信息产业股份有限公司 Rapid error positioning method of power supply of server based on complex programmable logic device (CPLD)
CN104375915A (en) * 2014-12-16 2015-02-25 浪潮电子信息产业股份有限公司 Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing
CN105548865B (en) * 2016-01-19 2018-07-06 歌尔股份有限公司 A kind of camera module electrifying timing sequence testing device and test method
CN105699788A (en) * 2016-04-27 2016-06-22 浪潮电子信息产业股份有限公司 Power supply time sequence measurement method, oscilloscope and system thereof
CN107797050A (en) * 2017-10-20 2018-03-13 郑州云海信息技术有限公司 A kind of method of location-server mainboard electrifying timing sequence abnormal state
CN109509506B (en) * 2018-12-20 2021-05-14 珠海博雅科技有限公司 Method and device for detecting Vcc during power-on test

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998005126A1 (en) * 1996-07-26 1998-02-05 Exel Microelectronics, Inc. Power-up detector for low power systems
CN1612509A (en) * 2003-10-31 2005-05-04 西安大唐电信有限公司 Method for detecting periodic signal disorder
CN1731354A (en) * 2005-08-16 2006-02-08 中国船舶重工集团公司第七○九研究所 Design method of power on self test (POST) in embedded system of PC hierarchy

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998005126A1 (en) * 1996-07-26 1998-02-05 Exel Microelectronics, Inc. Power-up detector for low power systems
CN1612509A (en) * 2003-10-31 2005-05-04 西安大唐电信有限公司 Method for detecting periodic signal disorder
CN1731354A (en) * 2005-08-16 2006-02-08 中国船舶重工集团公司第七○九研究所 Design method of power on self test (POST) in embedded system of PC hierarchy

Also Published As

Publication number Publication date
CN101017455A (en) 2007-08-15

Similar Documents

Publication Publication Date Title
CN101903865B (en) A method for testing in a reconfigurable tester
US6182248B1 (en) Method and tool for computer bus fault isolation and recovery design verification
CN100538652C (en) In having the system of a plurality of time domains, incident is carried out the equipment and the method for time-sequencing
EP1129408B1 (en) Microcomputer with test instruction memory
JP4335999B2 (en) Semiconductor integrated circuit device with built-in processor
EP0919028B1 (en) A method for emulating a non-bond-out version of a microcontroller that has standard port means and a system for executing the emulation
EP1632825B1 (en) Improvements in or relating to programmable logic controller and related electronic devices
KR100337006B1 (en) Method and apparatus for design verification of electronic circuits
US8538720B2 (en) Cold boot test system and method for electronic devices
CN100401820C (en) Cellular phone and operational mode switching method thereof
CN100375054C (en) Monitoring diagnosis device of computer main board failure
EP1922555A2 (en) Selectable jtag or trace access with data store and output
US8448112B1 (en) System, method, and computer program product for automatic power management verification
IL167671A (en) Communication interface for diagnostic circuits of an integrated circuit
CN100498650C (en) Driving controlling device of luminescence element and driving device of luminescence element
US20070168766A1 (en) Providing precise timing control between multiple standardized test instrumentation chassis
CN103186441B (en) Switching circuit
CN100395720C (en) Automated computer on-off operation testing device and method
JPH10503866A (en) Portable computer keyboard for use with multiple different host computers
CN101615104B (en) System for switching hard disks and switching method
WO2005048582B1 (en) Portable automatic test instrument for video displays and generators
JP2004037278A (en) Circuit verifying system
US20110066888A1 (en) System and method for testing sleep and wake functions of computer
CN102540060A (en) Digital integrated circuit chip testing system
KR100634991B1 (en) Integrated circuit tester with disk-based data streaming

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
GR01 Patent grant
C14 Grant of patent or utility model
ASS Succession or assignment of patent right

Owner name: SHENZHEN DINGHAI ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: SHENZHEN CITY DINGXING DIGITAL NETWORK TECHNOLOGY CO., LTD.

Effective date: 20100316

TR01 Transfer of patent right

Effective date of registration: 20100316

Address after: 518000, Shenzhen Industrial Zone, industrial zone, Shenzhen export processing zone, Longgang District, Guangdong, China, five floor, new industrial district

Patentee after: Shenzhen Dinghai Electron Co., Ltd.

Address before: 518040 Guangdong city of Shenzhen province Futian District Che Kung Temple Tairan Industrial Park 201 East 8 floor

Patentee before: Shenzhen Dingxing Digital Network Technology Co., Ltd.

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 518040 EAST 8F, BUILDING 201, TAIRAN INDUSTRIAL PARK, CHEGONGMIAO, FUTIAN DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE TO: 518000 HOUSE 5, BUILDING B, DAXIN INDUSTRY RESIDENTIAL QUATER, TAISHANG INDUSTRIAL PARK ZONE, SHENZHEN EXPORT PROCESSING AREA, LONGGANG DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081119

Termination date: 20150211

EXPY Termination of patent right or utility model