CN104077202A - Computer system - Google Patents
Computer system Download PDFInfo
- Publication number
- CN104077202A CN104077202A CN201410312843.5A CN201410312843A CN104077202A CN 104077202 A CN104077202 A CN 104077202A CN 201410312843 A CN201410312843 A CN 201410312843A CN 104077202 A CN104077202 A CN 104077202A
- Authority
- CN
- China
- Prior art keywords
- signal
- power supply
- computer system
- power
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention provides a computer system. The computer system comprises a plurality of power supply control units and a detection unit, wherein each power supply control unit is used for receiving a power supply enable signal to start the working of the power supply control unit, and outputting a power supply ready signal to indicate the state of the power supply controlled by the power supply control unit; the detection unit is provided with a plurality of detection modules, each detection module is used for receiving the power supply enable signal received by the corresponding power supply control unit and the output power supply ready signal, and when a first level is changed into a second level by the power supply enable signal, the first level is delayed by a preset time and then changed into the second level; when the power supply ready signal is in an invalid state, the detection module is used for outputting a power supply fault signal; when the power supply enable signal is changed into the first level from the second level, and the power supply ready signal is in the invalid state, the detection module is used for outputting the power supply fault signal.
Description
Technical field
The present invention relates to computer system, particularly whether a kind of power supply with the power control unit in detection computations machine system there is the computer system of abnormal function.
Background technology
When there is the phenomenons such as " cannot start shooting and power on ", " start power down " or " turning with regard to power down by shift knob fan " in server at present, testing staff just can only see through start sequential (power on sequence), with oscillograph or multimeter, remove to measure in order the coherent signals such as power supply good signal (power good signal) on a plurality of power control units in the computer system in server and power enable signal (power enable signal), to judge that finding is which power control unit goes wrong and causes server to start shooting.
Yet, existing detection method shortcoming is exactly, after server composition system, because computer system has been arranged on cabinet the inside, testing staff can not measure power supply good signal and power enable signal with oscillograph or multimeter easily, and which power control unit decision problem appears on soon, causes the inconvenience in trace routine.
Summary of the invention
The object of the present invention is to provide a kind of computer system, by the design of a plurality of logic lock elements, and power enable signal and the power supply good signal that according to original power control unit, will export, judge whether this power control unit occurs extremely.
For solving the problems of the technologies described above, the invention provides a kind of computer system, comprising:
A plurality of power control units, each power control unit receives the work of a power enable signal power-on control module, and exports a power supply ready signal with the state of the unit controlled of indication power control unit; And
One detecting unit, has a plurality of detection modules, each detection module be electrically connected accordingly power control unit one of them;
Wherein, detection module receives corresponding the power control unit power enable signal receiving and the power supply ready signal of exporting, when power enable signal will be changed to a second electrical level state by one first level state, to after the first level state time delay one Preset Time, be changed to second electrical level state, when power supply ready signal is during in non-productive work state, detection module is exported a power failure signal to indicate power control unit in an abnormal work state, and when power enable signal is the first level state by second electrical level state variation, and power supply ready signal is when non-productive work state, detection module out-put supply fault-signal is to indicate power control unit in abnormal work state.
When in one embodiment, the power supply interval greater than power control unit of Preset Time is normal, power enable letter inputs to the time interval of stating between the output of power supply ready signal.
In one embodiment, the first level state is low level, and second electrical level is high level.
In one embodiment, according to a power supply time-scale of computer system, the power enable signal of each detection module is the sequence relation that has time delay, or the power supply ready signal of each detection module output can be as the power enable signal of another detection module input.
In one embodiment, each detection module comprises:
One delay cell, in order to receive power enable signal, and when power enable signal will be changed to second electrical level state by the first level state, to after the first level state time delay Preset Time, be changed to second electrical level state and export a power enable time delayed signal, when power enable signal is changed to the first level by second electrical level, direct out-put supply enables time delayed signal;
One rp unit, in order to receive this power supply ready signal, carries out the ready inversion signal of anti-phase rear output one power supply to power supply ready signal; And
One logical block, in order to receive the ready inversion signal of power enable time delayed signal and power supply and to carry out logical and operation, out-put supply fault-signal.
In one embodiment, detecting unit is realized by inside programming by a CPLD, and CPLD is by Power supply to be started shooting, and at computing system, treats that open state and open state are all in running order.
In one embodiment, computer system also comprises a parallel serial conversion unit, the input end of parallel serial conversion unit is electrically connected the power failure signal in each detection module, and parallel serial conversion unit is in order to convert received at least one power failure signal to a string column signal.
Accept the above embodiments, detecting unit and parallel serial conversion unit have a CPLD to realize by inside programming, CPLD is by Power supply to be started shooting, and at computing system, treats that open state and open state are all in running order.
Accept the above embodiments, also comprise a baseboard management controller, baseboard management controller is by Power supply to be started shooting, treating that open state and open state are all in running order and manage with the duty to computer system in computer system, baseboard management controller receives the tandem signal of parallel serial conversion unit output, according to tandem signal, the duty of power control unit recorded and transfer to user side by a PORT COM, being beneficial to the abnormality of the rapid process computer system of user side.
Accept the above embodiments, PORT COM is a kind of in a network port, a serial ports, an I2C bus or a System Management Bus.
Accept the above embodiments, computer system more also comprises a display module, display module is electrically connected the output terminal of parallel serial conversion unit, display module is in order to produce a display according to tandem signal, and display is in order to the abnormity of power supply state of the power control unit in instruct computer system.
Computer system provided by the invention, there is following beneficial effect: the power enable signal that represents power enable state that this computer system is exported by its power control unit and the power supply ready signal that represents power supply kilter, and the design of the logic lock element in each detection module in detecting unit, whether the power supply that detects each power control unit in computer system occurs extremely, and produces according to this power fail signal.
Accompanying drawing explanation
Fig. 1 is the functional schematic of the computer system of one embodiment of the invention;
Fig. 2 is the thin portion functional schematic of detection module of the computer system of Fig. 1 embodiment;
Fig. 3 A is the signal timing diagram of computer system detection module when starting shooting and power fail does not occur power control unit of one embodiment of the invention;
Fig. 3 B is the signal timing diagram of computer system detection module when start and power control unit generation power fail of one embodiment of the invention;
Fig. 4 A is the signal timing diagram of computer system detection module when shutting down and power fail does not occur power control unit of one embodiment of the invention;
Fig. 4 B is the signal timing diagram of computer system detection module when shutdown and power control unit generation power fail of one embodiment of the invention.
Embodiment
Computer system the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 1, Fig. 1 is the functional schematic of the computer system of one embodiment of the invention.As shown in Figure 1, computer system (also claiming motherboard) 1 mainly comprises a plurality of power control units 10, detecting unit 12, parallel serial conversion unit (parallel/serial converter) 14 and display module 16.Wherein, detecting unit 12 more comprises a plurality of detection modules 120, each detection module 120 is electrically connected between described a plurality of power control unit 10 one of them and parallel serial conversion unit 14 accordingly, and the output terminal of parallel serial conversion unit 14 is electrically connected display module 16.In actual applications, the computer system 1 of the embodiment of the present invention is applicable to server system, but not as limit.In addition, in actual applications, detecting unit 12 can be realized by inside programming by CPLD (CPLD), this CPLD is by power supply to be started shooting (Standby power) power supply, described computer system 1 until open state and open state time all in running order.To with regard to each element in computer system 1, be described in detail respectively below.
Power control unit 10 receives power enable signal (power enable signal) S1 with the work of power-on control module 10, and out-put supply ready signal S2 is with the state of the power supply of indicating this power control unit 10 and being controlled.In more detail, power control unit 10 is in order to the server system power supply in when running to be provided, and each power control unit 10 can receive power enable signal S1 and to corresponding detection module 120 out-put supply ready signal S2.Wherein, power enable signal S1 is in order to indicate the power enable state of corresponding power control unit 10, power supply ready signal S2 is in order to indicate the power supply kilter of corresponding power control unit 10, in other words, power supply ready signal S2 is to be power supply good signal (power good signal).
In an embodiment of the present invention, when power enable signal S1 is high level (that is logic is " 1 "), represent that corresponding power control unit 10 is to be enabled, and make corresponding power control unit 10 start out-put supply; When power enable signal S1 is low level (that is logic is " 0 "), represents that corresponding power control unit 10 is to be disabled, and make corresponding power control unit 10 stop out-put supply.On the other hand, when power supply ready signal S2 is high level, represent that the power supply that corresponding power control unit 10 is exported is normal (also claiming that power supply is good); When power supply ready signal S2 is low level, represent that the power supply that corresponding power control unit 10 is exported is generation abnormal (also claiming power-fail or non-productive work state).
In actual applications, described a plurality of power control unit 10 can comprise P12V, P5V, P3V3, P1V8, PVDDQ, PVTT, PVPLL, PVSA and the PVCCP etc. that general computer system application arrives.In addition, P12V_STBY, P5V_STBY, P3V3_STBY, P1V8_STBY and P1V_STBY etc. when described a plurality of power control unit 10 more can comprise for standby (stand by), but the type of described a plurality of power control unit 10 is not limited with above-mentioned.The present invention is at this number of power control unit 10 and voltage level of out-put supply in limiting computer system 1 in addition not.
Detection module 120 receives the power enable signal S1 of corresponding power control unit 10 receptions and the power supply ready signal S2 of output.When power enable signal S1 will be changed to second electrical level state by the first level state, to after the first level state time delay Preset Time, be changed to second electrical level state, when power supply ready signal S2 is during in non-productive work state, detection module 120 meeting out-put supply fault-signal S3 are to indicate corresponding power control unit 10 in abnormal work state, and when power enable signal S1 is the first level state by second electrical level state variation, and power supply ready signal S2 is when non-productive work state, detection module 120 out-put supply fault-signal S3 are to indicate corresponding power control unit 10 in abnormal work state.
In other words, detection module 120 is in order to the accurate power supply status that detects corresponding power control unit 10 that changes in position with power supply ready signal S2 according to power enable signal S1, and occur when abnormal in the power supply that detects corresponding power control unit 10, produce power failure signal S3.In actual applications, the first described level state is low level, and described second electrical level state is high level.It should be noted that, power supply time-scale according to computer system 1, the power enable signal S1 of each detection module 120 is the sequence relation that has time delay, or the power supply ready signal S2 of each detection module 120 output can be used as the power enable signal S1 of another detection module 120 inputs.
The input end of parallel serial conversion unit 14 is electrically connected the output terminal (that is power failure signal S3) of each detection module 120, to receive 120 issuable power failure signal S3 of detection module.In actual operation, if described a plurality of power control unit 10 at least one of them power supply occur when abnormal, parallel serial conversion unit 14 can convert at least one received power failure signal S3 to a tandem signal.In actual applications, parallel serial conversion unit 14 can be a kind of universal input and output (General Purpose I/O, GPIO), but not as limit.In addition, in actual applications, detecting unit 120 and parallel serial conversion unit 14 can be realized by inside programming by CPLD (CPLD), this CPLD is by power supply to be started shooting (Standby power) power supply, and computer system 1 until open state and open state time all in running order.
Display module 16 produces display in order to the tandem signal of exporting according to parallel serial conversion unit 14, and this display occurs abnormal in order to the power supply of which power control unit 10 in instruct computer system 1.In actual applications, display module 16 can be a kind of display module (electronic display elements such as light emitting diode, display panel, seven-segment display.In addition, in embodiments of the present invention, display module 16 is also replaceable is sounding module (element such as the electronic sound such as loudspeaker, hummer).In addition, in actual operation, computer system 1 more includes a transistor-transistor logic (transistor-transistor logic, TTL) circuit (not shown), this transistor-transistor logic circuit is electrically connected between parallel serial conversion unit 14 and display module 16.
It should be noted that, the output terminal of the parallel serial conversion unit 14 in the computer system 1 of the embodiment of the present invention more can be electrically connected baseboard management controller (baseboard management controller, BMC) (not shown), this baseboard management controller is abnormal in order to come the power supply of which power control unit on detecting computer system 1 to occur according to received tandem signal, with the power supply status of the described a plurality of power control units 10 in remote monitoring computer system 1.In more detail, baseboard management controller is powered by power supply to be started shooting (Standby power), and computer system 1 until open state and open state time all in running order, so that the duty of computer system 1 is managed, baseboard management controller receives the tandem signal of parallel serial conversion unit 14 outputs, according to described tandem signal, the duty of described a plurality of power control units 10 recorded and transfers to user side by PORT COM, being beneficial to the abnormality of the rapid process computer system 1 of user side.In actual applications, described PORT COM can be a kind of network port, a kind of serial ports (COM PORT), a kind of I2C (Inter-Integrated Circuit) bus or a System Management Bus (SMBUS), but with above-mentioned, is not limited.
Practical operation situation for each detection module 120 in clearer explanation detecting unit 12, please also refer to Fig. 1 and Fig. 2, and Fig. 2 is the thin portion functional schematic of detection module of the computer system of Fig. 1 embodiment.As shown in Figure 2, each detection module 120 includes delay cell 1200, rp unit 1202 and logical block 1204.Wherein, the input end of delay cell 1200 is electrically connected the power enable signal S1 that corresponding power control unit 10 receives, the output terminal of delay cell 1200 is electrically connected one of them input end in logical block 1204, the input end of rp unit 1202 is electrically connected in corresponding power control unit 10 one end in order to out-put supply ready signal S2, the output terminal of rp unit 1202 is electrically connected another input end in logical block 1204, and the output terminal of logical block 1204 is electrically connected one of them input end in parallel serial conversion unit 14.
Delay cell 1200 is in order to receive power enable signal S1, and when power enable signal S1 will be changed to second electrical level state by the first level state, to after the first level state time delay Preset Time, be changed to second electrical level state and out-put supply enables time delayed signal, when power enable signal S1 is changed to the first level by second electrical level, direct out-put supply enables time delayed signal.In other words, delay cell 1200 is in order to receive and out-put supply enable signal S1, and when receiving the rising edge of power enable signal S1, postpones after one section of Preset Time just out-put supply enable signal S1.That is when positive edge triggering (that is transferring high level to by low level) occurs power enable signal S1, delay cell 1200 can postpone the power enable signal S1 that positive edge triggering occurs in output.
Rp unit 1202 is in order to receive power supply ready signal S2, and power supply ready signal S2 is carried out to the ready inversion signal of anti-phase rear out-put supply.That is rp unit 1202 is in order to receive power supply ready signal S2, and export according to this reverse power supply ready signal S2.In actual applications, rp unit 1202 is a kind of NOT logic locks.
Logical block 1204 is in order to receive the ready inversion signal of power enable time delayed signal and power supply and to carry out logical and operation, and out-put supply fault-signal S3 according to this.In other words, logical block 1204 judges with reverse power supply ready signal S2 whether the power supply of corresponding power control unit 10 occurs extremely in order to the received power enable signal S1 of foundation, and produces according to this power failure signal S3.In actual applications, logical block 1204 is a kind of AND logic locks.Certainly in affiliated technical field, have and conventionally know that the knowledgeable can also be designed to logical block 1204 combinational circuit (A & (～B)) of a kind of AND logic lock and NOT logic lock, therefore the present invention is in this implementation of circumscription logic unit 1204 in addition not.Below only with one of them power control unit 10 in computer system 1 when the practical operation, the situation that the detection module 120 of corresponding this power control unit 10 may detect is example.
Please also refer to Fig. 1, Fig. 2 and Fig. 3 A, Fig. 3 A is the signal timing diagram of computer system detection module when starting shooting and power fail does not occur power control unit of one embodiment of the invention.First be noted that computer system 1 is in the situation that starting shooting (also deserving to be called electricity) and power fail does not occur power control unit 10, power enable signal S1 can positive edge first occur compared with power supply ready signal S2 to be triggered.
As shown in Figure 3A, when computer system 1 is carried out start, can when time point t1, to corresponding delay cell 1200 outputs, there is the power enable signal S1 that positive edge triggers in power control unit 10, then, delay cell 1200 can one section of rear ability of preset time T 1 of delay will be exported through postponing the power enable time delayed signal S1 ' of preset time T 1 when time point t3.During being subject at power enable signal S1 that delay cell 1200 postpones that preset time T 1 just exports in (also real time point t1 is to the time interval of time point t3), described a plurality of power control units 10 can be when time point t2 the power supply ready signal S2 to the positive edge triggering of corresponding rp unit 1202 output generation.Finally, logical block 1204 can be when time point t3, an accurate state (being that logic is the low level of " 0 ") of the power supply ready signal S2 that the position accurate state (being that logic is the high level of " 1 ") of the power enable time delayed signal S1 ' through delay preset time T 1 that foundation is received and process are reverse, judge the power supply no exceptions of this power control unit 10, and make the power failure signal S3 that logical block 1204 is exported be continuously the low level not breaking down.
When the power supply interval greater than power control unit 10 that it should be noted that preset time T 1 is normal, power enable signal S1 inputs to the time interval between power supply ready signal S2 output.When in other words, 10 power supplys interval greater than power control unit of preset time T 1 are normal there is positive edge and be toggled to power supply ready signal S2 the positive edge time interval (also real time point t1 is to the time interval T2 of time point t) between triggering occurs in power enable signal S1.
Please also refer to Fig. 1, Fig. 2 and Fig. 3 B, Fig. 3 B is the signal timing diagram of computer system detection module when start and power control unit generation power fail of one embodiment of the invention.As shown in Figure 3 B, when computer system 1 is carried out start, can when time point t1, to corresponding delay cell 1200 outputs, there is the power enable signal S1 that positive edge triggers in power control unit 10, then, delay cell 1200 can one section of rear ability of preset time T 1 of delay will be exported through postponing the power enable time delayed signal S1 ' of preset time T 1 when time point t2.During being subject at power enable signal S1 that delay cell 1200 postpones that preset time T 1 just export in (also real time point t1 is to the time interval of time point t2), due to the power fail of this power control unit 10, and make the received power supply ready signal S2 of rp unit 1202 be continuously the low level that logic is " 0 ".Finally, logical block 1204 can be when time point t2, an accurate state (being that logic is the high level of " 1 ") of the power supply ready signal S2 that the position accurate state (being that logic is the high level of " 1 ") of the power enable time delayed signal S1 ' through delay preset time T 1 that foundation is received and process are reverse, the power supply of judging this power control unit 10 occurs abnormal, and makes the low level that power failure signal S3 that logical block 1204 is exported is " 0 " by logic change the high level that logic is " 1 " into.
Please also refer to Fig. 1, Fig. 2 and Fig. 4 A, Fig. 4 A is the signal timing diagram of computer system detection module when shutting down and power fail does not occur power control unit of one embodiment of the invention.First be noted that computer system 1 is in the situation that shutting down (also claiming power down) and power fail does not occur power control unit 10, power enable signal S1 can negative edge first occur compared with power supply ready signal S2 to be triggered.On the contrary, computer system 1 is the in the situation that of shutdown and power control unit 10 generation power fail, and power supply ready signal S2 can negative edge first occur compared with power enable signal S1 to be triggered.
As shown in Figure 4 A, when computer system 1 is carried out shutdown, can there is to corresponding delay cell 1200 outputs the power enable signal S1 that negative edge triggers in power control unit 10, make this delay cell 1200 immediately low level power enable signal S1 to be exported to logical block 1204 when time point t1.Then, because power fail does not occur this power control unit 10, therefore power control unit 10 can the power supply ready signal S2 that negative edge triggers occur to corresponding rp unit 1202 outputs when time point t2.Finally, logical block 1204 can be when time point t2, the position accurate state (being that logic is the high level of " 1 ") of the power supply ready signal S2 that the position accurate state (being that logic is the low level of " 0 ") of the power enable signal S1 that foundation is received and process are reverse, judge the power supply no exceptions of this power control unit 10, and make the power failure signal S3 that logical block 1204 is exported be continuously the low level not breaking down.
Please also refer to Fig. 1, Fig. 2 and Fig. 4 A, Fig. 4 B, Fig. 4 B is the signal timing diagram of computer system detection module when shutdown and power control unit generation power fail of one embodiment of the invention.As shown in Figure 4 B, because power fail occurs power control unit 10, therefore, when computer system 1 is carried out shutdown, the power supply ready signal S2 that above-mentioned power control unit 10 is exported can negative edge occur at time point t1 to be triggered.Now, the power enable signal S1 exporting due to this power control unit 10 is still positioned at high level, and not yet there is negative edge, triggers.Therefore, at time point t1 to the time interval of time point t2, the position accurate state (being that logic is the high level of " 1 ") of the power supply ready signal S2 that the position accurate state (being that logic is the high level of " 1 ") of the power enable signal S1 that logical block 1204 meeting foundations are received and process are reverse, the power supply of judging this power control unit 10 occurs abnormal, and to make power failure signal S3 that logical block 1204 exports be that logic is the high level of " 1 " at time point t1 during to the time interval of time point t2, until negative edge occurs power enable signal S1, trigger after (real time point t2), the high level that the power failure signal S3 that logical block 1204 is exported can be " 1 " by logic changes logic into for the low level of " 0 ".
In sum, the embodiment of the present invention discloses a kind of computer system, the power enable signal that represents power enable state that this computer system is exported by its power control unit and the power supply ready signal that represents power supply kilter, and the design of the logic lock element in each detection module in detecting unit, whether the power supply that detects each power control unit in computer system occurs extremely, and produces according to this power failure signal.Base this, each power failure signal that the computer system of the embodiment of the present invention can be exported by each detection module, learn fast and intuitively these detection modules respectively corresponding power control unit whether occur extremely, saved testing staff or user need according to the start sequential (power on sequence) of computer system come with oscillograph or multimeter, to measure in order the coherent signals such as relevant power enable signal and power supply ready signal with judgement be which power control unit goes wrong the required time of expending, extremely there is practicality.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection domain of claims.
Claims (11)
1. a computer system, is characterized in that, comprising:
A plurality of power control units, described in each, power control unit receives the work that a power enable signal is opened described power control unit, and exports a power supply ready signal with the state of the unit of indicating described power control unit and being controlled; And
One detecting unit, has a plurality of detection modules, described in each detection module be electrically connected accordingly described power control unit one of them;
Wherein, described detection module receives corresponding described the power control unit described power enable signal receiving and the described power supply ready signal of exporting, when described power enable signal will be changed to a second electrical level state by one first level state, to after described the first level state time delay one Preset Time, be changed to described second electrical level state, when described power supply ready signal is during in non-productive work state, described detection module is exported a power failure signal to indicate described power control unit in an abnormal work state, and when described power enable signal is this first level state by described second electrical level state variation, and described power supply ready signal is when non-productive work state, described detection module is exported described power failure signal to indicate described power control unit in this abnormal work state.
2. computer system as claimed in claim 1, is characterized in that, when the power supply interval greater than described power control unit of described Preset Time is normal described in power enable letter input to the time interval between the output of described power supply ready signal.
3. computer system as claimed in claim 1, is characterized in that, described the first level state is low level, and described second electrical level is high level.
4. computer system as claimed in claim 1, it is characterized in that, according to a power supply time-scale of described computer system, described in each, the described power enable signal of detection module is the sequence relation that has time delay, or the described power supply ready signal of detection module output described in each can be as the described power enable signal of detection module input described in another.
5. computer system as claimed in claim 1, is characterized in that, described each detection module comprises:
One delay cell, in order to receive described power enable signal, and when described power enable signal will be changed to described second electrical level state by described the first level state, to after Preset Time described in described the first level state time delay, be changed to described second electrical level state and export a power enable time delayed signal, when described power enable signal is changed to described the first level by this second electrical level, directly export described power enable time delayed signal;
One rp unit, in order to receive this power supply ready signal, carries out the ready inversion signal of anti-phase rear output one power supply to described power supply ready signal; And
One logical block, in order to receive described power enable time delayed signal and the ready inversion signal of described power supply and to carry out logical and operation, exports described power failure signal.
6. computer system as claimed in claim 1, it is characterized in that, described detecting unit is realized by inside programming by a CPLD, described CPLD is by Power supply to be started shooting, and at described computing system, treats that open state and open state are all in running order.
7. computer system as claimed in claim 1, it is characterized in that, described computer system also comprises a parallel serial conversion unit, the input end of described parallel serial conversion unit is electrically connected the described power failure signal in detection module described in each, and described parallel serial conversion unit is in order to convert received at least one described power failure signal to a string column signal.
8. computer system as claimed in claim 7, it is characterized in that, described detecting unit and described parallel serial conversion unit have a CPLD to realize by inside programming, described CPLD is by Power supply to be started shooting, and at described computing system, treats that open state and open state are all in running order.
9. computer system as claimed in claim 7, it is characterized in that, also comprise a baseboard management controller, described baseboard management controller is by Power supply to be started shooting, treating that open state and open state are all in running order and manage with the duty to described computer system in described computer system, described baseboard management controller receives the described tandem signal of described parallel serial conversion unit output, according to described tandem signal, the duty of described power control unit is recorded and transfer to user side by a PORT COM, be beneficial to user side and process rapidly the abnormality of described computer system.
10. computer system as claimed in claim 9, is characterized in that, described PORT COM is a kind of in a network port, a serial ports, an I2C bus or a System Management Bus.
11. computer systems as claimed in claim 7, it is characterized in that, described computer system more also comprises a display module, described display module is electrically connected the output terminal of described parallel serial conversion unit, described display module is in order to produce a display according to described tandem signal, and described display is in order to indicate the abnormity of power supply state of the described power control unit in described computer system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410312843.5A CN104077202A (en) | 2014-07-02 | 2014-07-02 | Computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410312843.5A CN104077202A (en) | 2014-07-02 | 2014-07-02 | Computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104077202A true CN104077202A (en) | 2014-10-01 |
Family
ID=51598471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410312843.5A Pending CN104077202A (en) | 2014-07-02 | 2014-07-02 | Computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104077202A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105049292A (en) * | 2015-08-20 | 2015-11-11 | 上海斐讯数据通信技术有限公司 | Fault indicating system |
| CN105094267A (en) * | 2015-07-29 | 2015-11-25 | 英业达科技有限公司 | Power supplying device |
| CN106292981A (en) * | 2016-08-04 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | A kind of server master board application process and system |
| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN109765500A (en) * | 2017-11-08 | 2019-05-17 | 中兴通讯股份有限公司 | A kind of power supply analog machine and power supply analogy method |
| CN109933182A (en) * | 2019-03-20 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of server power failure diagnostic method, device and system |
| CN111813037A (en) * | 2020-06-11 | 2020-10-23 | 中国长城科技集团股份有限公司 | Starting-up control method, starting-up control device and electronic equipment |
| CN113341334A (en) * | 2021-06-16 | 2021-09-03 | 西安易朴通讯技术有限公司 | Power failure processing system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727156A (en) * | 2008-10-10 | 2010-06-09 | 英业达股份有限公司 | Starting-up time sequence control device of computer and control method thereof |
| CN101866304A (en) * | 2010-02-24 | 2010-10-20 | 英业达股份有限公司 | Server capable of detecting state of voltage regulator |
| US20120144223A1 (en) * | 2010-12-07 | 2012-06-07 | Hitachi, Ltd. | Computer system |
| CN103176582A (en) * | 2011-12-23 | 2013-06-26 | 英业达股份有限公司 | Power supply sequential control device and adjusting method for power supply time sequence delay time |
-
2014
- 2014-07-02 CN CN201410312843.5A patent/CN104077202A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727156A (en) * | 2008-10-10 | 2010-06-09 | 英业达股份有限公司 | Starting-up time sequence control device of computer and control method thereof |
| CN101866304A (en) * | 2010-02-24 | 2010-10-20 | 英业达股份有限公司 | Server capable of detecting state of voltage regulator |
| US20120144223A1 (en) * | 2010-12-07 | 2012-06-07 | Hitachi, Ltd. | Computer system |
| CN103176582A (en) * | 2011-12-23 | 2013-06-26 | 英业达股份有限公司 | Power supply sequential control device and adjusting method for power supply time sequence delay time |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105094267A (en) * | 2015-07-29 | 2015-11-25 | 英业达科技有限公司 | Power supplying device |
| CN105049292A (en) * | 2015-08-20 | 2015-11-11 | 上海斐讯数据通信技术有限公司 | Fault indicating system |
| CN105049292B (en) * | 2015-08-20 | 2018-10-12 | 上海斐讯数据通信技术有限公司 | A kind of fault-indicating system |
| CN106292981A (en) * | 2016-08-04 | 2017-01-04 | 浪潮电子信息产业股份有限公司 | A kind of server master board application process and system |
| CN109765500A (en) * | 2017-11-08 | 2019-05-17 | 中兴通讯股份有限公司 | A kind of power supply analog machine and power supply analogy method |
| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN109933182A (en) * | 2019-03-20 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of server power failure diagnostic method, device and system |
| CN111813037A (en) * | 2020-06-11 | 2020-10-23 | 中国长城科技集团股份有限公司 | Starting-up control method, starting-up control device and electronic equipment |
| CN113341334A (en) * | 2021-06-16 | 2021-09-03 | 西安易朴通讯技术有限公司 | Power failure processing system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104077202A (en) | Computer system | |
| CN107193713B (en) | FPGA and method for realizing mainboard management control | |
| CN110515802A (en) | A kind of monitoring method, system and the associated component of server booting failure | |
| CN103605596B (en) | System and method for collaborative power management of FPGA (field programmable gata array) chip and BMC (baseboard management controller) chip used on ATCA (advanced telecom computing architecture) blade | |
| CN102147652A (en) | Shut-down energy-saving system and shut-down energy-saving method | |
| CN104375908A (en) | Method and equipment for detecting electric leakage of server | |
| US9524007B2 (en) | Diagnostic systems and methods of finite state machines | |
| WO2022187024A1 (en) | Independent slot control for peripheral cards | |
| CN103954946A (en) | T/R module debugging instrument | |
| CN114490208A (en) | Test apparatus, test method, computer device, storage medium, and program product | |
| TW201604679A (en) | Computer system | |
| CN207516929U (en) | Switching on and shutting down control circuit and mobile terminal | |
| CN203166465U (en) | Overvoltage protection circuit | |
| CN218824636U (en) | Power supply detection device for server hard disk backboard | |
| US20140164815A1 (en) | Server analyzing system | |
| CN116539992A (en) | Storage device in-place stable state detection device, method, logic module and medium | |
| CN115728665A (en) | Power failure detection circuit, method and system | |
| CN109885437A (en) | Baseboard management controller BMC, terminal and power-up state diagnotic module, method | |
| US20220082634A1 (en) | Power failure monitoring device and power failure monitoring method | |
| CN211698123U (en) | Power supply monitoring device | |
| CN210666782U (en) | System and device for verifying electric energy meter management chip | |
| TW202122962A (en) | System for visualizing power signal sequence | |
| CN103185847B (en) | Auxiliary test unit | |
| CN102263514A (en) | Direct current regulated power supply apparatus | |
| CN217932650U (en) | Power-on control module and case |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20141001 |
|
| WD01 | Invention patent application deemed withdrawn after publication |