TW201604679A - Computer system - Google Patents

Abstract

A computer system, includes multiple power control units and a detection unit. Each power control unit receives a power enable signal to turn on the power control unit, and outputs a power good signal to indicate the power state controlled by the power control unit. The detection unit includes multiple detection modules, each detection module receives the power enable signal and the power good signal of the corresponding power control unit. When the voltage level of the power enable signal is changed from a first level to a second level, the first level is delayed a preset time then changing the second level. The detection module outputs a power fault signal when the power good signal is invalid state. The detection module outputs the power fault signal when the power enable signal is changed from the second level to the first level and the power good level is invalid state.

Description

computer system

The present invention relates to a computer system, and more particularly to a computer system having the function of detecting whether a power source of a power control unit on a computer system is abnormal.

At present, the server can only use the oscilloscope in sequence through the power on sequence when there is a phenomenon such as "cannot be powered on", "powered off" or "powered down by the switch button." Or a multimeter to measure a power good signal and a power enable signal on a plurality of power control units on the computer system in the server to determine which power control unit is found. A problem has caused the server to fail to power on.

However, the shortcoming of the conventional detection method is that after the server is formed into a system, since the computer system is already installed in the chassis, it is not easy for the detection person to use the oscilloscope or the multimeter to measure the power good signal and the power enable signal, and also It is not possible to quickly determine which power control unit the problem is on, causing inconvenience in the detection procedure.

In view of the above problems, the present disclosure proposes a computer system, The computer system determines whether the power control unit is abnormal according to the design of the plurality of logic gate elements and according to the power enable signal and the power good signal that the original power control unit outputs.

According to a computer system in accordance with an embodiment of the present disclosure, the computer system includes a plurality of power control units and detection units. Each power control unit receives a power enable signal to turn on the power control unit and outputs a power ready signal to indicate the status of the power control controlled by the power control unit. The detecting unit has a plurality of detecting modules, and each detecting module is electrically connected to one of the plurality of power control units. The detection module receives the power enable signal received by the corresponding power control unit and the output power ready signal, and when the power enable signal changes from the first level state to the second level state, the first power is The flat state delay changes to the second level state after the preset time. When the power ready signal is in the inactive working state, the detecting module outputs a power failure signal to indicate that the power control unit is in an abnormal working state, and when the power source is enabled by the first When the two-level state changes to the first level state, and the power-good signal is in the inactive working state, the detecting module outputs a power failure signal to indicate that the power control unit is in an abnormal working state.

In an embodiment, the time interval of the preset time is greater than the time interval between the power enable signal input and the power ready signal output when the power control unit is powered.

In an embodiment, the first level state is a low level and the second level state is a high level.

In an embodiment, each of the power supply schedules of the computer system The power enable signal of one detection module is a sequence relationship with delay, or the power ready signal output by each detection module can be used as a power enable signal input by another detection module.

In an embodiment, each detection module includes a delay unit, an inverting unit, and a logic unit. The delay unit is configured to receive the power enable signal, and when the power enable signal is changed from the first level state to the second level state, the first level state is delayed by a preset time and then changed to the second level state. The output power enables the delay signal to directly output the power enable delay signal when the power enable signal changes from the second level to the first level. The inverting unit is configured to receive a power ready signal, and output a power ready inverted signal after inverting the power ready signal. The logic unit is configured to receive the power enable delay signal and the power ready reverse signal and perform logic and operation to output a power failure signal.

In an embodiment, the detecting unit is implemented by a complex programmable logic device through internal programming, and the complex programmable logic device is powered by the power to be turned on, and is in a working state in the standby state and the power-on state of the computer system.

In an embodiment, the computer system further includes a parallel-to-serial conversion unit, wherein the input end of the serial conversion unit is electrically connected to the power failure signal in each detection module, and the serial conversion unit is configured to receive the received at least one power supply. The fault signal is replaced by a serial signal.

According to the above embodiment, the detecting unit and the parallel-serial conversion unit are realized by internal programmable programming by a complex programmable logic device, and the complex programmable logic device is powered by the power to be turned on, and is in a state of being turned on and turned on in the computer system. State.

According to the above embodiment, the computer system further includes a baseboard management controller, and the baseboard management controller is powered by the power to be turned on, and is in a working state in the standby state and the power-on state of the computer system to manage the working state of the computer system, and the substrate The management controller receives the serial signal outputted by the parallel-to-serial conversion unit, records the working state of the plurality of power control units according to the serial signal, and transmits the working state to the user end through the communication port, so as to facilitate the user to quickly process the abnormality of the computer system. status.

According to the above embodiment, the computer system further includes a display module, the display module is electrically connected to the output end of the serial conversion unit, and the display module is configured to generate a display signal according to the serial signal, and the display signal is used to indicate the computer system. The power supply control unit has a power abnormal state. The above communication port is a network port or a serial port (COM PORT) or an I2C (Inter-Integrated Circuit) bus or a system management bus (SMBUS).

In summary, the present disclosure provides a computer system that transmits a power-enabled signal representing a power-enabled state and a power-good signal representing a power good state through a power control unit thereof, and a detection mode in the detection unit. The logic gate elements within the group are designed to detect if an abnormality has occurred in the power supply of each of the power control units on the computer system, and accordingly generate a power failure signal.

The above description of the disclosure and the following description of the embodiments are intended to illustrate and explain the spirit and principles of the invention and the invention The scope of the patent application is further explained.

1‧‧‧Computer system

10‧‧‧Power Control Unit

12‧‧‧Detection unit

120‧‧‧Test module

1200‧‧‧Delay unit

1202‧‧‧Inverting unit

1204‧‧‧Logical unit

14‧‧‧Parallel conversion unit

16‧‧‧Display module

S1‧‧‧Power enable signal

S2‧‧‧Power Ready Signal

S3‧‧‧Power failure signal

S1'‧‧‧ Delayed power-on delay signal for preset time

T1‧‧‧ preset time

T2‧‧‧ time interval

T1, t2, t3‧‧‧ time points

1 is a functional block diagram of a computer system in accordance with an embodiment of the present disclosure.

Figure 2 is a detailed functional block diagram of the detection module according to Figure 1.

FIG. 3A is a signal timing diagram of the detection module when the computer system is powered on and the power control unit does not have a power failure according to an embodiment of the present disclosure.

FIG. 3B is a signal timing diagram of the detection module when the computer system is powered on and the power control unit is powered off according to an embodiment of the present disclosure.

FIG. 4A is a signal timing diagram of the detection module when the computer system is turned off according to an embodiment of the present disclosure and the power control unit does not have a power failure.

FIG. 4B is a signal timing diagram of the detection module when the computer system is powered off and the power control unit is in a power failure according to an embodiment of the present disclosure.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1 , which is a diagram according to an embodiment of the present disclosure. A functional block diagram of a computer system. As shown in FIG. 1, the computer system (also referred to as the motherboard) 1 mainly includes a plurality of power supply control units 10, a detection unit 12, a parallel/serial converter 14 and a display module 16. The detecting unit 12 further includes a plurality of detecting modules 120, and each detecting module 120 is electrically connected to one of the plurality of power control units 10 and the parallel-to-serial converting unit 14, and the serial converting unit The output end of the 14 is electrically connected to the display module 16. The computer system 1 of the embodiment of the present invention is applicable to the server system, but is not limited thereto. In addition, in practice, the detecting unit 12 can be realized by a complex programmable logic device (CPLD) through internal programming, and the complex programmable logic device is powered by a standby power source, and is turned on and turned on in the computer system. The status is working. The respective components in the computer system 1 will be described in detail below.

The power control unit 10 receives a power enable signal S1 to turn on the operation of the power control unit 10, and outputs a power ready signal S2 to indicate the state of the power controlled by the power control unit 10. In more detail, the power control unit 10 is configured to provide power when the server system is in operation, and each of the power control units 10 can receive the power enable signal S1 and output a power ready signal S2 to the corresponding detection module 120. The power enable signal S1 is used to indicate the power enable state of the corresponding power control unit 10, and the power ready signal S2 is used to indicate the power good state of the corresponding power control unit 10, in other words, the power ready signal S2. It is a power good signal.

In the embodiment of the present invention, when the power enable signal S1 is at a high level (also That is, when the logic is "1"), it indicates that the corresponding power control unit 10 is enabled, and the corresponding power control unit 10 starts to output power; when the power enable signal S1 is low (that is, the logic is When "0"), it means that the corresponding power supply control unit 10 is disabled, and the corresponding power supply control unit 10 stops outputting power. On the other hand, when the power-good signal S2 is at a high level, it indicates that the power output of the corresponding power control unit 10 is normal (also called power good); when the power-good signal S2 is low, it indicates the corresponding power supply. The power output from the control unit 10 is an abnormality (also referred to as a power failure or an inactive operating state).

In practice, the plurality of power control units 10 may include P12V, P5V, P3V3, P1V8, PVDDQ, PVTT, PVPLL, PVSA, and PVCCP applied by a general computer system. In addition, the plurality of power control units 10 may further include P12V_STBY, P5V_STBY, P3V3_STBY, P1V8_STBY, and P1V_STBY when used by stand by, but the types of the plurality of power control units 10 are not limited to the above. The present invention does not limit the number of power control units 10 on the computer system 1 and the voltage level of the output power source.

The detection module 120 receives the power enable signal S1 received by the corresponding power control unit 10 and the output power ready signal S2. When the power enable signal S1 changes from the first level state to the second level state, the first level state is delayed by a preset time to a second level state, when the power ready signal S2 is in an inactive state. The detecting module 120 outputs a power failure signal S3 to indicate that the corresponding power control unit 10 is in an abnormal working state, and when the power enabling signal S1 changes from the second level state to the first level state, and the power is ready Signal S2 In the inactive working state, the detecting module 120 outputs a power failure signal S3 to indicate that the corresponding power control unit 10 is in an abnormal working state.

In other words, the detecting module 120 is configured to detect the power state of the corresponding power control unit 10 according to the level change of the power enable signal S1 and the power ready signal S2, and detect the power of the corresponding power control unit 10 When an abnormality occurs, a power failure signal S3 is generated. In practice, the first level state is a low level, and the second level state is a high level. It should be noted that, according to the power supply timing table of the computer system 1, the power enable signal S1 of each detection module 120 has a sequence relationship with delay, or the power ready signal S2 output by each detection module 120 can be used as another The power enable signal S1 input by the detection module 120 is detected.

The input end of the parallel conversion unit 14 is electrically connected to the output end of each detection module 120 (ie, the power failure signal S3) to receive the power failure signal S3 that may be generated by the detection module 120. In actual operation, if the power supply of at least one of the plurality of power control units 10 is abnormal, the parallel-to-serial conversion unit 14 converts the received at least one power failure signal S3 into a serial signal. In practice, the parallel-to-serial conversion unit 14 can be a general-purpose input/output (General Purpose I/O, GPIO), but is not limited thereto. Moreover, in practice, the detection unit 120 and the parallel-to-serial conversion unit 14 can be implemented by a complex programmable logic device (CPLD) that is powered by a standby power supply (Standby power) and is in a computer system. The standby state and the power-on state of 1 are all in working state.

The display module 16 is configured to output the string according to the parallel-to-serial conversion unit 14. The display signals are used to generate display signals for indicating which power supply control unit 10 on the computer system 1 is abnormally powered. In practice, the display module 16 can be a display module (such as a light-emitting diode, a display panel, a seven-segment display, etc.). In addition, in the embodiment of the present invention, the display module 16 can also be replaced with a sound. Module (such as electronic sounding components such as speakers, buzzers, etc.) In addition, in actual operation, computer system 1 further includes a transistor-transistor logic (TTL) circuit (not shown in The transistor-transistor logic circuit is electrically connected between the parallel-to-serial conversion unit 14 and the display module 16.

It is to be noted that the output of the parallel-to-serial conversion unit 14 in the computer system 1 of the embodiment of the present invention can be electrically connected to a baseboard management controller (BMC) (not shown). The management controller is configured to detect which power control unit power supply on the computer system 1 is abnormal according to the received serial signal to remotely monitor the power status of the plurality of power control units 10 on the computer system 1. In more detail, the baseboard management controller is powered by the standby power (Standby power), and is in a working state when the computer system 1 is in the power-on state and the power-on state, to manage the working state of the computer system 1, and the substrate management The controller receives the serial signal outputted by the parallel-to-serial conversion unit 14, records the working state of the plurality of power control units 10 according to the serial signal, and transmits the working state to the user terminal through the communication port, so that the user can quickly process the computer. The abnormal state of system 1. In practice, the above communication port can be a network port, a serial port (COM PORT), an I2C (Inter-Integrated Circuit) bus or a system management bus (SMBUS), but not the above Limited.

In order to more clearly explain the actual operation of each detection module 120 in the detection unit 12, please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a detailed functional block diagram of the detection module according to FIG. . As shown in FIG. 2, each detection module 120 includes a delay unit 1200, an inverting unit 1202, and a logic unit 1204. The input end of the delay unit 1200 is electrically connected to the power enable signal S1 received by the power control unit 10, and the output end of the delay unit 1200 is electrically connected to one of the input terminals of the logic unit 1204. The inverting unit 1202 The input end is electrically connected to one end of the power control unit 10 for outputting the power ready signal S2, and the output end of the inverting unit 1202 is electrically connected to the other input of the logic unit 1204, and the output of the logic unit 1204. One of the inputs of the parallel-to-serial conversion unit 14 is electrically connected.

The delay unit 1200 is configured to receive the power enable signal, S1, and when the power enable signal S1 is changed from the first level state to the second level state, the first level state is delayed by a preset time and then changed to the second state. The level state outputs a power enable delay signal, and directly outputs a power enable delay signal when the power enable signal S1 changes from the second level to the first level. In other words, the delay unit 1200 is configured to receive and output the power enable signal S1, and output the power enable signal S1 after delaying for a predetermined period of time after receiving the rising edge of the power enable signal S1. That is, when the power enable signal S1 is triggered by a positive edge (ie, from a low level to a high level), the delay unit 1200 delays the output of the power enable signal S1 at which the positive edge trigger occurs.

The inverting unit 1202 is configured to receive the power ready signal S2 and to the power supply The ready signal S2 is inverted to output a power ready inverted signal. That is, the inverting unit 1202 is configured to receive the power ready signal S2 and output a reverse power ready signal S2 accordingly. In practice, the inverting unit 1202 is a NOT logic gate.

The logic unit 1204 is configured to receive and perform a logic AND operation on the power enable delay signal and the power ready reverse signal, and output a power failure signal S3 accordingly. In other words, the logic unit 1204 is configured to determine whether the power of the corresponding power control unit 10 is abnormal according to the received power enable signal S1 and the reverse power ready signal S2, and accordingly generate a power failure signal S3. In practice, logic unit 1204 is an AND logic gate. Of course, those having ordinary knowledge in the technical field can also design the logic unit 1204 as a combination circuit of the AND logic gate and the NOT logic gate (A&(~B)), so the present invention does not limit the implementation of the logic unit 1204 herein. . In the following, only one of the power control units 10 on the computer system 1 may be detected by the detection module 120 of the power control unit 10 as an example.

Please refer to FIG. 1 , FIG. 2 and FIG. 3A together. FIG. 3A is a signal timing diagram of the detection module when the computer system is powered on and the power control unit does not have a power failure according to an embodiment of the present disclosure. It should be noted that, when the computer system 1 is powered on (also called power-on) and the power control unit 10 does not have a power failure, the power enable signal S1 will trigger positively before the power ready signal S2.

As shown in FIG. 3A, when the computer system 1 is powered on, the power control unit 10 outputs a power enable signal S1 that generates a positive edge trigger to the corresponding delay unit 1200 at time t1. Then, the delay unit 1200 will Delay a period After the preset time T1, the power enable delay signal S1' after the delay of the preset time T1 is outputted at the time point t3. In a period in which the power supply enable signal S1 is outputted by the delay unit 1200 after being delayed by the preset time T1 (that is, a time interval from the time point t1 to the time point t3), the plurality of power supply control units 10 may be at the time point t2. The corresponding inverting unit 1202 outputs a power-good signal S2 at which a positive edge trigger occurs. Finally, the logic unit 1204 will, at time t3, according to the received level of the power-on delay signal S1' that has been delayed by the preset time T1 (ie, the logic is "1" high level) and after the reverse The level state of the power-good signal S2 (ie, the low level of logic "0") determines that the power of the power control unit 10 is not abnormal, and causes the power failure signal S3 output by the logic unit 1204 to continue. A low level that has not failed.

It should be noted that the time interval of the preset time T1 is greater than the time interval between the input of the power enable signal S1 and the output of the power ready signal S2 when the power supply of the power control unit 10 is normal. In other words, the time interval between the preset time T1 is greater than the time interval between when the power supply control unit 10 of the power supply control unit is normal and the power supply enable signal S1 is positively triggered until the power supply ready signal S2 is positively edged (ie, the time point t1) Time interval T2) to time point t.

Referring to FIG. 1 , FIG. 2 and FIG. 3B together, FIG. 3B is a signal timing diagram of the detection module when the computer system is powered on and the power control unit is powered off according to an embodiment of the present disclosure. As shown in FIG. 3B, when the computer system 1 is powered on, the power control unit 10 outputs a power enable signal S1 that generates a positive edge trigger to the corresponding delay unit 1200 at time t1. The delay unit 1200 delays the power enable delay signal S1' after the delay time T1 is delayed at the time point t2 after a predetermined time T1. In a period in which the power supply enable signal S1 is output by the delay unit 1200 after being delayed by the preset time T1 (that is, a time interval from the time point t1 to the time point t2), the power supply unit 10 is powered off due to the power failure of the power supply control unit 10 The power ready signal S2 received by 1202 continues to be a low level of logic "0". Finally, the logic unit 1204, at time t2, according to the received level of the power-on delay signal S1' that has been delayed by the preset time T1 (ie, the logic is "1" high level) and after the reverse The level state of the power-good signal S2 (ie, the logic level of "1" is high) determines that the power supply of the power control unit 10 is abnormal, and causes the power failure signal S3 output by the logic unit 1204 to be logically The low level of "0" transitions to a high level of logic "1".

Referring to FIG. 1 , FIG. 2 and FIG. 4A together, FIG. 4A is a signal timing diagram of the detection module when the computer system is powered off and the power control unit does not have a power failure according to an embodiment of the present disclosure. It should be noted that, when the computer system 1 is turned off (also called power down) and the power control unit 10 does not have a power failure, the power enable signal S1 will trigger a negative edge before the power ready signal S2. Conversely, when the computer system 1 is turned off and the power control unit 10 has a power failure, the power ready signal S2 will trigger a negative edge first than the power enable signal S1.

As shown in FIG. 4A, when the computer system 1 performs shutdown, the power control unit 10 outputs a power-enable signal S1 that triggers a negative edge to the corresponding delay unit 1200 at time t1, so that the delay unit 1200 The low level power enable signal S1 is immediately output to the logic unit 1204. Then, due to this The power supply control unit 10 does not generate a power failure, so the power supply control unit 10 outputs a power-good signal S2 that generates a negative-edge trigger to the corresponding inverting unit 1202 at the time point t2. Finally, the logic unit 1204 will be at the time point t2 according to the level state of the received power enable signal S1 (ie, the low level of logic "0") and the level of the reverse power ready signal S2. The state (ie, the logic level of "1" is high) determines that the power supply of the power supply control unit 10 is not abnormal, and causes the power failure signal S3 output by the logic unit 1204 to continue to a low level that has not failed.

Please refer to FIG. 4B. FIG. 4B is a signal timing diagram of the detection module when the computer system is powered off and the power control unit is powered off according to an embodiment of the present disclosure. As shown in FIG. 4B, since the power supply control unit 10 has a power failure, when the computer system 1 performs shutdown, the power supply ready signal S2 output by the power control unit 10 will trigger a negative edge at time t1. At this time, since the power enable signal S1 output by the power control unit 10 is still at a high level, a negative edge trigger has not occurred. Therefore, in the time interval from the time point t1 to the time point t2, the logic unit 1204 will depend on the level state of the received power enable signal S1 (ie, the logic level is "1" high level) and the reverse direction. The level state of the power-good signal S2 (that is, the logic level of "1" is high) determines that the power supply of the power control unit 10 is abnormal, and causes the power failure signal S3 output by the logic unit 1204 to be at time t1. The time interval of the time point t2 is a high level of logic "1". After the power supply enable signal S1 has a negative edge trigger (ie, time point t2), the power failure signal S3 output by the logic unit 1204 is The high level of logic "1" transitions to the low level of logic "0."

In summary, the embodiment of the present invention discloses a computer system that transmits a power-enabled signal representing a power-enabled state and a power-good signal representing a power good state through a power control unit thereof, and each of the detection units. The design of the logic gate element in the detection module detects whether an abnormality occurs in the power supply of each power control unit on the computer system, and accordingly generates a power failure signal. Therefore, the computer system of the embodiment of the present invention can quickly and intuitively know whether the power control unit corresponding to each of the detection modules is abnormal through the power failure signals output by the detection modules, thereby eliminating the need for abnormality. The tester or user needs to use the oscilloscope or multimeter to measure the relevant signals of the power-enable signal and the power-good signal according to the power on sequence of the computer system in order to determine which power control unit has a problem. The time it takes is very practical.

Although the present invention has been disclosed above in the above embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1‧‧‧Computer system

10‧‧‧Power Control Unit

12‧‧‧Detection unit

120‧‧‧Test module

14‧‧‧Parallel conversion unit

16‧‧‧Display module

S1‧‧‧Power enable signal

S2‧‧‧Power Ready Signal

S3‧‧‧Power failure signal

Claims (11)

A computer system comprising: a plurality of power control units, each of the power control units receiving a power enable signal to activate the power control unit, and outputting a power ready signal to indicate the status of the power control controlled by the power control unit And a detecting unit having a plurality of detecting modules, each of the detecting modules being electrically connected to one of the power control units; wherein the detecting module receives the corresponding received by the power control unit The power enable signal and the output power ready signal are sent, and when the power enable signal is changed from a first level state to a second level state, the first level state is delayed by a preset time. For the second level state, when the power ready signal is in an inactive working state, the detecting module outputs a power failure signal to indicate that the power control unit is in an abnormal working state, and when the power enabling signal is from the first When the two-level state changes to the first level state, and the power-good signal is in an inactive working state, the detecting module loses The power failure indication signal to the power control unit is in the abnormal operation state. The computer system of claim 1, wherein the time interval of the preset time is greater than a time interval between the power enable signal input to the power ready signal output when the power control unit is normal. The computer system of claim 1, wherein the first level state is a low level and the second level state is a high level. The computer system of claim 1, wherein the power enable signal of each of the detection modules is in a sequence relationship with a delay, or the output of each of the detection modules, according to a power supply schedule of the computer system The power ready signal can be used as the power enable signal input by the other detection module. The computer system of claim 1, wherein each of the detection modules comprises: a delay unit for receiving the power enable signal, and when the power enable signal is changed from the first level state to the first In the two-level state, the first level state is delayed by the preset time and then changed to the second level state, and a power enable delay signal is output, when the power enable signal is changed from the second level to The first level directly outputs the power enable delay signal; an inverting unit is configured to receive the power ready signal, invert the power ready signal, and output a power ready inverted signal; and a logic unit, Receiving the power enable delay signal and the power ready reverse signal and performing a logical AND operation to output the power failure signal. The computer system of claim 1, wherein the detecting unit is implemented by a complex programmable logic device (CPLD) by internal programming, the complex programmable logic device being powered by a standby power source, in the computer system Both the power-on state and the power-on state are in a working state. The computer system of claim 1, wherein the computer system further comprises a parallel-to-serial conversion unit, wherein the input end of the parallel-serial conversion unit is electrically connected to the power failure signal in each of the detection modules, and the parallel-to-serial conversion The unit is configured to replace the received at least one power failure signal with a serial signal. The computer system of claim 7, wherein the detection unit and the parallel-to-serial conversion unit are implemented by a complex programmable logic device (CPLD) that is powered by a standby power supply (Standby power). The operating state and the power-on state of the computer system are in a working state. The computer system of claim 7, further comprising a baseboard management controller (BMC), the baseboard management controller is powered by a standby power source, and is in a working state and a power-on state of the computer system. a state is to manage the working state of the computer system, the substrate management controller receives the serial signal output by the parallel-serial conversion unit, records the working state of the power control unit according to the serial signal, and passes a communication The port is transmitted to the client to facilitate the user to quickly process the abnormal state of the computer system. The computer system of claim 9, wherein the communication port is a network port or a serial port (COM PORT) or an I2C (Inter-Integrated Circuit) bus or a system management bus (SMBUS). The computer system of claim 7, wherein the computer system further comprises a display module, the display module is electrically connected to the output end of the parallel-to-serial conversion unit, and the display module is configured to generate a signal according to the serial signal A display signal is used to indicate a power abnormal state of the power control units on the computer system.