CN112925696B - Power supply time sequence visualization system - Google Patents
Power supply time sequence visualization system Download PDFInfo
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- CN112925696B CN112925696B CN201911246585.4A CN201911246585A CN112925696B CN 112925696 B CN112925696 B CN 112925696B CN 201911246585 A CN201911246585 A CN 201911246585A CN 112925696 B CN112925696 B CN 112925696B
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- 238000012800 visualization Methods 0.000 title claims abstract description 23
- 238000004891 communication Methods 0.000 claims abstract description 19
- 238000012544 monitoring process Methods 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 8
- 230000008054 signal transmission Effects 0.000 claims description 8
- 239000003999 initiator Substances 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 5
- 239000000470 constituent Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 16
- 238000001514 detection method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/323—Visualisation of programs or trace data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
- G06F11/3062—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
- Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
- Y04S40/124—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wired telecommunication networks or data transmission busses
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- Data Mining & Analysis (AREA)
- Debugging And Monitoring (AREA)
- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
The invention provides a visualization system of a power supply time sequence, which mainly comprises: a microprocessor module and a control module. The microprocessor module includes: a first converter and a second converter. The first converter receives a power-on signal from a power chip and outputs a corresponding first digital signal, and the second converter receives a power-off signal from a power chip and outputs a corresponding second digital signal. By means of the design, a user receives a plurality of power supply time sequence data by connecting an electronic device to a communication unit of the control module through an Ethernet switching unit, and then monitors a power supply time sequence oscillogram to obtain the power supply operation conditions of all the constituent units of the power supply system.
Description
Technical Field
The invention relates to the technical field of power supply time sequences in power supply systems, in particular to a visualization system of a power supply time sequence.
Background
With the development of the complexity and diversification of electronic products, the Power-on sequence and the Power-off sequence of the Power system become more and more important. For example, if the voltage and current of each electronic component in the electronic product are not supplied in proper sequence, the power signal rises too fast or too slow, or the correct voltage of each component is not supplied sequentially, the signals and operation status of the circuit in the power system will be disturbed, and even the internal electronic components will be damaged and destroyed.
In order to make the electronic products safer, more economical, and more durable, it is important to detect and monitor the power timing signal and the amplitude signal of the electronic products. When the internal power of the electronic product has a problem, such as being unable to power on, power off or unstable voltage, the conventional method uses an Oscilloscope (Oscilloscope) or a Multimeter (Multimeter) to sequentially measure the power sequence (power sequence) of each signal source of the electronic device one by one. However, the use of an oscilloscope to measure the power timing of each signal source one by one results in a lot of labor cost, and the power sequence status or waveform of the electronic product cannot be known quickly. In addition, the detection method using the oscilloscope is difficult to avoid human careless mistakes and errors, and increases the probability of electric shock of personnel by the current of the power system. On the other hand, when the host of the electronic product is already installed in the chassis, if the above problem occurs, it is difficult to connect and measure the power-on timing signals of the signal sources of the electronic product using an oscilloscope or a multimeter, so that the state of the power timing cannot be detected in real time. Therefore, it is an urgent need in the related art to provide a method for effectively and rapidly detecting the power timing.
As can be seen from the above description, the conventional power timing detection method for electronic products still has some disadvantages. Therefore, the inventors of the present invention have made intensive studies and finally developed a power timing visualization system.
Disclosure of Invention
The invention provides a power supply time sequence visualization system, which mainly comprises: a microprocessor module and a control module. The micro-processing module includes: a first converter and a second converter. The first converter receives a power-on signal from a power chip and outputs a corresponding first digital signal. With such design, a user receives a plurality of power supply monitoring data and power supply oscillograms transmitted by the control module through an external electronic device, and then monitors the power supply time sequence oscillogram to obtain the power supply operation conditions of all the constituent units of the power supply system. According to the design of the invention, the power supply time sequence visualization system has the advantages of conveniently and quickly obtaining the power supply time sequence waveform, and effectively reduces the labor and time cost. Moreover, the user can monitor the power supply time sequence conditions of the electronic host in real time through the visual system of the power supply time sequence, so that the power supply system state of the electronic host can be clearly and conveniently monitored.
To achieve the above objective, the present invention provides an embodiment of a system for visualizing power timing in an electronic device, comprising:
a microprocessor module, which is arranged on a mainboard of an electronic host, and is electrically connected with a power chip arranged on the mainboard, and comprises:
the first converter receives a power supply starting signal from the power supply chip through a first signal transmission channel and generates a corresponding first digital signal according to the power supply starting signal, wherein the first digital signal is used for representing the power supply starting times of the power supply starting signal; and
a second converter, receiving a power-off signal from the power chip via a second signal transmission channel, and generating a corresponding second digital signal according to the power-off signal, wherein the second digital signal is used for representing a power-off frequency of the power-off signal;
the control module is electrically connected with the micro-processing module and comprises a communication unit; the control module receives the first digital signal and the second digital signal, and transmits a plurality of corresponding power monitoring data to an external electronic device through the communication unit.
In an embodiment of the system for visualizing a power timing of the present invention, the system further includes:
the bus is electrically connected between the micro-processing module and the control module;
the microprocessor module transmits the first digital signal and the second digital signal from a temporary storage of the microprocessor module to a temporary storage of the control module through a first channel of the bus, and the control module determines at least one first temporary storage address stored in the temporary storage of the control module according to a system frequency signal.
Drawings
FIG. 1 is a first block diagram of a visualization system showing a power timing sequence of the present invention;
FIG. 2 is a second block diagram of a power timing visualization system according to the present invention;
FIG. 3 is a third block diagram of a visualization system showing the power timing of the present invention;
FIG. 4 is a data diagram showing power waveforms and power data; and
FIG. 5 is a block diagram of a microprocessor module.
Reference numerals:
1 visualization system of power supply time sequence
11 micro-processing module
111 first converter
112 second converter
113 counting reset device
114 counting initiator
115 counting stopper
NSC first signal transmission channel
OSC second signal transmission channel
12 control module
121 network communication interface
11R temporary storage
12R temporary storage
13 Ethernet switching unit
3 electronic device
14 bus
141 first channel
2 mainboard
21 power supply chip
Detailed Description
In order to more clearly describe the power timing visualization system of the present invention, a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a first block diagram of a power timing visualization system according to the present invention is shown. Referring to fig. 2, a second block diagram of a power timing visualization system according to the present invention is shown. As shown in fig. 1 and fig. 2, the power timing visualization system 1 of the present invention includes a microprocessor module 11 and a control module 12; the microprocessor 11 is disposed on a Main Board (MB) 2 of an electronic host, and is electrically connected to a power chip 21. And, the microprocessor module 11 includes: a first converter 111 and a second converter 112. More specifically, the first converter 111 of the microprocessor module 11 receives a power on signal from the power chip 21 through a first signal transmission channel NSC, and generates a corresponding first digital signal according to the power on signal, where the first digital signal is used to indicate a power on (switch on) number of the power on signal. Furthermore, the second converter 112 receives a power-off signal from the power chip 21 through a second signal transmission channel OSC, and generates a corresponding second digital signal according to the power-off signal, where the second digital signal is used to indicate a power-off (switch off) number of the power-off signal. Next, the control module 12 is electrically connected to the microprocessor module 11 and includes a communication unit. Thus, the control module 12 receives the first power signal and the second power signal, and the communication unit transmits the corresponding power sequence data to an external electronic device 3.
As mentioned above, the Electronic host (Electronic host device) is a network server, and the communication unit is a network communication interface 121 for connecting with an ethernet switching unit 13 of the network server, so that the Electronic device 3 is connected to the control module 12 through the ethernet switching unit 13 and receives the plurality of power monitoring data. In addition, the communication unit is a wired communication interface or a wireless communication interface, and the electronic device 3 may be any one of the following: cloud server, notebook computer, panel computer, or smart phone. It should be noted that the microprocessor module 11 is a Field Programmable Gate Array (FPGA) chip or a Complex Programmable Logic Device (CPLD) chip. In this embodiment, the microprocessor module 11 is a Complex Programmable Logic Device (CPLD) chip. To illustrate, the first converter 111 is compiled into a firmware circuit in the form of a function library, variable or operand, and is further built into the microprocessor module 11; similarly, the second converter 112 is compiled into a firmware circuit in the form of a function library, variable or operand, and is further built into the microprocessor module 11. The control module 12 is a Baseboard Management Controller (BMC). It should be noted that, according to the functionality of the first converter 111, it may be regarded as turning on a Power on to digital converter (PN 2D); the second converter 112 can be regarded as a Power off to digital converter (PO 2D) according to its functionality.
With continued reference to fig. 2. Please refer to fig. 3, which is a third block diagram illustrating a power timing visualization system according to the present invention. As shown in fig. 3, the power timing visualization system of the present invention further includes a bus 14 electrically connected between the microprocessor module 11 and the control module 12. The microprocessor module 11 transmits the first digital signal and the second digital signal from a register 11R of the microprocessor module 11 to a register 12R of the control module 12 through a first channel 141 of the bus 14; then, the control module 12 determines at least one temporary address of the temporary memory 12R stored in the control module 12 according to a system clock signal. Please refer to fig. 4, which is a data diagram illustrating a power waveform and power data. As shown in fig. 4, the left half of fig. 4 is an exemplary example of the Power on signal (Power on signal) received by the control module 12, and the right half of fig. 4 is a waveform diagram of a plurality of Power timings presented by the electronic device 3 through the screen, wherein the electronic device (e.g., computer, mobile phone) is connected to the control module 12 through the ethernet switching unit 13 by a user using an external electronic device (e.g., computer, mobile phone). On the other hand, after the electronic device 3 is connected to the control module 12, the electronic device 3 receives a plurality of power monitoring data and compares the plurality of power monitoring data with a reference signal, and displays the plurality of power monitoring data on the electronic device 3 according to a comparison result. Thus, the user can conveniently monitor the Power timing waveform diagrams (Power waveform) of the Power on signal (Power on signal) and the Power off signal (Power off signal) of the electronic host and whether the Power timing waveform diagrams (Power waveform) meet the specification through the electronic device 3. In short, the user can easily monitor the power signal condition of the electronic host through the power timing visualization system 1 of the present invention. Moreover, when the start time of each signal source of the electronic host is up or no signal source is generated, the user can receive and check the waveform diagram (waveform) of the power timing signal and the comparison result by connecting to the network communication interface 121 of the control module 12.
With continued reference to fig. 3. Referring also to FIG. 5, a block diagram of the microprocessor module is shown. As shown in fig. 5, the microprocessor module 11 of the present invention further includes: a Counter resetting unit 113, a Counter initiator 114, and a Counter stopping unit 115. According to the design of the present invention, the microprocessor module 11 receives the first digital signal and the second digital signal of the electronic device 3, and resets the first converter 111 and/or the second converter 112 by the count reset device 113. Furthermore, the count initiator 114 is used for determining a start time of the first converter 111 and/or the second converter 112, and the count stopper 115 is used for determining a stop time of the first converter 111 and/or the second converter 112; thus, the micro processing module 11 further records the time point of the power on/off signal and generates a corresponding first digital signal or a corresponding second digital signal. It should be noted that the electronic host is an X86 host.
Thus, the technical features of the power timing visualization system 1 of the present invention are fully and clearly described above, and the following advantages can be obtained from the above description:
(1) unlike the method of using an oscilloscope to detect the power supply time sequence of each signal source of the electronic host one by one, a lot of labor cost and time cost are consumed. The invention provides a power supply time sequence visualization system 1, which mainly comprises: a microprocessor module 11 and a control module 12. A first converter 111 of the microprocessor module 11 receives a Power on signal (Power on signal) from a Power chip 21 and outputs a corresponding first digital signal. Moreover, the second converter 112 outputs a corresponding second digital signal according to a power-off signal received from the power chip 21. Then, the control module 12 receives the first digital signal and the second digital signal and outputs a plurality of corresponding power monitoring data. In this way, the user receives the power monitoring data and the power waveform diagram transmitted by the control module 12 through an external electronic device 3, and further monitors the power timing waveform diagram to obtain the power operation status of each component of the power system. According to the design of the present invention, the power timing visualization system 1 has the advantages of conveniently and rapidly obtaining the power timing waveform, and effectively reducing the labor and time costs. Moreover, the user can monitor the status of each power sequence of the electronic host in real time through the power sequence visualization system 1, thereby clearly and conveniently monitoring the status of the power system of the electronic host.
It should be emphasized that the above detailed description is specific to possible embodiments of the invention, but this is not to be taken as limiting the scope of the invention, and all equivalent implementations or modifications that do not depart from the technical spirit of the invention are intended to be included within the scope of the invention.
Claims (11)
1. A system for visualization of power timing, comprising:
a microprocessor module, which is disposed on a Main Board (MB) of an electronic host and is electrically connected to a power chip disposed on the main board, and is characterized by comprising:
the first converter receives a power supply starting signal from the power supply chip through a first signal transmission channel and generates a corresponding first digital signal according to the power supply starting signal, wherein the first digital signal is used for representing the power supply starting times of the power supply starting signal; and
the second converter receives a power supply closing signal from the power supply chip through a second signal transmission channel and generates a corresponding second digital signal according to the power supply closing signal, wherein the second digital signal is used for representing the power supply closing times of the power supply closing signal; and
the control module is electrically connected with the micro-processing module and comprises a communication unit; the control module receives the first digital signal and the second digital signal, and transmits a plurality of corresponding power monitoring data to an external electronic device through the communication unit.
2. The system for visualizing power timing of claim 1, wherein the electronic host is a network server, and the communication unit is a network communication interface for connecting with an ethernet switching unit of the network server, such that the electronic device is connected to the control module via the ethernet switching unit and receives the power monitoring data.
3. The system of claim 1, wherein the communication unit is a wired communication interface or a wireless communication interface, and the electronic device is any one of the following: cloud server, notebook computer, panel computer, or smart phone.
4. The system of claim 2, wherein the electronic device receives a plurality of power monitoring data and compares the power monitoring data with a reference signal, and displays a comparison result thereon.
5. The system for visualizing power timing of claim 1, wherein the micro-processing module is a Field Programmable Gate Array (FPGA) chip or a Complex Programmable Logic Device (CPLD) chip.
6. The system for visualizing power timing of claim 1 wherein the first translator is compiled as a firmware circuit in the form of a library, variables or operands and is built into the microprocessor module.
7. The system of claim 1, wherein the second converter is compiled as a firmware circuit in the form of a library, variables or operands and is built into the microprocessor module.
8. The system of claim 1, wherein the control module is a Baseboard Management Controller (BMC).
9. The system for visualizing power timing as in claim 1 further comprising:
the bus is electrically connected between the micro-processing module and the control module;
the microprocessor module transmits the first digital signal and the second digital signal from a temporary storage of the microprocessor module to a temporary storage of the control module through a first channel of the bus, and the control module determines at least one first temporary storage address stored in the temporary storage of the control module according to a system frequency signal.
10. The system for visualizing power timing of claim 1 wherein the microprocessor module further comprises:
a Counter resetting unit (Counter resetting unit) for resetting the first converter and/or the second converter;
a counting initiator for determining a start-up time of the first converter and/or the second converter; and
a count stop for determining a stop time of the first converter and/or the second converter.
11. The system for visualizing power timing of claim 1 wherein the electronic host is an X86 host.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911246585.4A CN112925696B (en) | 2019-12-06 | 2019-12-06 | Power supply time sequence visualization system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911246585.4A CN112925696B (en) | 2019-12-06 | 2019-12-06 | Power supply time sequence visualization system |
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| CN112925696B true CN112925696B (en) | 2022-08-23 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201199359Y (en) * | 2008-04-17 | 2009-02-25 | 福建升腾资讯有限公司 | Apparatus for monitoring state of mainboard power supply and sequence signal |
| TW200923391A (en) * | 2007-11-29 | 2009-06-01 | Gemtek Technology Co Ltd | Method and apparatus for power testing |
| CN104571434A (en) * | 2013-10-22 | 2015-04-29 | 英业达科技有限公司 | Server and reboot method thereof |
| TW201604679A (en) * | 2014-07-16 | 2016-02-01 | 英業達股份有限公司 | Computer system |
| US10394191B1 (en) * | 2018-03-27 | 2019-08-27 | Delta Electronics Int'l (Singapore) Pte Ltd | Time-to-digital converter |
-
2019
- 2019-12-06 CN CN201911246585.4A patent/CN112925696B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200923391A (en) * | 2007-11-29 | 2009-06-01 | Gemtek Technology Co Ltd | Method and apparatus for power testing |
| CN201199359Y (en) * | 2008-04-17 | 2009-02-25 | 福建升腾资讯有限公司 | Apparatus for monitoring state of mainboard power supply and sequence signal |
| CN104571434A (en) * | 2013-10-22 | 2015-04-29 | 英业达科技有限公司 | Server and reboot method thereof |
| TW201604679A (en) * | 2014-07-16 | 2016-02-01 | 英業達股份有限公司 | Computer system |
| US10394191B1 (en) * | 2018-03-27 | 2019-08-27 | Delta Electronics Int'l (Singapore) Pte Ltd | Time-to-digital converter |
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