CN112948220A

CN112948220A - Backboard control method and device and computer equipment

Info

Publication number: CN112948220A
Application number: CN202110339883.9A
Authority: CN
Inventors: 赵魁; 刘宜龙
Original assignee: Lenovo Beijing Information Technology Ltd
Current assignee: Lenovo Beijing Information Technology Ltd
Priority date: 2021-03-30
Filing date: 2021-03-30
Publication date: 2021-06-11

Abstract

The application provides a backboard control method, a backboard control device and computer equipment, wherein for a plurality of backboard controllers in an electronic system, calibration control information with a first time period sent by a main board controller is received, and phase calibration is carried out on output clock pulses based on the received calibration control information, so that the main board clock pulses are taken as calibration reference, the phase difference between the clock pulses output by each backboard controller and the main board clock pulses is reduced, the purpose of reducing the phase difference between the clock pulses output by the plurality of backboard controllers is achieved, then, the clock pulses after phase calibration are utilized, control signals of corresponding indicator lamps are obtained, the display state change of the indicator lamps is controlled, the display state change of the indicator lamps corresponding to the plurality of backboard controllers can be ensured to be basically consistent, and a user can conveniently and accurately and quickly determine the working state of a plurality of hard disks belonging to the same group of RAID indicated by the plurality of indicator lamps Status.

Description

Backboard control method and device and computer equipment

Technical Field

The present application relates to the field of communication control, and in particular, to a backplane control method and apparatus, and a computer device.

Background

Usually, a motherboard and information storage devices are assembled in the computer device, such as a hard disk, and in the running process of the computer device, in order to conveniently know whether the operation of the hard disk is abnormal in real time, the indicator lamp on the backplane is usually utilized to display the operation state of the corresponding hard disk, such as the power-on state and the read/write state of the hard disk, so that a user can conveniently and intuitively know whether the operation state of the hard disk is abnormal through the luminous information of the indicator lamp.

However, in a case where a computer device is equipped with a plurality of backplanes, reference frequencies of clock oscillators on the backplanes often have differences, which eventually causes the on-off flickering of the indicator lights on the backplanes to be inconsistent, especially in a case where hard Disks on a plurality of backplanes belong to the same group of Redundant Array of Independent Disks (RAID), when the group of RAID is in a rebuilding state, an indicator light on one backplane may be on, and an indicator light on another backplane is off, which may reduce the detection efficiency of the working state of the hard disk.

Disclosure of Invention

In view of this, the present application provides the following technical solutions:

in one aspect, the present application provides a backplane control method for an electronic system having a plurality of backplane controllers, the method comprising:

receiving calibration control information sent by a main board controller, wherein the calibration control information is determined according to a first time period;

performing phase calibration on the clock pulses output by the backplane controller based on the calibration control information to reduce phase differences among the clock pulses output by the plurality of backplane controllers;

and obtaining a control signal of a corresponding indicator light by using the clock pulse after phase calibration, wherein the control signal is used for controlling the display state change of the indicator light arranged on the back plate where the back plate controller is located.

In some embodiments, the obtaining of the calibration control information comprises:

the mainboard controller generates a mainboard clock signal with a second time period;

the mainboard controller determines calibration control information corresponding to the plurality of backboard controllers based on the mainboard clock signal; wherein the calibration control information comprises a calibration timestamp, and the calibration timestamp corresponds to a polarity state of the clock signal;

the mainboard controller sends the determined calibration control information to the corresponding backboard controller at the mainboard time of the calibration timestamp;

wherein the second time period is greater than the first time period.

In some embodiments, the determining, by the motherboard controller, calibration control information corresponding to each of the plurality of backplane controllers based on the motherboard clock signal includes:

the mainboard controller sequentially determines a plurality of calibration timestamps on the mainboard clock signal in each first time period, and the polarity states of the mainboard clock signals corresponding to the plurality of calibration timestamps;

the mainboard controller sends the determined calibration control information to the corresponding backboard controller at the mainboard time of the calibration timestamp, and the method comprises the following steps:

and when the mainboard controller determines any one of the calibration timestamps, the mainboard controller sends the determined calibration timestamp and the polarity state of the mainboard clock pulse corresponding to the calibration timestamp to any one of the backplate controllers which are not calibrated in the first time period.

In some embodiments, the determining, by the motherboard controller and based on the clock signal, calibration control information corresponding to each of the plurality of backplane controllers comprises:

the mainboard controller generates a matched calibration timestamp from any mainboard time generated by the mainboard clock signal in each first time period, and determines the polarity state of the mainboard time signal at the mainboard time;

and when determining the calibration timestamp, the mainboard controller respectively sends the calibration timestamp and the polarity state of the mainboard clock pulse corresponding to the calibration timestamp to the plurality of backboard controllers.

In some embodiments, the first time period of the determining calibration control information for each of the plurality of backplane controllers is different.

In some embodiments, the phase calibrating the clock pulse output by the backplane controller based on the calibration control information includes:

if the polarity state of the mainboard clock signal received this time is different from the polarity state of the mainboard clock signal received last time, updating the counting time of the backboard controller for the clock pulse according to the calibration timestamp so as to calibrate the backboard clock signal of the backboard controller;

and if the polarity state of the mainboard clock signal received this time is the same as the polarity state of the mainboard clock signal received last time, continuing to work according to the backboard clock signal of the backboard controller.

In some embodiments, the method further comprises:

detecting whether the calibration control information meets a calibration condition;

if the calibration condition is met, executing the step of sending the determined calibration control information to the corresponding backboard controller at the time of the mainboard where the calibration timestamp is positioned by the mainboard controller, or carrying out the phase calibration step on the clock pulse output by the backboard controller based on the calibration control information;

and if the calibration condition is not met, the plurality of backboard controllers continue to work according to respective backboard clock signals.

In some embodiments, the detecting whether the calibration control information satisfies a calibration condition includes:

detecting whether the polarity state of the mainboard clock signal contained in the calibration control information determined this time is the same as the polarity state of the mainboard clock signal determined last time or not for the same backboard controller;

the condition that the calibration condition is satisfied is specifically that a polarity state of the motherboard clock signal included in the calibration control information determined this time is different from a polarity state of the motherboard clock signal determined this time last time.

In another aspect, the present application further provides a backplane control apparatus adapted for an electronic system having a plurality of backplane controllers, the apparatus comprising:

the calibration control information receiving module is used for receiving calibration control information sent by the mainboard controller, wherein the calibration control information is determined according to a first time period;

the calibration processing module is used for carrying out phase calibration on the clock pulses output by the backplane controller based on the calibration control information so as to reduce the phase difference among the clock pulses output by the plurality of backplane controllers;

and the indicating lamp control module is used for obtaining a control signal of a corresponding indicating lamp by using the clock pulse after the phase calibration, and the control signal is used for controlling the display state change of the indicating lamp arranged on the back plate where the back plate controller is positioned.

In another aspect, the present application further provides a computer device, which includes

The system comprises a main board, a power supply and a power supply, wherein a main board controller is arranged on the main board;

the back plates are provided with back plate controllers and indicator lamps;

the main board controller is used for sending the determined calibration control information to the back board controller, wherein the calibration control information is determined according to a first time period;

each backboard controller is used for executing a program for realizing the following steps;

receiving the calibration control information sent by the mainboard controller;

based on the calibration control information, performing phase calibration on the clock pulses output by the backplane controller to reduce phase differences among the clock pulses output by the plurality of backplane controllers;

and obtaining a control signal corresponding to the indicator light by using the clock pulse after phase calibration, wherein the control signal is used for controlling the display state change of the indicator light arranged on the backboard where the backboard controller is located.

Therefore, the application provides a backboard control method, a backboard control device and a computer device, for a plurality of backboard controllers in an electronic system, all receiving calibration control information with a first time period sent by a main board controller, and performing phase calibration on output clock pulses based on the respective received calibration control information, so that the main board clock pulses are taken as calibration reference, the phase difference between the clock pulses output by each backboard controller and the main board clock pulses is reduced, thereby achieving the purpose of reducing the phase difference between the clock pulses output by the plurality of backboard controllers, and then using the clock pulses after phase calibration to obtain control signals of corresponding indicator lamps to control the display state change of the indicator lamps, thereby ensuring that the display state changes of the indicator lamps corresponding to the plurality of backboard controllers are basically consistent, the user can accurately and quickly determine the working states of the hard disks belonging to the same RAID group and indicated by the plurality of indicator lamps.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a comparison of clock pulses output by different backplane controllers;

FIG. 2 is a schematic diagram of a hardware structure of an alternative example of a computer device suitable for use in the backplane control method and apparatus proposed in the present application;

FIG. 3 is a schematic diagram of an alternative control link between a motherboard controller and a backplane controller of a computer device suitable for use in the backplane control method and apparatus provided herein;

FIG. 4 is a schematic flow chart diagram of an alternative example of a backplane controller method presented herein;

FIG. 5 is an alternative schematic diagram of the driving principle of the indicator lights on the back panel in the back panel controller method of the present application;

FIG. 6 is a signaling flow diagram of yet another alternative example of a backplane controller method presented herein;

fig. 7 is a schematic diagram of a motherboard controller sending calibration control information to a plurality of backplane controllers, which is suitable for the backplane control method and apparatus provided in the present application;

FIG. 8 is a schematic flow chart diagram of yet another alternative example of a backplane controller method presented herein;

FIG. 9 is a schematic flow diagram of yet another alternative example of a backplane controller method presented herein;

FIG. 10 is a signaling flow diagram of yet another alternative example of a backplane controller method presented herein;

FIG. 11 is a schematic diagram of an alternative example of a backplane controller apparatus according to the present application;

fig. 12 is a schematic structural diagram of yet another alternative example of the backplane controller apparatus proposed in the present application.

Detailed Description

To solve the technical problem described in the background section, for example, two backplanes (backplane a and backplane B) are installed on a server system, and if a clock of 50MHz ± 25PPM standard is used, i.e., the maximum clock deviation is twenty five parts per million, that is, 25 clocks are deviated every 1,000,000 clocks, and the clock is converted into a time concept, and according to the conversion method, 25 × 50 × 20ns is 25us, it is known that each second (50 × 10 × 20 ns) is⁶One clock) may be offset by 25 microseconds.

Based on the above analysis, if the clock specification of the backplane a is: 50MHz +0PPM, the backplate B has the following specifications all the time: 50MHz +25PPM, and the start-up time of the two backplane controllers is the same, in the initial stage, as shown in fig. 1, the 1Hz indicator light blinking pulses generated by the two backplane clocks are of the same phase, but as time goes on, the phases of the pulses generated by the crystal clocks of the two back plates will shift, and the phase shift amount becomes larger and larger until it becomes 20,000s (sec) to 5.55hours after 500ms (msec)/25 us (μ sec), as shown in fig. 1, the polarities of the clock signals of the two back plates are completely opposite, the flashing states of the indicator lights controlled correspondingly respectively are completely opposite, that is, the indicator light on one backboard is lighted, and the indicator light on the other backboard is extinguished, if the two indicator lights are used for indicating the working state of the same hard disk, this will seriously interfere the user to check the flashing state of the indicator light and determine the detection efficiency and accuracy of the working state of the hard disk.

In order to solve the problems, the application provides that the crystal oscillator clock offset phases of the backboard controllers are calibrated according to the system clock on the main board, so that the phase difference between clock pulses output by different backboard controllers is reduced, even though the pulses generated by different backboard controllers are kept basically consistent all the time, the flashing states of the indicator lamps on the corresponding backboard are kept basically consistent, the inconsistent flashing states of different indicator lamps for indicating the working state of the same hard disk are avoided, and the interference is caused to a user for checking the flashing state of the indicator lamps.

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments, for convenience of description, only the parts related to the related inventions are shown in the drawings, and features in the embodiments and the embodiments in the present application can be combined with each other without conflict. That is, all other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.

It should be understood that "system", "apparatus", "unit" and/or "module" as used herein is a method for distinguishing different components, elements, parts or assemblies at different levels. However, other words may be substituted by other expressions if they accomplish the same purpose.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. An element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

In the description of the embodiments herein, "/" means "or" unless otherwise specified, for example, a/B may mean a or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality" means two or more than two. The terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

Additionally, flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or several steps of operations may be removed from the processes.

Referring to fig. 2, a schematic diagram of a hardware structure of an alternative example of a computer device suitable for the backplane control method and apparatus provided in the present application is shown, where the computer device may be a server or a terminal device, and the terminal device may include, but is not limited to: tablet computers, Personal Computers (PCs), robots, desktop computers, and the like, the present application does not limit the product type of the computer device, and may be determined as the case may be. As shown in fig. 2, the computer apparatus may include:

a motherboard 100, the motherboard 100 having a motherboard controller 110 disposed thereon.

A plurality of backplates 200, a backplate controller 210 and an indicator light 220 are disposed on each backplate 200, and the backplates 200 are used to connect the motherboard 100 and the hard disk 300 in the computer equipment.

The motherboard 100 may be called a main board (main board) or a system board (system board), and is installed in a main chassis of a computer, which is one of the most important components of the computer. The main circuit System of the computer, such as a BIOS (Basic Input/Output System) chip, an I/O control chip, a keyboard and panel control switch interface, an indicator light connector, an expansion slot, a motherboard, and a dc power supply connector of the plug-in card, may be mounted on the rectangular circuit board.

Backplane 200 may be an interface of a plug board in a computer device, and enables connection between motherboard 100 of the computer device and other hardware in the computer device. Therefore, different backplanes, such as a power backplane, a fan backplane, a hard disk backplane, etc., can be distinguished according to the types of hardware connected to the backplanes, where the backplane 200 is mainly referred to as a hard disk backplane, and the application does not limit the specific structural composition of the hard disk backplane.

In some embodiments, the hard disks 300 may also be disposed on the corresponding backplanes 200, that is, a hard disk 300 is disposed on each backplane 200, and the hard disks 300 may belong to the same RAID group, for example, in the reconstruction state of the RAID group, the working states of the hard disks 300 are the same, and the display states of the indicator lights 220 on the backplanes 200 need to be consistent, so that a user can quickly and accurately know the working states of the hard disks.

It should be noted that, the deployment relationship between the hard disk 300 and the backplane 200 is not limited in the present application, and the present application is only described with the connection deployment relationship shown in fig. 2 as an example, and for a computer device having the deployment relationship between the hard disk 300 and the backplane 200 described in some embodiments, implementation processes of applying the backplane control method provided in the present application are similar, and details are not repeated in the present application.

Motherboard controller 110 may include, but is not limited to: an FPGA (Field Programmable Gate Array), a BMC (Baseboard Management Controller), and the like, as the case may be.

The backplane controller 210 may include, but is not limited to: a CPLD (Complex Programming logic device), a programmable system on a chip PSoC, and the like, as the case may be. In the embodiment of the present application, the types of the backplane controllers 210 on the plurality of backplanes 210 may be the same or different, and the present application does not limit the types of the plurality of backplane controllers 210.

In some embodiments, referring to a schematic diagram of an optional control link between a motherboard controller and a backplane controller of a computer device shown in fig. 3, taking the backplane controller as a CPLD for example, in a general case, an access link of the CPLD on each backplane is an I2C interface, that is, a simple and bidirectional two-wire (one data line SDA and one clock line SCL) synchronous serial bus interface, and the application does not describe the working principle of such an interface in detail.

In practical applications, the motherboard controller usually needs to write accurate calibration control information into each backplane controller at a relatively fast period (e.g., 250ms or 500 ms), so as shown in fig. 3, in this embodiment of the present application, the motherboard controller accessing each backplane controller may preferentially select an FPGA, rather than selecting a control device such as a BMC running under an operating system. Certainly, in some embodiments, the selection end of the selection switch in fig. 3 may be switched to the BMC, and the BMC may serve as a motherboard controller to access each backplane controller through the I2C physical link, which is still applicable to the backplane control method provided in this application, so as to implement calibration control on the respective backplane clock signals of each backplane controller.

Therefore, in the embodiment of the present application, the control right of the I2C physical link accessing the backplane may be arbitrated between the FPGA and the BMC as listed above but not limited thereto according to the actual application requirement or mechanism, so as to determine the motherboard controller in the current scenario of the motherboard. Optionally, the arbitration selection for the motherboard controller may be implemented by the BMC as a decision maker, but is not limited thereto.

It is understood that the motherboard controller is not limited to accessing the backplane controller on the backplane through the I2C physical link, and may also access other I2C devices on the backplane as needed, which is not listed herein.

The indicator lamp 220 is an indicator for indicating the operation state of the hard disk 300 connected to the back plate 200. For example, if the hard disk 300 is in a normal working state, the main board 100 controls the indicator light 230 on the back panel 200 connected to the hard disk to go off; if the hard disk 300 is in an abnormal working state, the main board 100 controls the indicator lamp 220 on the back panel 200 connected to the hard disk 300 to emit light, so that a user can directly determine whether the corresponding hard disk 300 works normally by turning on or off the indicator lamp 220.

It should be noted that, the association relationship between the hard disk operating state and the indicating state of the indicator light is not limited to the content described in the present embodiment, and may be determined as the case may be. Moreover, the indicator lights 220 may include, but are not limited to, LED lights, etc., and the types and the disposition positions of the indicator lights 220 on the back plates 200 are not limited in the present application, and may be determined according to the actual application requirements.

In this embodiment, in order to calibrate the clock signal output by each backplane controller 210, it is proposed that the motherboard controller 110 generates calibration control information with a certain time period, and periodically sends the calibration control information to each backplane controller 210, and then, for any backplane controller 210, it may execute the backplane control method proposed in this application to implement phase calibration of the clock pulse output by itself, and a specific control process may refer to the description of a corresponding part of the method embodiment below, which is not described herein again.

It can be seen that each backplane controller 210 actually calibrates each backplane time according to the system time of the motherboard 100, so that the clock pulse of each backplane controller 210 is substantially consistent with the system clock pulse, that is, the phase difference between the clock pulses output by different backplane controllers 210 is reduced, thereby ensuring that the flashing states of the indicator lamps 220 on the backplane 200 of different backplane controllers 210 are substantially consistent, and avoiding the situation that the flashing states of different indicator lamps 220 for indicating the hard disk operating states belonging to the same group of RAID (Redundant array of Independent Disks) are inconsistent when the group of RAID is in the rebuilt (Rebuild) state, which causes visual interference to the user viewing the flashing states of the indicator lamps, thereby improving the inspection efficiency of the hard disk operating states.

It should be understood that the structure of the computer device shown in fig. 2 is not limited to the computer device in the embodiment of the present application, and in practical applications, the computer device may include more or less components than those shown in fig. 2, or some components in combination, which is not listed here.

In conjunction with the computer device described above, referring to fig. 4, a flow diagram of an alternative example of the backplane controller method provided in the present application is shown, and the method may be applied to an electronic system having a plurality of backplane controllers, where the electronic system may include, but is not limited to, each of the computer devices listed above, so that the backplane control method provided in the present application may be applied to scenarios such as detection or maintenance of each of the computer devices listed above, and may also be applied to scenarios such as product development and test with the electronic system, and the present application does not limit a specific application scenario of the backplane control method.

As shown in fig. 4, the backplane control method provided in this embodiment and executed by any backplane controller in the electronic system may include:

step S41, receiving calibration control information sent by the mainboard controller;

as can be seen from the above description of the technical concept of the present application, the calibration control information is used to perform phase calibration on the constant pulses output by the backplane controller, and is determined by the motherboard controller according to the first time period, and the content included in the calibration control information is not limited by the present application. The time of the first time period may be determined according to calibration requirements of a specific scenario, that is, the smaller the phase difference between the clock pulses output by the clock crystal oscillators of the backplane controllers is, the smaller the value of the first time period is, so that the more the number of times of phase calibration of the clock pulses output by the backplane controllers is, that is, the higher the calibration frequency is, the closer the change of the display states of the indicator lights is.

Similarly, if the requirement for the consistent visual effect of the display state changes of the plurality of indicator lights in the current scene is not high, in order to reduce the occupation of system resources in the phase calibration process, the value of the first time period is relatively large, that is, the interval is relatively long, and the phase calibration is performed once on the clock pulse output by each backboard controller. It can be seen that the present application does not limit the specific value of the first time period, which may be determined according to the circumstances.

It can be seen that, for any backplane controller, it receives the calibration control information sent by the motherboard controller according to the first time period, and the calibration control information is generated by the motherboard controller according to the system time of the motherboard at the time when the motherboard controller needs to send the calibration control information, that is, the motherboard controller generates a calibration control information, and will directly send the calibration control information to the corresponding backplane controller, for example, the calibration control information is transmitted through the physical communication link shown in fig. 3, but is not limited to this transmission manner.

In some embodiments, the calibration control information sent by the motherboard controller to each backplane controller may be the same, and at this time, the motherboard controller is usually required to send the calibration control information to the plurality of backplane controllers at the same time. Certainly, the system resources are rich, and under the condition that normal implementation of other functions is ensured, the sending events of the calibration control information are sufficiently supported to be executed by a plurality of processes at the same time, and the sending mode greatly improves the phase calibration efficiency of the clock pulses of a plurality of backboard controllers.

In still other embodiments, the motherboard controller may also send various corresponding calibration control information to the backplane controllers in sequence, in this case, the backplane controllers receive their respective calibration control information at different times, and the contents of the respective calibration control information received by the backplane controllers often differ, and this way of sending the calibration control information requires relatively low system resources for each sending time, and often does not affect the implementation of other functions of the electronic system.

It should be noted that, the specific sending manner of the main board controller sending the plurality of calibration control information includes, but is not limited to, the above-listed two implementation manners, which may be determined as the case may be.

Step S42, performing phase calibration on the clock pulses output by the backplane controller based on the calibration control information to reduce the phase difference between the clock pulses output by the backplane controllers;

since the backplane control methods implemented by the plurality of backplane controllers in the electronic device are the same, the embodiment of the present application only takes the backplane control method executed by one backplane controller as an example for description, and thus, the backplane controller in the embodiment may be any backplane controller in the electronic system.

In this embodiment of the present application, since the calibration control information received by each backplane controller is determined and sent by the motherboard controller, each backplane controller performs phase calibration on the clock pulse output by its own clock crystal oscillator by using the received calibration control information, that is, calibrates the frequency division counter inside the backplane controller for driving the indicator light on the backplane to flash by using the received calibration control information, and if the current counting time of the frequency division counter is replaced by the calibration control information, the frequency division counter continues to count the clock pulse output by the backplane controller with the system time of the current motherboard as the starting time.

Therefore, the plurality of backplane controllers are calibrated according to the above method, and at respective calibration time, the count time of each of the plurality of backplane controllers is aligned with the system time, and since the difference between the respective calibration time of the plurality of backplane controllers is zero or a small value, after performing a phase calibration on the clock pulse output by each backplane controller according to the above method, the phase difference between the clock pulse output by each backplane controller and the clock pulse of the motherboard is reduced, which is equivalent to the clock pulse output by each backplane controller approaching the clock pulse of the motherboard, so that the phase difference between the clock pulses output by each backplane controller is reduced.

It should be understood that, for any backplane controller, one phase calibration is completed in the above manner, at the calibration time, the effect of reducing the phase difference between the clock pulses output by the multiple backplane controllers is achieved, but each subsequent backplane controller continues to output clock pulses according to the reference frequency of its own clock crystal oscillator, and before the next calibration, the phase difference may still be increased relative to the reduced phase difference corresponding to the calibration time as time advances, so that, in order to improve the control effect of the multiple indicator lamps flickering uniformly, the present application may continue to perform phase calibration on the clock pulses output by each of the multiple backplane controllers in the above manner, so as to gradually reduce the phase difference between the clock pulses output by the multiple backplane controllers until the phase difference is zero or a small value.

Certainly, after the phase calibration is performed once according to the above-mentioned phase calibration method, the reduced phase difference value can be ignored, that is, the blinking of the indicator lights is controlled according to the phase difference, and the human eyes of the user cannot distinguish the difference between the blinking states of the plurality of indicator lights, and it is considered that the blinking states of the plurality of indicator lights are consistent, and if the reduced phase difference is 25 microseconds at most, the phase calibration is not required to be performed any more; when the subsequent phase difference is larger than a certain threshold (a relatively large value, a user obviously feels the phase difference value corresponding to the inconsistency of the flashing states of the plurality of indicator lights, the specific size of the threshold is not limited by the application), the phase calibration is continuously performed on the clock pulses output by the plurality of backboard controllers according to the above mode, and therefore the occupation of system resources in the phase calibration process is reduced.

And step S43, obtaining a control signal of the corresponding indicator light by using the clock pulse after phase calibration, wherein the control signal is used for controlling the display state change of the indicator light arranged on the backboard where the backboard controller is located.

As can be seen from the above-mentioned schematic structural diagram of the computer device shown in fig. 2, the backplane controller is used as a driving device for the indicator on the backplane, and controls the indicator to turn on or off according to the high or low level of the clock pulse output by the backplane controller, and the flashing frequency of the indicator is generated by always dividing the frequency of the crystal oscillator of the backplane controller, as shown in an optional schematic diagram of the indicator driving principle shown in fig. 5, after frequency division by the divider, a relatively high frequency clock pulse signal is divided into always pulsed signals with different frequencies, and a high level fixed signal (e.g. a signal represented by '1' in fig. 5, which can control the indicator to turn on constantly) and a low level fixed signal (e.g. a signal represented by '0' in fig. 5, which can control the indicator to turn off constantly). Therefore, according to the actual requirement on the flashing frequency of the indicator light, the one-out-of-multiple selection unit can select the corresponding partitioned signal transmission port (for example, any one of the four dots on the left side in fig. 5) to be connected with the indicator light control port (for example, one dot on the right side in fig. 5), and the specific control process is not described in detail herein.

Based on the above analysis, after any backplane controller completes phase calibration of the clock pulse output by itself, the calibration time continues to output the clock pulse according to the clock frequency thereof, and then, as described above, a path of frequency division signal corresponding to a signal transmission port communicated with an indicator lamp control port can be determined as a control signal of the current stage of the indicator lamp, and after the control signal is transmitted to the indicator lamp, the flashing frequency of the indicator lamp is controlled according to the high and low levels contained in the control signal, that is, the display state change of the indicator lamp arranged on the backplane where the backplane controller is located is controlled. It should be noted that the determination process of the control signal of the indicator light is not limited to the control signal determination manner shown in fig. 5.

In summary, in the embodiment of the present application, for a plurality of backplane controllers in an electronic system, calibration control information having a first time period sent by a motherboard controller is received, and based on the respective received calibration control information, the phase calibration is carried out on the output clock pulse so as to hopefully realize the synchronization of the clock pulse output by each backboard controller and the clock pulse of the main board, thereby achieving the purpose of reducing the phase difference among the clock pulses output by the plurality of backboard controllers, then utilizing the clock pulses after phase calibration to obtain the control signals of the corresponding indicator lamps, the display state change of the indicator light is controlled, the display state change of the indicator light corresponding to each backboard controller can be basically consistent, a user can view the current display state of any one or more indicator lights in the plurality of indicator lights, and the working states of the plurality of hard disks belonging to the same RAID group are accurately and quickly determined.

Referring to fig. 6, which is a signaling flow diagram of another optional example of the backplane controller method provided in this application, this embodiment mainly describes how the motherboard controller determines a process of calibrating control information in the foregoing embodiment, and for an implementation process of how the backplane controller utilizes the calibration controller to perform calibration, reference may be made to descriptions of corresponding parts in the foregoing embodiment, which is not described in detail in this embodiment. As shown in fig. 6, the backplane controller method proposed in this embodiment may include:

step S61, the motherboard controller generates a motherboard clock signal having a second time period;

step S62, the mainboard controller determines calibration control information corresponding to each of the plurality of backboard controllers based on the mainboard clock signal;

in the embodiment of the present application, in order to implement periodic calibration of clock pulses output by each backplane controller, phase differences between clock pulses output by different backplane controllers are gradually reduced, until each clock pulse is consistent, a motherboard controller is proposed to periodically send calibration control information to each backplane controller, and in combination with the above description of the technical concept of the present application, in order to implement synchronization with accurate system clock pulses, the motherboard controller generates a motherboard clock signal having a second time period based on the motherboard clock pulses, and determines calibration control information corresponding to each of the plurality of backplane controllers for a standard in sequence.

It can be seen that the calibration control information determined in this embodiment includes the calibration timestamp, and the polarity state of the motherboard clock signal corresponding to the calibration timestamp, and the like. In addition, as can be known from the above description of the calibration control information, different backplane controllers can receive the calibration control information sequentially at different times (e.g., the system time of the calibration timestamp); the same calibration control information sent by the motherboard controller may also be received at the same time, which is not limited in this application.

In this embodiment of the application, the time of the second time period may be determined according to a maximum deviation value of a clock crystal oscillator of the backplane controller, and the second time period may be 2 seconds in the clock of 50MHz ± 25PPM standard of the above example, that is, the motherboard controller (such as FPGA, etc.) may generate a timestamp with 1s as a period, and simultaneously, according to characteristics of a clock signal, a polarity inversion pulse may be generated every 1 s. The second time period is not limited in size, and it can be understood that the second time period is greater than the first time period.

Step S63, the motherboard controller sends the determined calibration control information to the corresponding backplane controller at the motherboard time where the calibration timestamp included in the calibration control information is located.

Referring to fig. 7, a schematic diagram of a motherboard controller sending calibration control information to a plurality of backplane controllers is shown, and still taking an example that an electronic system includes two backplanes (backplane a and backplane B), the backplane controllers on the corresponding backplanes are respectively denoted as backplane controller a and backplane controller B, and then, for example, the motherboard controller generates a calibration timestamp with a period of 1S, and generates a motherboard clock signal with a polarity inversion pulse every 1S.

Then, the motherboard controller may determine to perform phase calibration on the clock pulse output by each backplane controller at any time, as shown in fig. 7, and write a calibration timestamp obtained thereby and the corresponding polarity state on the motherboard clock signal into a register of the backplane controller a (e.g., any backplane controller in the electronic system) at time t 1; similarly, a calibration timestamp thus obtained, and its corresponding polarity status on the motherboard clock signal, may be written into the register of backplane controller B at time t 2. If the electronic system includes more backplane controllers, the motherboard controller may continue to write corresponding calibration control information to other backplane controllers in this manner.

Since the polarity states of the motherboard clock signals at different times are not consistent, as shown in fig. 7, the polarity state corresponding to the calibration timestamp t5 written into the backplane controller a at time t5 is different from the polarity state written at time t 1.

It should be understood that, as described in the foregoing analysis, the motherboard controller does not necessarily send calibration control information to each backplane controller in sequence as shown in fig. 7, and may also invoke multiple processes, and send the same calibration control information to multiple backplane controllers at the same time, where the implementation process is similar to the above process of writing calibration control information into one backplane controller, and details of this application are not described here.

Step S64, determining, by any backplane controller, a polarity state of the currently received motherboard clock signal, which is different from a polarity state of the motherboard clock signal received last time, and updating a count time of the backplane controller for clock pulses according to the currently received calibration timestamp, so as to calibrate the backplane clock signal of the backplane controller;

in step S65, any backplane controller determines the polarity state of the currently received motherboard clock signal, which is the same as the polarity state of the last received motherboard clock signal, and continues to operate according to the backplane clock signal of the backplane controller.

Also as described above with reference to the calibration method shown in fig. 7, in the calibration control information sent by the motherboard controller at time t1, time t2, time t5 and time t6, the polarity state of the motherboard control signal jumps, such as from a high state to a low state, or from a low state to a high state, the backboard controller receiving the calibration control information at the corresponding time calibrates the indicator light flicker frequency division counter inside by using the received calibration time stamp, for example, the backplane controller may update the internal count time to the calibration timestamp received at time t1, time t2, time t5, time t6, etc. as described above, therefore, calibration of the backplane clock signal output by the backplane controller is achieved, and the backplane clock signal is synchronized with the motherboard clock signal at the moment.

Similarly, as shown in fig. 7, in the calibration control information generated by the motherboard controller at the time t3 and the time t4, the polarity state of the motherboard clock signal included in the calibration control information does not jump and is still in a low level state, and at this time, the backplane controller does not calibrate the internal count time of the motherboard clock signal according to the received calibration timestamp, and still continues to output the backplane clock signal, but during this period, the phases of the clock pulses output by the backplane controllers continue to shift, so that the phase difference between the clock pulses may continue to increase until the next phase calibration.

Based on the synchronization mechanism of clock pulses between the backplane controller and the motherboard controller shown in fig. 7, the calibration time period of each backplane controller in the electronic system will dynamically vary from 1s to (1s + T), and will not be greater than 2 s. Here, 1s refers to a time period during which the motherboard controller generates the polarity inversion pulse, and T may refer to a time period during which the motherboard controller sends calibration control information to any backplane controller, such as the first time period described above.

According to the calibration method described above by way of example, the phase difference Δ P between indicator light flicker frequency division counters among a plurality of backplane controllers in an electronic system is very small, for example, microsecond-level phase difference, so that visual effects of flicker states of a plurality of corresponding indicator lights are kept consistent, and thus, when hardware operating states to be indicated by the plurality of indicator lights are consistent, the flicker states of the plurality of indicator lights are consistent, thereby avoiding inconsistency of flicker states under the condition and causing interference to work of a user viewing the hardware operating states.

Referring to fig. 8, which is a schematic flow chart of yet another optional example of the backplane controller method proposed in the present application, this embodiment may be an optional detailed implementation method of the calibration control information obtaining process described in the foregoing embodiment, and therefore, the backplane control method of this embodiment may be executed by a motherboard controller, as shown in fig. 8, the motherboard controller may obtain the calibration control information of each backplane controller according to, but not limited to, the following steps:

step S81, generating a motherboard clock signal having a second time period;

step S82, in each first time period, sequentially determining a plurality of calibration timestamps on the motherboard clock signal, and determining a polarity state of the motherboard clock signal corresponding to each of the plurality of calibration timestamps;

step S83, when any calibration timestamp is determined, sending the determined calibration timestamp and the polarity state of the motherboard clock pulse corresponding to the calibration timestamp to any backplane controller that is not calibrated in the first time period.

In conjunction with the description of the corresponding parts of the above embodiments, the first time period may be a time period when the motherboard controller generates calibration control information for the same backplane controller, as indicated by T in fig. 7. Since the implementation process of generating any calibration control information by the motherboard controller is similar in each first time period, the embodiment is described by taking an example of an acquisition process of generating the calibration control information required by each backplane controller in only one first time period, and for the acquisition process of the calibration control information in other subsequent first time periods, reference may be made to the description of the embodiment, and details of the embodiment are not described herein.

Referring to the above process of acquiring calibration control information shown in fig. 7, in each T, the motherboard controller takes each determined calibration time (e.g., time T1, time T2, etc.) as a calibration timestamp, and writes the calibration timestamp and the polarity status of the corresponding motherboard clock pulse to the backplane controller at that time. Since this embodiment is implemented by sequentially writing calibration control information into a plurality of backplane controllers, the calibration control information corresponding to each backplane controller is received at different times. In order to avoid that the same backplane controller repeatedly receives calibration control information, the backplane controllers which send the calibration control information can be marked by the main board controller in the current first time period, so that when the calibration control information is sent, the calibration control information obtained this time can be sent to any backplane controller which is not calibrated (i.e. not received) in the first time period according to the recorded marking information in the first time period.

It should be noted that, in the present application, there is no limitation on the marking method and content for whether each backplane controller receives the calibration control information in each first time period, which may be determined as the case may be. Moreover, the first time periods for determining the calibration control information corresponding to each of the backplane controllers may be the same (as described in this embodiment), or may be different.

As to how to implement the process of calibrating the phase of the clock pulse (which may be referred to as a backplane clock pulse) output by a plurality of backplane controllers in an electronic system after the plurality of backplane controllers receive calibration control information, such as the calibration timestamp and the polarity state of the corresponding motherboard clock pulse, reference may be made to the description of the corresponding part of the above embodiment, which is not described herein again in this embodiment of the present application.

Referring to fig. 9, which is a schematic flowchart of a further optional example of the backplane controller method proposed in the present application, this embodiment may be a further optional detailed implementation method of the calibration control information acquisition process described in distinction from the foregoing embodiment, and as shown in fig. 9, the method may include:

step S91, generating a motherboard clock signal having a second time period;

step S92, in each first time period, generating a matched calibration timestamp by any mainboard time generated by the mainboard clock signal, and determining the polarity state of the mainboard time signal at the mainboard time;

for specific implementation processes of step S91 and step S92, reference may be made to the description of corresponding parts in the foregoing embodiments, which are not described herein again.

Step S93, when determining the calibration timestamp, sending the calibration timestamp and the polarity status of the motherboard clock pulse corresponding to the calibration timestamp to the backplane controllers, respectively.

It can be seen that, different from the manner in which the motherboard controller sequentially sends the calibration control information to the plurality of backplane controllers described in the above embodiments, this embodiment provides an implementation manner in which the motherboard controller simultaneously sends the calibration control information to the plurality of backplane controllers, and in this case, it is not necessary to obtain the plurality of calibration control information, and it is sufficient to directly write the calibration control information into respective registers of the plurality of backplane controllers simultaneously, and detailed details are not given in this application.

It can be understood that, in the case that system resources of the computer device are sufficient, the implementation manner of sending the calibration control information to the plurality of backplane controllers simultaneously according to the embodiment of the present application can improve calibration efficiency.

Based on the backplane control method described in each of the above embodiments, before the motherboard controller obtains the calibration control information, the present application may further detect whether the calibration control information is reliable, that is, whether phase calibration of the clock pulse output by the backplane controller can be implemented, and if not, the calibration control information may be sent without occupying system resources. Therefore, referring to fig. 10, a signaling flow diagram of still another alternative example of the backplane controller method proposed in the present application is shown, as shown in fig. 10, the method may include:

step S101, the mainboard controller generates a mainboard clock signal with a second time period

Step S102, the mainboard controller determines calibration control information corresponding to each of the plurality of backboard controllers based on the mainboard clock signal;

wherein, calibration control information can include the calibration timestamp to and the polarity state that this calibration timestamp corresponds mainboard clock signal, namely the mainboard controller is at the mainboard clock pulse's of this calibration timestamp output polarity state, specifically can represent the polarity state that this calibration timestamp corresponds mainboard clock signal by this mainboard clock pulse, consequently, above-mentioned calibration control information can include calibration timestamp and the mainboard clock pulse that corresponds.

For specific implementation processes of step S101 and step S102, reference may be made to descriptions of corresponding parts in the foregoing embodiments, which are not described herein again.

Step S103, the main board controller detects whether the calibration control information meets the calibration condition, if so, the step S104 is carried out, and if not, the step S105 is carried out;

in combination with the above analysis, the calibration condition may include that the motherboard clock pulse included in the calibration control information is an inverted polarity pulse, that is, the polarity state of the motherboard clock signal included in the calibration control information determined this time is different from the polarity state of the motherboard clock signal determined last time. Based on this, step S103 may specifically include: for the same backplane controller, detecting whether the polarity state of the motherboard clock signal included in the calibration control information determined this time is the same as the polarity state of the motherboard clock signal determined last time, that is, detecting whether the motherboard clock pulse in the calibration control information is a polarity inversion pulse, and the like, and the application does not limit the specific implementation method of step S103.

Step S104, the mainboard controller sends the determined calibration control information to the corresponding backboard controller at the mainboard time of the calibration timestamp;

in still other embodiments, after the backplane controller receives the calibration control information, the application may execute step S103, and perform phase calibration on the clock pulse output by the backplane controller based on the calibration control information when it is determined that the calibration condition is satisfied. It can be seen that, the application does not limit the execution stage of the whole backplane control method in step S103, and the execution stage may be determined according to the situation.

In step S105, the plurality of backplane controllers continue to operate according to their respective backplane clock signals.

Still referring to the calibration scenario shown in fig. 7 as an example, since the corresponding motherboard clock pulse is not a polarity inversion pulse in the calibration control information determined at the time t3 and the time t4 by the motherboard controller, even if the calibration control information at the time is sent to the backplane controller, the indicator light blinking frequency division counter inside the backplane controller is not calibrated.

Therefore, in this embodiment, it may be first detected whether the determined calibration control information meets the calibration condition, and the process may be implemented during the determination of the calibration control information, mainly when the polarity state of the motherboard clock pulse is determined, that is, the step S103 may be executed simultaneously with the step S102, so that, when the detection result is not satisfied, the calibration control information may be written into the register of the corresponding backplane controller without occupying data transmission resources, and meanwhile, the storage resources of the backplane controller are also saved, thereby ensuring that the calibration control information sent to each backplane controller is valid information, that is, the phase calibration information of the clock pulse output by the corresponding backplane controller can be reliably implemented, and the reliability of each backplane controller in responding to the calibration control information is improved.

Referring to fig. 11, which is a schematic structural diagram of an optional example of the backplane control apparatus provided in the present application, the apparatus may be applied to an electronic system having a plurality of backplane controllers, and for connection relationships between the plurality of backplane controllers and other devices in the electronic system, such as a motherboard controller, an indicator light, and the like, reference may be made to descriptions of corresponding parts in the foregoing embodiments, which are not described in detail herein in this embodiment. It should be noted that the backplane control apparatus provided in this embodiment is specifically applicable to any backplane controller, as shown in fig. 11, the backplane control apparatus may include:

a calibration control information receiving module 211, configured to receive calibration control information sent by a motherboard controller, where the calibration control information is determined according to a first time period;

a calibration processing module 212, configured to perform phase calibration on the clock pulses output by the backplane controller based on the calibration control information, so as to reduce phase differences between the clock pulses output by the plurality of backplane controllers;

and the indicator light control module 213 is configured to obtain a control signal of the corresponding indicator light by using the clock pulse after the phase calibration, where the control signal is used to control a display state change of the indicator light arranged on the back panel where the back panel controller is located.

In some embodiments, as shown in fig. 12, in order for the motherboard controller to obtain the calibration control information, the backplane control apparatus may further include the following modules adapted to the motherboard controller:

a motherboard clock signal generating module 111, configured to generate a motherboard clock signal with a second time period;

a calibration control information determining module 112, configured to determine, based on the motherboard clock signal, calibration control information corresponding to each of the plurality of backplane controllers; the calibration control information comprises a calibration timestamp, and the calibration timestamp corresponds to the polarity state of the mainboard clock signal;

a calibration control information sending module 113, configured to send the determined calibration control information to a corresponding backplane controller at the time of the motherboard where the calibration timestamp is located;

wherein the second time period is greater than the first time period.

In a possible implementation manner, the calibration control information determining module 112 may include:

a first determining unit, configured to sequentially determine, in each first time period, a plurality of calibration timestamps on the motherboard clock signal, and a polarity state of the motherboard clock signal corresponding to each of the plurality of calibration timestamps;

based on this, the calibration control information sending module 113 may include:

and the first sending unit is configured to send the determined calibration timestamp and the polarity state of the motherboard clock pulse corresponding to the calibration timestamp to any one of the backplane controllers that is not calibrated in the first time period when any one of the calibration timestamps is determined.

In another possible implementation manner, the calibration control information determining module 112 may also include:

a second determining unit, configured to generate a matching calibration timestamp from any motherboard time generated by the motherboard clock signal in each of the first time periods, and determine a polarity state of the motherboard time signal at the motherboard time;

based on this, the calibration control information transmitting module 113 may further include:

and the second sending unit is used for sending the calibration timestamp and the polarity state of the mainboard clock pulse corresponding to the calibration timestamp to the plurality of backplane controllers respectively when the calibration timestamp is determined.

In still other embodiments, the first time periods for determining the calibration control information corresponding to each of the backplane controllers may be the same or different, as the case may be.

Based on the above description of the present embodiment, the calibration processing module 212 in the backplane controller may include:

the first calibration unit is used for updating the counting time of the backboard controller for clock pulses according to the calibration timestamp to calibrate the backboard clock signal of the backboard controller under the condition that the polarity state of the mainboard clock signal received this time is determined to be different from the polarity state of the mainboard clock signal received last time;

and the first trigger unit is used for continuing to work according to the backboard clock signal of the backboard controller under the condition that the polarity state of the mainboard clock signal received this time is determined to be the same as the polarity state of the mainboard clock signal received last time.

In still other embodiments, based on the description of the foregoing embodiments, the backplane control device provided in the present application may further include:

a detection module, configured to detect whether the calibration control information meets a calibration condition, and if the calibration condition is met, trigger the calibration control information sending module 113 to send the determined calibration control information to the corresponding backplane controller at the time of the motherboard where the calibration timestamp is located, or trigger the calibration processing module 212 to perform phase calibration on the clock pulse output by the backplane controller based on the calibration control information.

In a possible implementation manner, the detection module may include:

the detection unit is used for detecting whether the polarity state of the mainboard clock signal contained in the calibration control information determined this time is the same as the polarity state of the mainboard clock signal determined last time or not aiming at the same backboard controller;

accordingly, the condition that the calibration condition is satisfied is that a polarity state of the motherboard clock signal included in the calibration control information determined this time is different from a polarity state of the motherboard clock signal determined this time last time.

And the trigger module is used for continuously working according to respective backboard clock signals by the plurality of backboard controllers under the condition that the detection result of the detection module is negative.

It should be noted that, various modules, units, and the like in the embodiments of the foregoing apparatuses may be stored in corresponding memories as program modules, and the processor executes the program modules stored in the memories to implement corresponding functions, and for the functions implemented by the program modules and the combinations thereof and the achieved technical effects, reference may be made to the description of corresponding parts in the embodiments of the foregoing methods, which is not described in detail in this embodiment.

The present application further provides a computer-readable storage medium, on which a computer program may be stored, where the computer program may be called and loaded by a motherboard controller or a backplane controller, so as to implement the steps of the backplane control method described in the foregoing embodiments from the corresponding sides.

Finally, it should be noted that, in the present specification, the embodiments are described in a progressive or parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device and the computer equipment disclosed by the embodiment correspond to the method disclosed by the embodiment, so that the description is relatively simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A backplane control method adapted for use in an electronic system having a plurality of backplane controllers, the method comprising:

2. The method of claim 1, the obtaining of the calibration control information comprising:

the mainboard controller determines calibration control information corresponding to the plurality of backboard controllers based on the mainboard clock signal; the calibration control information comprises a calibration timestamp, and the calibration timestamp corresponds to the polarity state of the mainboard clock signal;

wherein the second time period is greater than the first time period.

3. The method of claim 2, the motherboard controller determining calibration control information corresponding to each of the plurality of backplane controllers based on the motherboard clock signal, comprising:

4. The method of claim 2, the motherboard controller determining calibration control information corresponding to each of the plurality of backplane controllers based on the motherboard clock signal, comprising:

5. The method of claim 2, the first time period of the determining calibration control information for each of the plurality of backplane controllers is different.

6. The method according to any one of claims 2 to 5, wherein the phase calibration of the clock pulse output by the backplane controller based on the calibration control information comprises:

7. The method of any of claims 2-5, further comprising:

8. The method of claim 7, the detecting whether the calibration control information satisfies a calibration condition, comprising:

9. A backplane control apparatus adapted for use in an electronic system having a plurality of backplane controllers, the apparatus comprising:

10. A computer device, the computer device comprising

the back plates are provided with back plate controllers and indicator lamps;

receiving the calibration control information sent by the mainboard controller;