WO2021238276A1

WO2021238276A1 - Electric leakage detection method and apparatus for cpld

Info

Publication number: WO2021238276A1
Application number: PCT/CN2021/073496
Authority: WO
Inventors: 谢武志
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2020-05-27
Filing date: 2021-01-25
Publication date: 2021-12-02
Also published as: CN111707966A

Abstract

An electric leakage detection method for a CPLD, comprising: a CPLD controls a power chip to stop outputting voltage, and records a first output voltage value of the power chip (S1); set all output pins of the CPLD to high impedance, and record a second output voltage value of the power chip (S2); compare whether the first output voltage value is consistent with the second output voltage value (S3); if the first output voltage value is not consistent with the second output voltage value, sequentially and separately restore N output pins of the CPLD from a high impedance state to a pre-working state; according to the comparison between recorded N third output voltage values of the restored power chip and the second output voltage value, determine whether electric leakage occurs at the output pins of the CPLD. Also provided is an electric leakage detection apparatus for a CPLD. The present invention improves the efficiency of solving an electric leakage problem of a server, distinguishes whether the electric leakage problem of the server is caused by the output pins of the CPLD, and specifically positions which one of the output pins of the CPLD has electric leakage, thereby having a good positioning effect.

Description

A CPLD leakage detection method and device

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on May 27, 2020, the application number is 202010460586.5, and the invention title is "a method and device for CPLD leakage detection", the entire content of which is incorporated herein by reference Applying.

Technical field

The present invention relates to the field of leakage detection design, in particular to a method and device for leakage detection of CPLD.

Background technique

In the era of information explosion, the role of servers is becoming more and more important. Whether it is AI acceleration, data analysis of large databases, Internet of Things and other applications, the application level of these software development needs hardware to support. In the development stage of the server, a large number of test verifications are required to meet various required test conditions, and leakage detection is also one of the test verifications.

In the traditional method of testing leakage, most engineers directly measure each voltage. If the VR (voltage conversion chip) voltage is found to be output abnormally when it is not powered on, it needs to be analyzed to see if there is a problem. , Disconnect for the question point, and then measure whether there is improvement. Repeat this until the measured voltage reaches the normal range value, and then the leakage problem can be found.

As shown in Figure 1, the power supply of the entire server is provided by the PDB board (power distribution board), and then the power chip on the power distribution board performs voltage conversion to provide various voltages to meet the needs of the chip. Most of the control switches of all power chips are controlled by CPLD (Complex Programmable Logic Device, programmable logic device). According to the power-on sequence provided by the microprocessor (CPU or GPU), the power of the power chip is turned on in sequence. The leakage situation is that when the power chip is not turned on, the output voltage of the power chip (Power IC) is measured to be an abnormal voltage. For example, if P12V_MAIN is not turned on, the output of P12V_MAIN measures 2V, as shown in Figure 2.

There are many reasons for leakage. Among them, when the CPLD is outputting the output pin, the output recharge is caused by a definition error at a certain point in time, which is also one of the common. Figure 3 is a schematic diagram of the CPLD pin connection on the server. Since the server system is very large, which node causes the leakage, or the output pin leakage of the CPLD itself, in the existing method, engineers need to give the circuit of the problem point one by one. Disconnect it, and then measure whether there is any leakage. If there is still a problem, continue to disconnect other doubtful points. Repeat this until the leakage phenomenon is improved, and when the circuit is disconnected, the risk of chip (IC) damage or solder joints falling off will be caused by carelessness, which is not conducive to the rapid and efficient solution of the server leakage problem.

Summary of the invention

In order to solve the problems in the prior art, the present invention innovatively proposes a CPLD leakage detection method and device, which effectively solves the problem of high leakage detection risk and low efficiency due to engineers disconnecting the circuit of the problem point one by one for measurement. , Effectively improve the efficiency of the server leakage problem.

The first aspect of the present invention provides a CPLD leakage detection method, including:

CPLD controls the power chip to stop outputting voltage, and records the first output voltage value of the power chip;

Set all output pins of the CPLD to high impedance, and record the second output voltage value of the power chip;

Compare whether the first output voltage value is consistent with the second output voltage value. If they are the same, none of the CPLD output pins will leak; if they are inconsistent, the N output pins of the CPLD will be individually restored from the high impedance state to the pre-working state in turn , Record the N third output voltage values of the restored power chip in sequence, and compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent. If they are consistent, the corresponding CPLD output The pins have no leakage. If they are inconsistent, the output pin of the corresponding CPLD is leakage, where N is a positive integer.

Optionally, restoring the N output pins of the CPLD individually from the high impedance state to the pre-working state in turn, and respectively sequentially recording the restored N third output voltage values of the power chip specifically includes:

Restore the first output pin of the CPLD from the high impedance state to the pre-working state, record the corresponding first third output voltage value of the restored power chip, and reset the first output pin of the CPLD to the high impedance state ；

Restore the second output pin of the CPLD from the high impedance state to the pre-working state, record the second and third output voltage values of the restored power chip, and reset the second output pin of the CPLD to the high impedance state ；

Until the Nth output pin of the CPLD is restored from the high impedance state to the pre-working state, record the corresponding Nth third output voltage value of the restored power chip, and reset the Nth output pin of the CPLD to high impedance state.

Optionally, the first output voltage value, the second output voltage value, and the N third output voltage values are all recorded by the ADC inside the CPLD.

Further, it also includes: the CPLD sends the internal ADC record data to the background through the URAT interface.

Optionally, the CPLD controlling the power chip to stop outputting voltage is specifically an enable signal for the CPLD to turn off the power chip through an internal VR control module.

Optionally, setting all output pins of the CPLD to high impedance, and restoring the N output pins of the CPLD from the high impedance state to the pre-working state individually in turn are all implemented through the IO management module inside the CPLD.

The second aspect of the present invention provides a CPLD leakage detection device, including:

The first recording unit, the CPLD controls the power chip to stop outputting voltage, and records the first output voltage value of the power chip;

The second recording unit sets all output pins of the CPLD to high impedance, and records the second output voltage value of the power chip;

The comparison unit compares whether the first output voltage value is consistent with the second output voltage value. If they are the same, none of the CPLD output pins will leak; if they are inconsistent, the N output pins of the CPLD will be individually restored from the high impedance state in turn In the pre-working state, record the N third output voltage values of the restored power chip in sequence, and compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent. If they are consistent, the corresponding The output pin of the CPLD has no leakage. If it is inconsistent, the output pin of the corresponding CPLD has leakage, where N is a positive integer.

Optionally, it further includes: a data sending unit, where the CPLD sends the internal ADC record data to the background through the URAT interface.

The technical scheme adopted by the present invention includes the following technical effects:

1. The present invention effectively solves the problem of high leakage detection risk and low efficiency due to engineers disconnecting the circuit of the problem point one by one for measurement, and effectively improves the efficiency of the server leakage problem.

2. The technical solution of the present invention distinguishes whether the server leakage problem is caused by the output pin of the CPLD itself, and further locates which output pin of the CPLD is caused by the specific output pin, and the positioning effect is better.

3. In the technical scheme of the present invention, the first output voltage value, the second output voltage value, and the N third output voltage values are uniformly recorded by the ADC inside the CPLD, which avoids the problem of low detection efficiency due to separate recording and improves detection efficient.

4. In the technical scheme of the present invention, the CPLD sends the internal ADC record data to the background through the URAT interface, which is convenient for the background to monitor the leakage of each output pin of the CPLD.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, Without creative work, other drawings can be obtained based on these drawings.

Fig. 1 is a schematic diagram of power supply for a server power distribution board in the prior art;

Figure 2 is a schematic diagram of leakage detection of a server power chip in the prior art;

FIG. 3 is a schematic diagram of the connection of the CPLD chip in the server in the prior art;

Fig. 4 is a schematic flow chart of the method of Example 1 in the scheme of the present invention;

5 is a schematic diagram of the hardware architecture of CPLD self-detection in the first embodiment of the scheme of the present invention;

6 is a schematic flowchart of step S5 in the method of Example 1 in the solution of the present invention;

Fig. 7 is a schematic flow chart of the method of Example 2 in the scheme of the present invention;

8 is a schematic diagram of the hardware architecture of the CPLD self-detection in the second embodiment of the solution of the present invention;

FIG. 9 is a schematic diagram of the structure of the device of Example 3 in the scheme of the present invention;

Fig. 10 is a schematic diagram of the structure of the device of Example 4 in the scheme of the present invention.

Detailed ways

In order to clearly illustrate the technical characteristics of the present solution, the present invention will be described in detail below through specific implementations and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. In addition, the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or settings discussed. It should be noted that the components illustrated in the drawings are not necessarily drawn to scale. The present invention omits descriptions of well-known components and processing techniques and processes to avoid unnecessarily limiting the present invention.

Example one

As shown in Figure 4, the present invention provides a CPLD leakage detection method, including:

S1, CPLD controls the power chip to stop outputting voltage, and records the first output voltage value of the power chip;

S2: Set all output pins of the CPLD to high impedance, and record the second output voltage value of the power chip;

S3, compare whether the first output voltage value is consistent with the second output voltage value, if the judgment result is yes, then step S4 is executed; if the judgment result is no, then step S5 is executed;

S4, the CPLD output pins are not leaking;

S5, restore the N output pins of the CPLD from the high impedance state to the pre-working state individually in turn, and respectively record the restored N third output voltage values of the power chip after the restoration, where N is a positive integer;

S6, compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent, if the judgment result is yes, then execute step S7; if the judgment result is no, then execute step S8;

S7, the output pin of the corresponding CPLD has no leakage;

S8, the output pin of the corresponding CPLD is leaking.

As shown in Figure 5, it is the basic hardware architecture of the CPLD in the present invention. The CPLD includes a VR control module (VR Control), ADC (Analog-to-digital converter, analog-to-digital converter), and a self-checking process control module (Self- test flow Control), IO management module (I/O Management), the CPLD turns off the enable signal of the power chip (Power IC) through the internal VR control module, so that the power chip stops outputting the voltage; the IO management module inside the CPLD can set the CPLD’s All output pins are set to high impedance and the N output pins of the CPLD are individually restored from the high impedance state to the pre-working state in turn; the first output voltage value, the second output voltage value, and the N third output voltage values all pass The ADC record inside the CPLD; the self-detection process control module realizes the control of the CPLD's entire leakage detection test process, including but not limited to the sending and receiving of commands.

As shown in Fig. 6, step S5 specifically includes:

S51. Restore the nth output pin of the CPLD from the high impedance state to the pre-working state, record the corresponding nth third output voltage value of the restored power chip, and reset the nth output pin of the CPLD to high Impedance state, where n is a positive integer less than or equal to N, and the initial value is 1;

S52, judge whether the nth output pin of the CPLD is the Nth output pin of the CPLD, if the judgment result is yes, then execute step S53, if the judgment result is no, then execute step S54;

S53, the setting of all output pins of the CPLD is completed, and step S6 is executed;

S54: Restore the n+1th output pin of the CPLD from the high impedance state to the pre-working state, record the n+1th third output voltage value of the restored power chip, and output the n+1th CPLD The pin is reset to a high impedance state, and step S52 is continued.

In steps S51-S54, the purpose is to sequentially restore all the N output pins of the CPLD and record the corresponding third output voltage value to facilitate the data comparison in step S6.

In order to explain the technical solution of this embodiment more clearly, an example is given, and the details are as follows:

The CPLD controls the power chip to stop the output voltage, and records the first output voltage value of the power chip. The first output voltage value is the voltage value at the time of leakage. At this time, the output pins of the CPLD are in the normal working state (normal output). For example, the power chip P1V8 has 1V leakage;

Set all the output pins of the CPLD to high impedance, record the second output voltage value of the power chip P1V8, at this moment the power chip P1V8 stops outputting the voltage, and compare whether the first output voltage value is consistent with the second output voltage value, if they are consistent , That is, the second output voltage value is still 1V, the leakage is caused by other devices, not the output pin of the CPLD itself; if it is inconsistent, the second output voltage value becomes 0.2V, indicating that the leakage phenomenon has been improved , It can be determined that the leakage is caused by the output pin of the CPLD;

The N output pins of the CPLD are individually restored from the high impedance state to the pre-operating state in turn, and the N third output voltage values of the restored power chip P1V8 are recorded in sequence, and the N third output voltage values are sequentially compared with the first Compare the two output voltage values to see if they are consistent. If a third output voltage value is consistent with the second output voltage value, that is, it is still less than 0.2V, it means that the corresponding output pin has no leakage; if a third output voltage value is Inconsistent with the second output voltage value, that is, 0.1V or 0.3V, etc., it indicates that the corresponding output pin is leaking.

The invention effectively solves the problems of high leakage detection risk and low efficiency caused by the engineers disconnecting the circuits of the problem points one by one for measurement, and effectively improves the efficiency of the server leakage problem.

The technical scheme of the present invention distinguishes whether the server leakage problem is caused by the output pin of the CPLD itself, and further locates which output pin of the CPLD is caused by the specific output pin, and the positioning effect is better.

In the technical scheme of the present invention, the first output voltage value, the second output voltage value, and the N third output voltage values are uniformly recorded by the ADC inside the CPLD, which avoids the problem of low detection efficiency caused by separate recording and improves the detection efficiency.

Example two

As shown in Figure 7, the present invention provides a CPLD leakage detection method, including:

S4, the CPLD output pins are not leaking;

S7, the output pin of the corresponding CPLD has no leakage;

S8, the output pin of the corresponding CPLD is leaking;

S9, the CPLD sends the internal ADC record data to the background through the URAT interface.

As shown in Figure 8, it is the basic hardware architecture of the CPLD in the present invention. The CPLD includes a VR control module (VR Control), ADC (Analog-to-digital converter, analog-to-digital converter), and a self-checking process control module (Self- test flow Control), IO management module (I/O Management), RAM, URAT interface (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver/Transmitter) control module (URAT Control), CPLD turns off the power chip (Power IC) through the internal VR control module ) Enables the power chip to stop the output voltage; the IO management module inside the CPLD can set all the output pins of the CPLD to high impedance and restore the N output pins of the CPLD individually from the high impedance state to pre-work in turn Status: The first output voltage value, the second output voltage value, and the N third output voltage values are all recorded by the ADC inside the CPLD. The self-detection process control module realizes the control of the CPLD's entire leakage detection test process, including but not limited to the sending and receiving of commands; RAM will record the data (first output voltage value, second output voltage value, Nth Three output voltage values) are stored and sent to the background through the URAT interface control module.

In the technical scheme of the present invention, the CPLD sends the internal ADC record data to the background through the URAT interface, which is convenient for the background to monitor the leakage of each output pin of the CPLD.

Example three

As shown in Figure 9, the technical solution of the present invention also provides a CPLD leakage detection device, including:

The first recording unit 101, the CPLD controls the power chip to stop outputting voltage, and records the first output voltage value of the power chip;

The second recording unit 102 sets all output pins of the CPLD to high impedance, and records the second output voltage value of the power chip;

The comparison unit 103 compares whether the first output voltage value is consistent with the second output voltage value. If they are the same, none of the CPLD output pins will leak; if they are inconsistent, the N output pins of the CPLD are individually switched from high impedance states in turn Restore to the pre-working state, respectively record the N third output voltage values of the restored power chip in sequence, and compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent. If they are consistent, then The output pin of the corresponding CPLD has no leakage. If it is inconsistent, the output pin of the corresponding CPLD is leakage, where N is a positive integer.

Further, the first output voltage value, the second output voltage value, and the N third output voltage values are all recorded by the ADC inside the CPLD.

Embodiment four

As shown in Figure 10, the technical solution of the present invention also provides a CPLD leakage detection device, including:

The comparison unit 103 compares whether the first output voltage value is consistent with the second output voltage value. If they are the same, none of the CPLD output pins will leak; if they are inconsistent, the N output pins of the CPLD are individually switched from high impedance state in turn Restore to the pre-working state, respectively record the N third output voltage values of the restored power chip in sequence, and compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent. If they are consistent, then The output pin of the corresponding CPLD has no leakage. If it is inconsistent, the output pin of the corresponding CPLD is leakage, where N is a positive integer.

In the data sending unit 104, the CPLD sends the internal ADC record data to the background through the URAT interface.

Although the specific embodiments of the present invention are described above in conjunction with the accompanying drawings, they are not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that on the basis of the technical solutions of the present invention, those skilled in the art do not need to make creative efforts. Various modifications or variations that can be made are still within the protection scope of the present invention.

Claims

A CPLD leakage detection method, which is characterized in that it includes:

CPLD controls the power chip to stop outputting voltage, and records the first output voltage value of the power chip;

Set all output pins of the CPLD to high impedance, and record the second output voltage value of the power chip;

Compare whether the first output voltage value is consistent with the second output voltage value. If they are the same, none of the CPLD output pins will leak; if they are inconsistent, the N output pins of the CPLD will be individually restored from the high impedance state to the pre-working state in turn , Record the N third output voltage values of the restored power chip in sequence, and compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent. If they are consistent, the corresponding CPLD output The pins have no leakage. If they are inconsistent, the output pin of the corresponding CPLD is leakage, where N is a positive integer.
The CPLD leakage detection method according to claim 1, characterized in that the N output pins of the CPLD are individually restored from the high impedance state to the pre-working state in sequence, and the N third output pins of the restored power chip are recorded in sequence. The output voltage values specifically include:

Restore the first output pin of the CPLD from the high impedance state to the pre-working state, record the corresponding first third output voltage value of the restored power chip, and reset the first output pin of the CPLD to the high impedance state ；

Restore the second output pin of the CPLD from the high impedance state to the pre-working state, record the second and third output voltage values of the restored power chip, and reset the second output pin of the CPLD to the high impedance state ；

Until the Nth output pin of the CPLD is restored from the high impedance state to the pre-working state, record the corresponding Nth third output voltage value of the restored power chip, and reset the Nth output pin of the CPLD to high impedance state.
The CPLD leakage detection method according to claim 1, wherein the first output voltage value, the second output voltage value, and the N third output voltage values are all recorded by the ADC inside the CPLD.
The CPLD leakage detection method according to claim 3, further comprising: the CPLD sends the internal ADC record data to the background through the URAT interface.
The CPLD leakage detection method according to claim 1, wherein the CPLD controlling the power chip to stop outputting voltage is specifically an enable signal for the CPLD to turn off the power chip through an internal VR control module.
The CPLD leakage detection method according to claim 1, wherein all the output pins of the CPLD are set to high impedance, and the N output pins of the CPLD are individually restored from the high impedance state to the pre-working state. Realized through the IO management module inside the CPLD.
A CPLD leakage detection device, which is characterized in that it includes:

The first recording unit, the CPLD controls the power chip to stop outputting voltage, and records the first output voltage value of the power chip;

The second recording unit sets all output pins of the CPLD to high impedance, and records the second output voltage value of the power chip;

The comparison unit compares whether the first output voltage value is consistent with the second output voltage value. If they are the same, the CPLD output pins are not leaking; if they are not consistent, the N output pins of the CPLD are individually switched to high impedance state in turn Restore to the pre-working state, respectively record the N third output voltage values of the restored power chip in sequence, and compare the N third output voltage values with the second output voltage values in sequence to see if they are consistent. If they are consistent, then The output pin of the corresponding CPLD has no leakage. If it is inconsistent, the output pin of the corresponding CPLD is leakage, where N is a positive integer.
The CPLD leakage detection device according to claim 7, wherein the first output voltage value, the second output voltage value, and the N third output voltage values are all recorded by the ADC inside the CPLD.
The CPLD leakage detection device according to claim 8, further comprising: a data sending unit, the CPLD sends the internal ADC record data to the background through the URAT interface.