CN110796975A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110796975A CN110796975A CN201911168213.4A CN201911168213A CN110796975A CN 110796975 A CN110796975 A CN 110796975A CN 201911168213 A CN201911168213 A CN 201911168213A CN 110796975 A CN110796975 A CN 110796975A
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- transistor
- display panel
- test pad
- electrically connected
- finger area
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- 238000012360 testing method Methods 0.000 claims abstract description 75
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 23
- 239000010931 gold Substances 0.000 claims description 23
- 229910052737 gold Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 239000010408 film Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Abstract
The invention discloses a display panel and a display device. The invention realizes the electrical connection with the grid electrode of the transistor by arranging the at least one test pad on the chip on film and the printed circuit board and by the routing connected to the golden finger area, thereby being capable of simply, quickly and accurately testing the grid electrode waveform of the transistor output to the display panel by the GOA circuit of the display panel, improving the development efficiency and improving the product reliability.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
With the gradual improvement of the maturity of liquid crystal panel design, the narrow frame and low cost become more and more the main consideration factors of panel design. The goa (gate Driver on array) design of the panel can meet the customer's requirements for narrow bezel and low cost. The GOA technology directly manufactures the gate scan driving circuit of the thin film transistor on the display substrate, so as to save the scan driving chip, reduce the Bonding time, and reduce the usage of Anisotropic Conductive Film (ACF). In order to realize the integration of scanning drive on a glass substrate array, a time schedule controller is required to provide signals such as a frame start signal STV, field shift pulse signals CKV 1-2N (N is more than or equal to 1), and the levels of an analog grounding voltage VSSD and an analog working voltage VDDD are converted into a gate-off voltage VGL and a gate-on voltage VGH through a Level Shifter (Level Shifter). However, waveforms of transistors of the display panel to turn on and off when the GOA circuit is input to the display panel cannot be simply and rapidly measured and obtained, and risk situations such as performance of the GOA circuit and performance of GOA output waveforms in the panel cannot be rapidly judged in the early stage, so that errors occur in the later stage of a project and precious development time is wasted.
In order to eliminate risks related to the GOA circuit as much as possible, the conventional scheme is to test the timing sequence of external control signals such as STV and CK output from a timing controller to the inside (or in plane for short, the same hereinafter) of a display panel, and then simulate the output waveform of the GOA circuit through software, or indirectly test the output waveform of the GOA circuit by performing laser bridging on a line in the plane. The analog simulation parameters are different from the parameters and environment parameters during the actual panel GOA circuit period, and the real output waveform of the GOA circuit cannot be obtained. Through laser bridging mode, often need carry out the lobe of a leaf to the liquid crystal box and look for laser point location under high power microscope, consume more manpower and need high-end equipment. The success rate is relatively low, the effect of the laser point location cannot be guaranteed, and the output result has large difference. Above, there are uncontrollable factors that make it impossible to obtain accurate data.
Therefore, how to simply, rapidly and accurately test the gate waveforms outputted from the GOA circuit of the display panel to the transistors in the display panel is an important issue in the display technology.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, wherein at least one test pad is arranged on a chip on film and a printed circuit board, and the test pad is electrically connected with a grid of a transistor through a wire connected to a golden finger area, so that the waveform of the grid of the transistor output to the display panel by a GOA circuit of the display panel can be simply, quickly and accurately tested, the development efficiency is improved, and the product reliability is improved.
According to an aspect of the present invention, there is provided a display panel including: a printed circuit board provided with a first golden finger area; the chip on film is provided with a second golden finger area and at least one test pad, wherein the at least one test pad of the chip on film is electrically connected with the second golden finger area; the substrate wire area is provided with at least one wire and a plurality of substrate wires, wherein the at least one wire is electrically connected with the first golden finger area and the second golden finger area; the scanning driving circuit comprises a plurality of scanning lines, and each scanning line is electrically connected with each corresponding substrate lead; and a plurality of cascaded GOA units, wherein the plurality of GOA units in the first row comprise at least one transistor, the grid electrode of the at least one transistor is connected to the second golden finger area through the at least one wire, and the grid electrode of the at least one transistor is electrically connected with the at least one test pad of the chip on film.
Furthermore, a time schedule controller, a level shifter and a power switch are arranged on the printed circuit board, wherein the level shifter is electrically connected with the time schedule controller and the power switch respectively.
Further, the timing controller is used for providing control signals, and the control signals comprise a frame start signal and a field displacement pulse signal.
Further, the level shifter is used for converting the levels of the analog grounding voltage and the analog working voltage into a gate-off voltage and a gate-on voltage.
Further, the power switch is used for turning on or off the level shifter.
Furthermore, the printed circuit board is provided with at least one test pad, and the at least one test pad of the printed circuit board is electrically connected with the first golden finger area.
Further, at least one test pad of the printed circuit board is electrically connected with the gate of the at least one transistor through the at least one trace connected to the first gold finger area.
Further, the at least one transistor includes a first transistor, a second transistor, and a third transistor.
Further, the first transistor is located at the left of the first row of the plurality of GOA cells, the second transistor is located at the middle of the first row of the plurality of GOA cells, and the third transistor is located at the right of the first row of the plurality of GOA cells.
According to another aspect of the present invention, there is provided a display device including any one of the display panels described above.
According to the embodiment of the invention, at least one test pad is arranged on the chip on film and the printed circuit board, and the test pad is electrically connected with the grid of the transistor through the wiring connected to the golden finger area, so that the grid waveform of the transistor output from the GOA circuit of the display panel to the display panel can be simply, quickly and accurately tested, the development efficiency is improved, and the product reliability is improved.
Drawings
The technical solution and the advantages of the present invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In particular embodiments, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. Further, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements.
The terminology used in the detailed description is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it is to be understood that terms such as "comprising," "having," and "containing" are intended to specify the presence of stated features, integers, steps, acts, or combinations thereof, as taught in the present specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.
Referring to fig. 1, an embodiment of the invention provides a display panel, which includes a printed circuit board 10, a first gold finger region 110, a timing controller 110, a level shifter 120, a power switch 130, a first test pad 150, a second test pad 160, a third test pad 170, a chip on film 20, a second gold finger region 210, a fourth test pad 220, a fifth test pad 230, a sixth test pad 240, a substrate wire region 30, a substrate wire 310, a first wire 320, a second wire 330, a third wire 340, a scan driving circuit 40, a scan line 410, a GOA unit 50, a first transistor 510, a second transistor 520, and a third transistor 530.
The printed circuit board 10 has a first gold finger region 110 and at least one test pad. The first gold finger area 110 is provided with a plurality of conductive contacts for signal transmission. In the embodiment of the present invention, the at least one test pad of the printed circuit board 10 includes a first test pad 150, a second test pad 160, and a third test pad 170. However, in some other embodiments, the number of the at least one test pad of the printed circuit board 10 is not limited thereto.
In addition, the printed circuit board 10 is further provided with a timing controller 110, a level shifter 120 and a power switch 130. The level shifter 120 is connected to the timing controller 110 and the power switch 130, respectively. The timing controller 110 is used for providing control signals, wherein the control signals include, but are not limited to, a frame start signal and a field shift pulse signal. The level shifter 120 is used for converting the levels of the analog ground voltage and the analog operating voltage into a gate-off voltage and a gate-on voltage. The power switch 130 is used to turn on or off the level shifter 120.
The chip on film 20 has a second gold finger region 210 and at least one test pad. Wherein at least one test pad of the chip on film is electrically connected to the second gold finger region 210. In the embodiment of the invention, the at least one test pad includes a fourth test pad 220, a fifth test pad 230 and a sixth test pad 240, and the fourth test pad 220, the fifth test pad 230 and the sixth test pad 240 are all electrically connected to the second gold finger region 210. However, in some other embodiments, the number of the at least one test pad of the chip on film 20 is not limited thereto.
The substrate wire area 30 has at least one trace and a plurality of substrate wires 310, wherein the at least one trace is electrically connected to the first gold finger area 110 and the second gold finger area 210. In the embodiment of the present invention, the at least one trace includes a first trace 320, a second trace 330, and a third trace 340. In some other embodiments, the number of at least one trace disposed in the substrate trace area 30 is not limited thereto.
The first trace 320, the second trace 330, and the third trace 340 are electrically connected to the first golden finger region 110 and the second golden finger region 210.
The scan driving circuit 40 includes a plurality of scan lines 410. Each scan line 410 is electrically connected to each corresponding substrate wire. The scan driving circuit 40 is used to drive a plurality of scan lines 410.
A plurality of GOA cells 50 in cascade, wherein the plurality of GOA cells 50 in the first row comprises at least one transistor. The gate of at least one transistor is connected to the second gold finger region 210 by at least one trace. The gate of at least one transistor is electrically connected to at least one test pad of the chip on film 20.
In the embodiment of the present invention, the at least one transistor includes a first transistor 510, a second transistor 520, and a third transistor 530. The first transistor 510 is located to the left of the first row of the plurality of GOA cells 50, the second transistor 520 is located in the middle of the first row of the plurality of GOA cells 50, and the third transistor 530 is located to the right of the first row of the plurality of GOA cells. The gates of the first transistor 510, the second transistor 520, and the third transistor 530 are respectively connected to the first gold finger region 110 through the first wire 320, the second wire 330, and the third wire 340, and the gates of the first transistor 510, the second transistor 520, and the third transistor 530 are electrically connected to the first test pad 150, the second test pad 160, and the third test pad 170. Meanwhile, the gates of the first transistor 510, the second transistor 520, and the third transistor 530 are respectively connected to the second gold finger region 210 through the first wire 320, the second wire 330, and the third wire 340, and the gates of the first transistor 510, the second transistor 520, and the third transistor 530 are electrically connected to the fourth test pad 220, the fifth test pad 230, and the sixth test pad 240. When the GOA circuit of the display panel outputs grid waveforms of transistors in the display panel, a probe of a common oscilloscope is only needed to test a test pad on the chip on film 20 or the printed circuit board 10, so that the method is very convenient, rapid and accurate. It should be noted that, in some other embodiments, the number of the at least one transistor is not limited to this. For example, the at least one transistor includes a fourth transistor located to the left of the first row in the plurality of GOA cells 50 and a fifth transistor located to the right of the first row in the plurality of GOA cells.
According to the embodiment of the invention, at least one test pad is arranged on the chip on film and the printed circuit board, and the test pad is electrically connected with the grid of the transistor through the wiring connected to the golden finger area, so that the grid waveform of the transistor output from the GOA circuit of the display panel to the display panel can be simply, quickly and accurately tested, the development efficiency is improved, and the product reliability is improved.
Referring to fig. 2, the embodiment of the invention provides another display panel, which is different from the previous embodiment in that the display panel is not provided with a test pad on a printed circuit board. The display panel includes a printed circuit board 10, a first golden finger region 110, a timing controller 110, a level shifter 120, a power switch 130, a chip on film 20, a second golden finger region 210, a first test pad 220, a second test pad 230, a third test pad 240, a substrate wire region 30, a substrate wire 310, a first wire 320, a second wire 330, a third wire 340, a scan driving circuit 40, a scan line 410, a GOA unit 50, a first transistor 510, a second transistor 520, and a third transistor 530.
The printed circuit board 10 is provided with a first gold finger area 110. The first gold finger area 110 is provided with a plurality of conductive contacts for signal transmission.
In addition, the printed circuit board 10 is further provided with a timing controller 110, a level shifter 120 and a power switch 130, wherein the level shifter 120 is connected to the timing controller 110 and the power switch 130, respectively. The timing controller 110 is used for providing control signals, wherein the control signals include, but are not limited to, a frame start signal and a field shift pulse signal. The level shifter 120 is used for converting the levels of the analog ground voltage and the analog operating voltage into a gate-off voltage and a gate-on voltage. The power switch 130 is used to turn on or off the level shifter 120.
The chip on film 20 has a second gold finger region 210 and at least one test pad, wherein the at least one test pad of the chip on film is electrically connected to the second gold finger region 210. In the embodiment of the invention, the at least one test pad includes a first test pad 220, a second test pad 230 and a third test pad 240, and the first test pad 220, the second test pad 230 and the third test pad 240 are all electrically connected to the second gold finger region 210.
The substrate wire area 30 has at least one trace and a plurality of substrate wires 310, wherein the at least one trace is electrically connected to the second gold finger area 210. In the embodiment of the present invention, the at least one trace includes a first trace 320, a second trace 330 and a third trace 340, wherein the first trace 320, the second trace 330 and the third trace 340 are electrically connected to the second golden finger region 210.
The scan driving circuit 40 includes a plurality of scan lines 410, and each scan line 410 is electrically connected to each corresponding substrate wire. The scan driving circuit 40 is used to drive a plurality of scan lines 410.
A plurality of cascaded GOA units 50, wherein the plurality of GOA units 50 in the first row include at least one transistor, a gate of the at least one transistor is connected to the second gold finger region 210 through at least one wire, and the gate of the at least one transistor is electrically connected to at least one test pad of the chip on film 20.
In the embodiment of the present invention, the at least one transistor includes a first transistor 510, a second transistor 520, and a third transistor 530. The first transistor 510 is located to the left of the first row of the plurality of GOA cells 50, the second transistor 520 is located in the middle of the first row of the plurality of GOA cells 50, and the third transistor 530 is located to the right of the first row of the plurality of GOA cells. The gates of the first transistor 510, the second transistor 520, and the third transistor 530 are respectively connected to the second gold finger region 210 through the first wire 320, the second wire 330, and the third wire 340, and the gates of the first transistor 510, the second transistor 520, and the third transistor 530 are electrically connected to the first test pad 220, the second test pad 230, and the third test pad 240. When the GOA circuit of the display panel is tested and the grid waveform of the transistor in the display panel is output, only the probe of the common oscilloscope is needed to test the test pad on the chip on film 20 or the printed circuit board 10, which is very convenient, fast and accurate.
According to the embodiment of the invention, at least one test pad is arranged on the chip on film and the printed circuit board, and the test pad is electrically connected with the grid of the transistor through the wiring connected to the golden finger area, so that the grid waveform of the transistor output from the GOA circuit of the display panel to the display panel can be simply, quickly and accurately tested, the development efficiency is improved, and the product reliability is improved.
Referring to fig. 3, an embodiment of the invention provides a display device 2 including the display panel 1 as described above. The display device 2 may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The display panel and the display device provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained herein by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A display panel, comprising:
a printed circuit board provided with a first golden finger area;
the chip on film is provided with a second golden finger area and at least one test pad, wherein the at least one test pad of the chip on film is electrically connected with the second golden finger area;
the substrate wire area is provided with at least one wire and a plurality of substrate wires, wherein the at least one wire is electrically connected with the first golden finger area and the second golden finger area;
the scanning driving circuit comprises a plurality of scanning lines, and each scanning line is electrically connected with each corresponding substrate lead; and
the plurality of GOA units in the first row comprise at least one transistor, the grid electrode of the at least one transistor is connected to the second golden finger area through the at least one wire, and the grid electrode of the at least one transistor is electrically connected with the at least one test pad of the chip on film.
2. The display panel of claim 1, wherein the printed circuit board has a timing controller, a level shifter and a power switch, and the level shifter is electrically connected to the timing controller and the power switch respectively.
3. The display panel according to claim 2, wherein the timing controller is configured to provide control signals, and the control signals comprise a frame start signal and a field shift pulse signal.
4. The display panel of claim 2, wherein the level shifter is configured to convert the levels of the analog ground voltage and the analog operating voltage into a gate-off voltage and a gate-on voltage.
5. The display panel according to claim 2, wherein the power switch is configured to turn on or off the level shifter.
6. The display panel of claim 1, wherein the printed circuit board has at least one test pad, and the at least one test pad of the printed circuit board is electrically connected to the first gold finger area.
7. The display panel of claim 6, wherein at least one test pad of the printed circuit board is electrically connected to the gate of the at least one transistor through the at least one trace connected to the first gold finger area.
8. The display panel according to claim 1, wherein the at least one transistor comprises a first transistor, a second transistor, and a third transistor.
9. The display panel of claim 8, wherein the first transistor is located to the left of a first row of the plurality of GOA cells, the second transistor is located in the middle of the first row of the plurality of GOA cells, and the third transistor is located to the right of the first row of the plurality of GOA cells.
10. A display device comprising the display panel according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911168213.4A CN110796975B (en) | 2019-11-25 | 2019-11-25 | Display panel and display device |
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| CN201911168213.4A CN110796975B (en) | 2019-11-25 | 2019-11-25 | Display panel and display device |
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| CN110796975B CN110796975B (en) | 2023-11-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021223280A1 (en) * | 2020-05-06 | 2021-11-11 | 武汉华星光电技术有限公司 | Fingerprint identification driving circuit |
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| WO2021223280A1 (en) * | 2020-05-06 | 2021-11-11 | 武汉华星光电技术有限公司 | Fingerprint identification driving circuit |
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| CN110796975B (en) | 2023-11-28 |
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