CN107340657A - Array base palte - Google Patents
Array base palte Download PDFInfo
- Publication number
- CN107340657A CN107340657A CN201710663004.1A CN201710663004A CN107340657A CN 107340657 A CN107340657 A CN 107340657A CN 201710663004 A CN201710663004 A CN 201710663004A CN 107340657 A CN107340657 A CN 107340657A
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- China
- Prior art keywords
- goa
- stv
- goa circuits
- electrically connected
- viewing area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of array base palte, the array base palte by the STV signal leads of an a plurality of output signal line of leap in the prior art by being divided into two STV signal leads, a wherein STV signal lead is directly accessed the GOA circuits via the GOA circuits close to the side of the viewing area, another STV signal lead accesses the GOA circuits away from GOA circuits described in the side wraparound of the viewing area from the GOA circuits close to the side of the viewing area, STV signal leads can be avoided to cross over a plurality of output signal line, prevent STV signal leads from producing interference with output signal line, ensure the job stability of liquid crystal display panel.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) has thin fuselage, power saving, radiationless etc. numerous excellent
Point, is widely used.Such as：LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen
Curtain or notebook computer screen etc., occupy an leading position in flat display field.
In active liquid crystal display, each pixel is electrically connected with a thin film transistor (TFT) (TFT), the grid of thin film transistor (TFT)
Pole (Gate) is connected to horizontal scanning line, and drain electrode (Drain) is connected to the data wire of vertical direction, and source electrode (Source) then connects
To pixel electrode.Apply enough voltage on horizontal scanning line, can be electrically connected to the institute on this horizontal scanning line
Have TFT openings, so as to the signal voltage on data wire can writing pixel, control light transmittance and then the control of different liquid crystal
Color and the effect of brightness.The driving of current active liquid crystal display panel horizontal scanning line is mainly by external surface-mounted integrated circuit
(Integrated Circuit, IC) is completed, and external IC can control the charging and discharging step by step of horizontal scanning lines at different levels.
And GOA technologies (Gate Driver on Array) are array base palte row actuation techniques, liquid crystal display panel can be used
Gate driving circuit is produced on the array base palte of liquid crystal display panel by array process, realizes the driving to grid progressive scan
Mode.GOA technologies can reduce external IC welding (bonding) process, have an opportunity to lift production capacity and reduce product cost, and
Liquid crystal display panel can be made to be more suitable for the display product for making narrow frame or Rimless.
As shown in figure 1, the existing array base palte using GOA technologies includes：Viewing area 100, positioned at the viewing area 100
The GOA circuits 200 of side and bonding (Bonding) area 300 above the GOA circuits 200 and viewing area 100,
The GOA circuits 200 include the GOA unit for the multiple cascades being arranged in order, and pass through an output signal per one-level GOA unit
Line 400 is electrically connected with the viewing area 100, and the bonding area 300 is used to pass through chip on film (Chip On Flex, COF)
All kinds of control signals of GOA circuits 200 are obtained from external printed circuit board (Printed Circuit Board, PCB), and will
All kinds of control signals are input in GOA circuits 200 by corresponding cabling, wherein, circuit start (STV) signal is usual GOA
A kind of indispensable control signal of circuit, be mainly used in controlling what preceding GOA unit of GOA circuits start working and it is rear what
The signal that GOA unit is stopped, existing STV signal leads 500 first access GOA circuits 200 after being drawn from bonding area 300
The first order or what preceding GOA unit, then across the afterbody of access GOA circuits 200 after a plurality of output signal line 400 or finally
What GOA unit, this cabling design span a plurality of output signal line 400, easily produce signal interference (Couple), influence
The normal work of liquid crystal display panel, reduce the job stability of liquid crystal display panel.
The content of the invention
It is an object of the invention to a kind of array base palte, and STV signal leads can be avoided to cross over a plurality of output signal line, prevents
Only STV signal leads produce interference with output signal line, ensure the job stability of liquid crystal display panel.
To achieve the above object, the invention provides a kind of array base palte, including：Viewing area, it is located at the display respectively
The GOA circuits of the adjacent both sides in area and bonding area, a plurality of output signal cabling of connection viewing area and GOA circuits and connection
The GOA circuits and the first STV signal leads in bonding area and the 2nd STV signal leads；
The GOA circuits the side of the close viewing area be provided with least one first STV signals access point and
At least one 2nd STV signal access points, each first STV signals access point are located at the GOA circuits close to the nation
Determine the one end in area, each 2nd STV signals access point is located at the one end of the GOA circuits away from the bonding area；
The first STV signal leads are drawn from the bonding area, via the GOA circuits close to the one of the viewing area
Side is electrically connected with each first STV signals access point, and the 2nd STV signal leads are drawn from the bonding area, around institute
Side of the GOA circuits away from the viewing area is stated to be electrically connected with each 2nd STV signals access point.
The GOA circuits include：The multistage GOA unit of cascade, pass through an output signal cabling per one-level GOA unit
It is electrically connected with the viewing area.
The GOA circuits are provided with a first STV signals access point and one second in the side close to the viewing area
STV signal access points, the first order GOA unit of one first STV signals access point and the GOA circuits are electrically connected with,
The afterbody GOA unit of one 2nd STV signals access point and the GOA circuits is electrically connected with.
The GOA circuits are provided with two the first STV signals access points and two second in the side close to the viewing area
STV signal access points, described two first STV signals access points first order GOA unit and second with the GOA circuits respectively
Level GOA unit is electrically connected with, described two 2nd STV signals access points afterbody GOA unit with the GOA circuits respectively
It is electrically connected with penultimate stage GOA unit.
The multiple pixel cells and multi-strip scanning line of array arrangement are provided with the viewing area, per one-row pixels unit pair
Electrotropism connects a scan line, each scan line one output signal cabling of corresponding connection.
The bonding area is also electrically connected with by chip on film and a printed circuit board (PCB), and the bonding area is electric from the printing
Road plate obtains STV signals and provides the first STV signal leads and the 2nd STV signal leads.
Also include：A plurality of to connect the GOA circuits and the control signal cabling in bonding area, the bonding area is also from the print
Printed circuit board obtains control signal and provides the control signal cabling.
The control signal includes the clock signal of GOA circuits.
The control signal cabling from the bonding area draw via side of the GOA circuits away from the viewing area with
The GOA circuits are electrically connected with.
Beneficial effects of the present invention：The present invention provides a kind of array base palte, and the array base palte is by will in the prior art one
Bar is divided into two STV signal leads across the STV signal leads of a plurality of output signal line, wherein a STV signal lead via
The GOA circuits are directly accessed the GOA circuits close to the side of the viewing area, and another STV signal lead is from the GOA
Circuit accesses the GOA circuits, energy away from GOA circuits described in the side wraparound of the viewing area close to the side of the viewing area
Enough avoid STV signal leads from crossing over a plurality of output signal line, prevent STV signal leads from producing interference with output signal line, ensure
The job stability of liquid crystal display panel.
Brief description of the drawings
In order to be further understood that the feature of the present invention and technology contents, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, be not used for being any limitation as the present invention.
In accompanying drawing,
Fig. 1 is the structural representation of existing array base palte；
Fig. 2 is the structural representation of the array base palte of the present invention；
Fig. 3 is the electricity of the GOA unit in addition to the first order and afterbody of the first embodiment of the array base palte of the present invention
Lu Tu；
Fig. 4 is the circuit diagram of the first order GOA unit of the first embodiment of the array base palte of the present invention；
Fig. 5 is the circuit diagram of the afterbody GOA unit of the first embodiment of the array base palte of the present invention.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Referring to Fig. 2, the present invention provides a kind of array base palte, including：Viewing area 10, it is located at the phase of viewing area 10 respectively
The GOA circuits 20 of adjacent both sides and bonding area 30, connection viewing area 10 and GOA circuits 20 a plurality of output signal cabling 40, with
And the connection GOA circuits 20 and the first STV signal leads 51 in bonding area 30 and the 2nd STV signal leads 52；
The GOA circuits 20 access in the side of the close viewing area 10 provided with least one first STV signals
Point 53 and at least one 2nd STV signals access point 54, each first STV signals access point 53 are located at the GOA circuits
20 close to the one end in the bonding area 30, and each 2nd STV signals access point 54 is located at the GOA circuits 20 away from described
The one end in bonding area 30；
The first STV signal leads 51 are drawn from the bonding area 30, via the GOA circuits 20 close to the display
The side in area 10 is electrically connected with each first STV signals access point 53, and the 2nd STV signal leads 52 are from the bonding area
30 draw, and electrically connect around side of the GOA circuits 20 away from the viewing area 10 and each 2nd STV signals access point 54
Connect.Namely the first STV signal leads 51 are directly accessed institute via the GOA circuits 20 close to the side of the viewing area 10
State GOA circuits 20, GOA described in the 2nd STV signal leads 52 from side wraparound of the GOA circuits 20 away from the viewing area 10
Circuit 20 accesses the GOA circuits 20 again behind the side of the viewing area 10.
Specifically, as shown in Fig. 2 the GOA circuits 20 include：The multistage GOA unit 21 of cascade, per one-level GOA unit
21 are electrically connected with by an output signal cabling 40 and the viewing area 10.Further, it is provided with the viewing area 10
The multiple pixel cells 11 and multi-strip scanning line 12 of array arrangement, it is corresponding per one-row pixels unit 11 to be electrically connected with a scanning
Line 12, each one output signal cabling 40 of corresponding connection of scan line 12.
Specifically, the quantity of the first STV signals access point 53 and the 2nd STV signals access point 54 is according to the GOA
The actual circuit of circuit 20 is set accordingly.
For example, in the first embodiment of the invention, include per one-level GOA unit 21 in the GOA circuits 20：On
Draw control module 1, pull-up module 2, drop-down module 5, first to pull down maintenance module 3, second and pull down maintenance module 4 and storage
Electric capacity Cb, if N is positive integer, in addition to the first order and afterbody GOA unit 21, in N levels GOA unit 21, the pull-up
Control module 1 includes：11st thin film transistor (TFT) T11, the 11st thin film transistor (TFT) T11 grid and source electrode access
The output signal G (N-1) of one-level GOA unit, drain electrode are electrically connected with first node Q (N)；The pull-up module 2 includes：20th
One thin film transistor (TFT) T21, the 21st thin film transistor (TFT) T21 grid is electrically connected with first node Q (N), source electrode access
Clock signal CK, drain electrode output signal output G (N)；The drop-down module 5 includes：41st thin film transistor (TFT) T41, it is described
The output signal G (N+1) of 41st thin film transistor (TFT) T41 grid access next stage GOA unit, source electrode are electrically connected with first
Node Q (N), drain electrode access low-potential signal VSS；31st thin film transistor (TFT) T31, the 31st thin film transistor (TFT)
The output signal G (N+1) of T31 grid access next stage GOA unit, source electrode are electrically connected with the 21st thin film transistor (TFT) T21
Drain electrode, drain electrode access low-potential signal VSS；The first drop-down maintenance module 3 includes the 32nd thin film transistor (TFT) T32,
The grid of the 32nd thin film transistor (TFT) T32 is electrically connected with section point K (N), and source electrode is electrically connected with the 21st film
Transistor T21 drain electrode, drain electrode access low-potential signal VSS；42nd thin film transistor (TFT) T42,42 film are brilliant
Body pipe T42 grid is electrically connected with section point K (N), and source electrode is electrically connected with first node Q (N), drain electrode access low-potential signal
VSS；51st thin film transistor (TFT) T51, the 51st thin film transistor (TFT) T51 grid and source electrode access the second drop-down
Control signal LC2, drain electrode are electrically connected with the 52nd thin film transistor (TFT) T52 source electrode；52nd thin film transistor (TFT) T52, institute
The grid for stating the 52nd thin film transistor (TFT) T52 is electrically connected with first node Q (N), drain electrode access low-potential signal VSS；5th
13 thin film transistor (TFT) T53, the 53rd thin film transistor (TFT) T53 grid is electrically connected with the 52nd thin film transistor (TFT)
T52 source electrode, source electrode access the second drop-down control signal LC2, drain electrode are electrically connected with section point K (N)；54th film is brilliant
Body pipe T54, the 54th thin film transistor (TFT) T54 grid are electrically connected with first node Q (N), and source electrode is electrically connected with second
Node K (N), drain electrode access low-potential signal VSS；The second drop-down maintenance module 4 includes：33rd thin film transistor (TFT)
T33, the 33rd thin film transistor (TFT) T33 grid are electrically connected with the 3rd node P (N), and source electrode is electrically connected with the 21st
Thin film transistor (TFT) T21 drain electrode, drain electrode access low-potential signal VSS；43rd thin film transistor (TFT) T43, described 43 is thin
Film transistor T43 grid is electrically connected with the 3rd node P (N), and source electrode is electrically connected with first node Q (N), drain electrode access low potential
Signal VSS；61st thin film transistor (TFT) T61, the 61st thin film transistor (TFT) T61 grid and source electrode access first
Control signal LC1 is pulled down, drain electrode is electrically connected with the 62nd thin film transistor (TFT) T62 source electrode；62nd thin film transistor (TFT)
T62, the 62nd thin film transistor (TFT) T62 grid are electrically connected with first node Q (N), drain electrode access low-potential signal
VSS；63rd thin film transistor (TFT) T63, the 63rd thin film transistor (TFT) T63 grid are electrically connected with the 62nd film
Transistor T62 source electrode, source electrode access the first drop-down control signal LC1, drain electrode are electrically connected with the 3rd node P (N)；64th
Thin film transistor (TFT) T64, the 64th thin film transistor (TFT) T64 grid are electrically connected with first node Q (N), and source electrode electrically connects
Meet the 3rd node P (N), drain electrode access low-potential signal VSS；One end of the storage capacitance Cb is electrically connected with first node Q
(N), the other end is electrically connected with the 21st thin film transistor (TFT) T21 drain electrode.
Further, in this first embodiment, as shown in figure 4, its first order GOA unit 21 with except the first order and finally
The difference of other GOA units is outside one-level GOA unit 21, the 11st thin film transistor (TFT) T11 in the first order GOA unit 21
Source electrode STV signals are accessed by the first STV signals access point 53 and the first STV signal leads 51, as shown in figure 5, its
The difference of afterbody GOA unit 21 and other GOA units in addition to the first order and afterbody GOA unit 21 is, it is described most
The 41st thin film transistor (TFT) T41 and the 31st thin film transistor (TFT) T31 grid pass through described in rear stage GOA unit 21
Two STV signals access points 54 and the 2nd STV signal leads 52 access STV signals, namely in this first embodiment, the GOA
Circuit 20 is connecing close to the side of the viewing area 10 provided with a first STV signals access point 53 and a 2nd STV signal
Access point 54, the first order GOA unit 21 of one first STV signals access point 53 and the GOA circuits 21 are electrically connected with, institute
The afterbody GOA unit 21 for stating a 2nd STV signals access point 54 and the GOA circuits 21 is electrically connected with.
Certainly, in other embodiments of the invention, the GOA circuits 20 close to the viewing area 10 side other
First STV signals access point 53 of quantity and the 2nd STV signals access point 54, for example, when the GOA circuits 20 are swept using interlacing
When retouching, the GOA circuits 20 can also set two Hes of the first STV signals access point 53 close to the side of the viewing area 10
Two the 2nd STV signals access points 54, described two first STV signals access points 53 respectively with the GOA circuits 21 first
Level GOA unit 21 and second level GOA unit 21 be electrically connected with, described two 2nd STV signals access points 54 respectively with the GOA
The afterbody GOA unit 21 and penultimate stage GOA unit 21 of circuit 21 are electrically connected with, and these can be according to specific
GOA circuits 20 are set accordingly.
Specifically, as shown in Fig. 2 the bonding area 30 is also electrically connected by chip on film 60 and a printed circuit board (PCB) 70
Connect, the bonding area 30 obtains STV signals from the printed circuit board (PCB) 70 and provides the first STV signal leads 51 and second
STV signal leads 52.Further, the array base palte also includes：The a plurality of control for connecting the GOA circuits 20 and bonding area 30
Signal lead 55 processed, the bonding area 30 also obtain control signal and provide the control signal from the printed circuit board (PCB) 70
Line 55, it is preferable that the control signal includes the clock signal of GOA circuits 20, and the control signal cabling 55 is from the bonding
Area 30 is drawn to be electrically connected with via side of the GOA circuits 20 away from the viewing area 10 with the GOA circuits 20.
In summary, the present invention provides a kind of array base palte, the array base palte by will in the prior art a leap it is more
The STV signal leads of bar output signal line are divided into two STV signal leads, wherein a STV signal lead is via GOA electricity
Road is directly accessed the GOA circuits close to the side of the viewing area, and another STV signal lead is away from the GOA circuits
GOA circuits described in the side wraparound of the viewing area access the GOA circuits close to the side of the viewing area, can avoid
STV signal leads cross over a plurality of output signal line, prevent STV signal leads from producing interference with output signal line, ensure liquid crystal
Show the job stability of panel.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the claims in the present invention
Protection domain.
Claims (9)
- A kind of 1. array base palte, it is characterised in that including：Viewing area (10), respectively positioned at the viewing area (10) it is adjacent two The GOA circuits (20) of side and a plurality of output signal cabling of bonding area (30), connection viewing area (10) and GOA circuits (20) (40) and the connection GOA circuits (20) and the first STV signal leads (51) of bonding area (30) and the 2nd STV signals are walked Line (52)；The GOA circuits (20) are accessed in the side of the close viewing area (10) provided with least one first STV signals Point (53) and at least one 2nd STV signals access point (54), each first STV signals access point (53) is positioned at described GOA circuits (20) are located at the GOA close to one end of the bonding area (30), each 2nd STV signals access point (54) The one end of circuit (20) away from the bonding area (30)；The first STV signal leads (51) are drawn from the bonding area (30), via the GOA circuits (20) close to described aobvious Show that the side in area (10) is electrically connected with each first STV signals access point (53), the 2nd STV signal leads (52) are from institute Bonding area (30) extraction is stated, around side of the GOA circuits (20) away from the viewing area (10) and each 2nd STV signals Access point (54) is electrically connected with.
- 2. array base palte as claimed in claim 1, it is characterised in that the GOA circuits (20) include：The multistage GOA of cascade Unit (21), it is electrically connected with per one-level GOA unit (21) by an output signal cabling (40) and the viewing area (10).
- 3. array base palte as claimed in claim 2, it is characterised in that the GOA circuits (20) are close to the viewing area (10) side is provided with a first STV signals access point (53) and a 2nd STV signals access point (54), and one One STV signals access point (53) and the first order GOA unit (21) of the GOA circuits (21) are electrically connected with, and one second STV signals access point (54) and the afterbody GOA unit (21) of the GOA circuits (21) are electrically connected with.
- 4. array base palte as claimed in claim 2, it is characterised in that the GOA circuits (20) are close to the viewing area (10) side is provided with two the first STV signals access points (53) and two the 2nd STV signals access points (54), and described two One STV signals access point (53) first order GOA unit (21) and second level GOA unit with the GOA circuits (21) respectively (21) it is electrically connected with, described two 2nd STV signals access points (54) afterbody GOA with the GOA circuits (21) respectively Unit (21) and penultimate stage GOA unit (21) are electrically connected with.
- 5. array base palte as claimed in claim 2, it is characterised in that multiple provided with array arrangement in the viewing area (10) Pixel cell (11) and multi-strip scanning line (12), it is corresponding per one-row pixels unit (11) to be electrically connected with a scan line (12), Each scan line (12) one output signal cabling (40) of corresponding connection.
- 6. array base palte as claimed in claim 1, it is characterised in that the bonding area (30) also by chip on film (60) with One printed circuit board (PCB) (70) is electrically connected with, and the bonding area (30) obtains STV signals from the printed circuit board (PCB) (70) and provided The first STV signal leads (51) and the 2nd STV signal leads (52).
- 7. array base palte as claimed in claim 6, it is characterised in that also include：It is a plurality of to connect the GOA circuits (20) and nation Determine the control signal cabling (55) in area (30), the bonding area (30) also obtains control signal simultaneously from the printed circuit board (PCB) (70) The control signal cabling (55) is provided.
- 8. array base palte as claimed in claim 7, it is characterised in that the control signal includes the clock of GOA circuits (20) Signal.
- 9. array base palte as claimed in claim 7, it is characterised in that the control signal cabling (55) is from the bonding area (30) draw and be electrically connected with via side of the GOA circuits (20) away from the viewing area (10) with the GOA circuits (20).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710663004.1A CN107340657A (en) | 2017-08-04 | 2017-08-04 | Array base palte |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710663004.1A CN107340657A (en) | 2017-08-04 | 2017-08-04 | Array base palte |
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| CN107340657A true CN107340657A (en) | 2017-11-10 |
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| CN201710663004.1A Pending CN107340657A (en) | 2017-08-04 | 2017-08-04 | Array base palte |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991816A (en) * | 2017-11-27 | 2018-05-04 | 深圳市华星光电技术有限公司 | The manufacture method of liquid crystal display panel and bar shaped liquid crystal display panel |
| CN110109301A (en) * | 2019-04-23 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate, display device |
| CN110208993A (en) * | 2019-05-15 | 2019-09-06 | 深圳市华星光电技术有限公司 | Display panel |
| WO2020013982A1 (en) * | 2018-07-13 | 2020-01-16 | Corning Incorporated | Apparatus and displays with reduced light leakage mura |
| CN110796975A (en) * | 2019-11-25 | 2020-02-14 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN110928009A (en) * | 2019-11-26 | 2020-03-27 | Tcl华星光电技术有限公司 | Liquid crystal display panel |
| WO2020215549A1 (en) * | 2019-04-25 | 2020-10-29 | 深圳市华星光电技术有限公司 | Display device |
| CN112180645A (en) * | 2020-10-19 | 2021-01-05 | Tcl华星光电技术有限公司 | Array substrate |
| CN113314064A (en) * | 2021-05-31 | 2021-08-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN115331601A (en) * | 2022-08-15 | 2022-11-11 | 厦门天马显示科技有限公司 | Display panel and display device |
| WO2023155164A1 (en) * | 2022-02-18 | 2023-08-24 | 京东方科技集团股份有限公司 | Display apparatus and driving method therefor |
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| CN107991816A (en) * | 2017-11-27 | 2018-05-04 | 深圳市华星光电技术有限公司 | The manufacture method of liquid crystal display panel and bar shaped liquid crystal display panel |
| WO2020013982A1 (en) * | 2018-07-13 | 2020-01-16 | Corning Incorporated | Apparatus and displays with reduced light leakage mura |
| CN110109301A (en) * | 2019-04-23 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate, display device |
| WO2020215549A1 (en) * | 2019-04-25 | 2020-10-29 | 深圳市华星光电技术有限公司 | Display device |
| CN110208993A (en) * | 2019-05-15 | 2019-09-06 | 深圳市华星光电技术有限公司 | Display panel |
| CN110796975A (en) * | 2019-11-25 | 2020-02-14 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN110796975B (en) * | 2019-11-25 | 2023-11-28 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN110928009A (en) * | 2019-11-26 | 2020-03-27 | Tcl华星光电技术有限公司 | Liquid crystal display panel |
| CN112180645A (en) * | 2020-10-19 | 2021-01-05 | Tcl华星光电技术有限公司 | Array substrate |
| CN112180645B (en) * | 2020-10-19 | 2022-02-01 | Tcl华星光电技术有限公司 | Array substrate |
| CN113314064A (en) * | 2021-05-31 | 2021-08-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| WO2023155164A1 (en) * | 2022-02-18 | 2023-08-24 | 京东方科技集团股份有限公司 | Display apparatus and driving method therefor |
| CN115331601A (en) * | 2022-08-15 | 2022-11-11 | 厦门天马显示科技有限公司 | Display panel and display device |
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