WO2020013982A1

WO2020013982A1 - Apparatus and displays with reduced light leakage mura

Info

Publication number: WO2020013982A1
Application number: PCT/US2019/038870
Authority: WO
Inventors: Ravindra Kumar AKARAPU; Wei Shin Chen; Tomohiro Ishikawa
Original assignee: Corning Incorporated
Priority date: 2018-07-13
Filing date: 2019-06-25
Publication date: 2020-01-16
Also published as: TW202013746A

Abstract

An apparatus includes a substrate, a thin-film-transistor (TFT) array, a circuit, driving lines, and straight signal lines. The substrate includes a first area and a second area. The TFT array is in the first area of the substrate. The circuit is in the second area of the substrate and in electrical communication with the TFT array. The driving lines are in the second area of the substrate between a first edge of the substrate and the circuit. The driving lines are in electrical communication with the circuit. The straight signal lines are aligned with and in electrical communication with the driving lines in the second area of the substrate. The straight signal lines extend to a second edge of the substrate perpendicular to the first edge.

Description

APPARATUS AND DISPLAYS WITH REDUCED LIGHT LEAKAGE

MURA

BACKGROUND

Field

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application Serial No. 62/697,491 filed on July 13, 2018, the content of which is relied upon and incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to liquid crystal displays. More particularly, it relates to liquid crystal displays with reduced light leakage mura.

Technical Background

[0003] A thin-film-transistor (TFT) array may be formed on a substrate to control liquid crystal display (LCD) elements to form images. Gate-on-array (GOA) circuitry may also be formed on the substrate to drive the rows (i.e., gates) of the TFT array. As the frame area for LCD displays becomes narrower, the area available for the GOA circuitry also becomes narrower. A narrower width for the GOA circuitry leads to narrower GOA driving lines, which leads to higher resistivity of the GOA driving lines. The higher resistivity of the GOA driving lines leads to higher joule heating of the GOA driving lines. The higher joule heating of the GOA driving lines leads to higher thermal stress in the glass substrate. The higher thermal stress in the substrate increases the impact on stress retardation within the substrate which results in a higher light leakage mura (LLM) intensity. LLM may affect the quality of the displayed images and thus should be minimized or eliminated.

[0004] LLM may be defined as follows. With the presence of the temperature gradient VT, a magnitude of retardation, R, is given by:

R=|VT|*a*E*SOC*d where a is a coefficient of thermal expansion, SOC is a stress optical coefficient, E is Young’s modulus, and d is a thickness of the substrate, respectively. Along R, the azimuthal direction of retardation also impacts LLM. Light intensity of LLM, I, is proportional to the factor given as:

where Q is an azimuthal angle of retardation with respect to the polarizer axes (vertical and horizontal) of the LCD display, and l is a wavelength of the light. Thus, there is no LLM if Q is 0 or 90 degrees, even with high R.

SUMMARY

[0005] Some embodiments of the present disclosure relate to an apparatus. The apparatus includes a substrate, a thin-film-transistor (TFT) array, a circuit, driving lines, and straight signal lines. The substrate includes a first area and a second area. The TFT array is in the first area of the substrate. The circuit is in the second area of the substrate and in electrical communication with the TFT array. The driving lines are in the second area of the substrate between a first edge of the substrate and the circuit. The driving lines are in electrical communication with the circuit. The straight signal lines are aligned with and in electrical communication with the driving lines in the second area of the substrate. The straight signal lines extend to a second edge of the substrate perpendicular to the first edge.

[0006] Yet other embodiments of the present disclosure relate to a display. The display includes a substrate, a TFT array, a row addressing circuit, gate driving lines, straight gate signal lines, source driving lines, a printed circuit board (PCB), and a chip-on-film (COF) film. The substrate includes a first area and a second area. The TFT array is in the first area of the substrate. The row addressing circuit is in the second area of the substrate and in electrical communication with the TFT array. The gate driving lines are in the second area of the substrate between a first edge of the substrate and the row addressing circuit. The gate driving lines are in electrical communication with the row addressing circuit. The straight gate signal lines are aligned with and in electrical communication with the gate driving lines in the second area of the substrate. The straight gate signal lines extend to a second edge of the substrate perpendicular to the first edge. The source driving lines are in the first area of the substrate and in electrical communication with the TFT array. The COF film electrically couples the PCB to the straight gate signal lines and the source driving lines. [0007] Yet other embodiments of the present disclosure relate to a display. The display includes a substrate, a TFT array, a row addressing circuit, gate driving lines, straight gate signal lines, source driving lines, a printed circuit board (PCB), a first COF film, and a second COF film. The substrate includes a first area and a second area. The TFT array is in the first area of the substrate. The row addressing circuit is in the second area of the substrate and in electrical communication with the TFT array. The gate driving lines are in the second area of the substrate between a first edge of the substrate and the row addressing circuit. The gate driving lines are in electrical communication with the row addressing circuit. The straight gate signal lines are aligned with and in electrical communication with the gate driving lines in the second area of the substrate. The straight gate signal lines extend to a second edge of the substrate perpendicular to the first edge. The source driving lines are in the first area of the substrate and in electrical communication with the TFT array. The first COF film electrically couples the PCB to the straight gate signal lines. The second COF film electrically couples the PCB to the source driving lines.

[0008] The apparatus and displays disclosed herein reduce or eliminate light leakage mura (LLM) due to thermal stress from gate-on-array (GOA) circuitry. The apparatus and displays maintain a narrow frame by not having to increase the GOA line width to achieve lower joule heating. In addition, the apparatus and displays are applicable to higher resolution (e.g., 8k) displays where an increased number (thus narrower) of GOA driving lines are expected.

[0009] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.

[0010] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiment s), and together with the description serve to explain principles and operation of the various embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. l is a top-down view of an exemplary apparatus including a thin-film-transistor (TFT array) with gate-on-array (GOA) circuitry; [0012] FIG. 2 is a top-down view of an exemplary display including one chip-on-film (COF) film;

[0013] FIG. 3 is a top-down view of an exemplary display including two COF films;

[0014] FIG. 4 is a cross-sectional view of an exemplary display including a liquid crystal display (LCD) stack; and

[0015] FIGS. 5A-5C are top-downs views of maps of simulated temperature, retardation, and light leakage mura (LLM), respectively, for the displays of FIGS. 2 and 3.

DETAILED DESCRIPTION

[0016] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

[0017] Ranges can be expressed herein as from“about” one particular value, and/or to “about” another particular value. When such a range is expressed, another embodiment includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent“about,” it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

[0018] Directional terms as used herein - for example up, down, right, left, front, back, top, bottom, vertical, horizontal - are made only with reference to the figures as drawn and are not intended to imply absolute orientation.

[0019] Unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order, nor that with any apparatus, specific orientations be required. Accordingly, where a method claim does not actually recite an order to be followed by its steps, or that any apparatus claim does not actually recite an order or orientation to individual components, or it is not otherwise specifically stated in the claims or description that the steps are to be limited to a specific order, or that a specific order or orientation to components of an apparatus is not recited, it is in no way intended that an order or orientation be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps, operational flow, order of components, or orientation of components; plain meaning derived from grammatical organization or punctuation, and; the number or type of embodiments described in the specification.

[0020] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to“a” component includes aspects having two or more such components, unless the context clearly indicates otherwise.

[0021] Referring now to FIG. 1, a top-down view of an exemplary apparatus 100 is depicted. Apparatus 100 may be used in a display device. Apparatus 100 includes a substrate 102, a thin- film-transistor (TFT) array 112, a row addressing circuit 114, gate driving lines 116, straight gate signal lines 118, and source driving lines 120. Row addressing circuit 114, gate driving lines 116, and straight gate signal lines 118 form a gate-on-array (GOA) circuit. Substrate 100 includes a first (i.e., main) area 104 and a second (i.e., left edge) area 106. Substrate 100 may be made of a transparent material, such as glass or plastic. TFT array 112 is in the first area 104 of substrate 102. TFT array 112 may be in electrical communication with a liquid crystal display (LCD) stack, which will be described in more detail below with reference to FIG. 4. TFT array 112 and the LCD stack may form an LCD panel for displaying images by individually controlling each pixel of the LCD panel. Each pixel of the LCD panel is individually controlled by individually controlling each transistor of the TFT array 112 via row addressing circuit 114 and source driving lines 120.

[0022] Row addressing circuit 114 is in the second area 106 of substrate 102 and in electrical communication with the TFT array 112. Row addressing circuit 114 selects the rows (i.e., gates) of TFT array 112 based on an address signal on gate driving lines 116. The gate driving lines 116 are in the second area 106 of the substrate 102 between a first edge 108 of the substrate 102 and the row addressing circuit 114. The gate driving lines 116 are in electrical communication with the row addressing circuit 114. The straight gate signal lines 118 are aligned with and in electrical communication with the gate driving lines 116 in the second area 106 of the substrate 102. The straight gate signal lines 118 are parallel to each other and extend to a second edge 110 of the substrate 102 perpendicular to the first edge 108. The straight gate signal lines 118 pass address signals to the gate driving lines 116. Any suitable number of straight gate signal lines 118 may be used to pass address signals to gate driving lines 116 based upon the size of TFT array 112 and the configuration of row addressing circuit 114.

[0023] Source driving lines 120 are in the first area 104 of the substrate 102 and are in electrical communication with the TFT array 112. In certain exemplary embodiments, source driving lines 120 may be parallel to straight gate signal lines 118 and may extend to the second edge 110 of the substrate 102. In other embodiments, source driving lines 120 may be arranged in a fan layout between TFT array 112 and the second edge 110 of the substrate 102. A suitable number of source driving lines 120 based on the size of TFT array 112 are used for selecting columns (i.e., sources) of the TFT array 112.

[0024] During operation of apparatus 100, joule heating of the straight gate signal lines 118 is limited to the vertical portion parallel to the first edge 108 in the second area 106 of the substrate 102. Accordingly, LLM is reduced or eliminated as will be described in more detail below with reference to FIGS. 5A-5C.

[0025] FIG. 2 is a top-down view of an exemplary display 200. Display 200 includes apparatus 100 previously described and illustrated with reference to FIG. 1. In addition, display 200 includes a printed circuit board (PCB) 202 and a chip-on-film (COF) film 204. PCB 202 may include row and/or column address generating and timing circuitry for controlling TFT array 112. COF film 204 electrically couples the PCB 202 to the straight gate signal lines 118 and the source driving lines 120. COF film 204 includes gate signal lines 206 to electrically couple PCB 202 to straight gate signal lines 118. COF film 204 may include a column (i.e., source) driving chip 208 to electrically couple PCB 202 to source driving lines 120.

[0026] FIG. 3 is a top-down view of an exemplary display 250. Display 250 includes apparatus 100 previously described and illustrated with reference to FIG. 1 and PCB 202 previously described and illustrated with reference to FIG. 2. In addition, display 250 includes a first COF film 252 and a second COF film 256. First COF film 252 may be spaced apart horizontally from second COF film 256. First COF film 252 electrically couples the PCB 202 to the straight gate signal lines 118. First COF film 252 includes gate signal lines 254 to electrically couple PCB 202 to straight gate signal lines 118. Second COF film 256 electrically couples the PCB 202 to the source driving lines 120. Second COF film 256 may include a column (i.e., source) driver chip 258 to electrically couple PCB 202 to source driving lines 120.

[0027] FIG. 4 is a cross-sectional view of an exemplary display 300. Display 300 may include a backlight 302, a substrate 304 including a TFT array, and an LCD stack 306, 308, and 310. In certain exemplary embodiments, substrate 304 may be similar to substrate 102 and may include a TFT array 112, row addressing circuit 114, gate driving lines 116, straight gate signal lines 118, and source driving lines 120 as previously described and illustrated with reference to FIG. 1. The LCD stack may include a liquid crystal layer 306, a color filter layer 308, and a polarizer layer 310. In other examples, the LCD stack may include other suitable layers. The LCD stack is in electrical communication with the TFT array of substrate 304. Backlight 302 is coupled to substrate 304 and may include any suitable direct lit or edge lit backlight.

[0028] FIGS. 5A-5C are top-downs views of a simulated temperature map 400a, a simulated retardation map 400b, and a simulated LLM map 400c, respectively, for the displays of FIGS. 2 and 3. As a comparison, a simulated temperature map 402a, a simulated retardation map 402b, and a simulated LLM map 402c, respectively, are also shown for a display that does not include straight gate signal lines (e.g., for a display where the gate signal lines extend into the first area of the substrate). In temperature maps 400a and 402a, the temperature is indicated by the grayscale level (i.e., lighter areas indicate higher temperatures). From the temperature maps 400a and 402a of FIG. 5A, the stress distribution within the substrates was calculated using finite element analysis (FEA), respectively. From the stress distributions, the retardation maps 400b and 402b (magnitude and direction) were derived as shown in FIG. 5B, respectively. In retardation maps 400b and 402b, the magnitude of retardation R is shown by the grayscale level (i.e., lighter areas indicate a greater magnitude of retardation) while the azimuthal direction (corresponding to the principal stress axis) is indicated by arrows. From the retardation maps 400b and 402b, the LLM maps 400c and 402c of FIG. 5C were derived, respectively. Referring to maps 400a, 400b, and 400c, it is noted that high R is concentrated near the left edge (where the GOA circuitry is arranged) where |VT| has large values. It is further noted that high R does not always correspond to a high LLM area.

[0029] High R concentrated near the left edge is expected as R is proportional to VT. However, since high R does not always correspond to a high LLM area, it is possible to control the LLM intensity and extent. Accordingly, the portion of higher LLM in map 400c FIG. 5C is not the portion with the highest retardation (e.g., along the left edge), rather, the portion of higher LLM is the portion where the azimuthal direction deviates the most from the vertical/horizontal direction.

[0030] The retardation azimuth is given by:

where scc and ayy are tensile stresses, and axy is share stress. This equation shows that non zero axy makes the azimuth deviate from the horizontal and the vertical direction, thus is responsible for the LLM. The left edge has high retardation, but due to a small share stress, the azimuth angle of retardation lines up with that of polarizers resulting in essentially no LLM.

[0031] LLM is reduced or eliminated in displays 200 and 250 of FIGS. 2 and 3 by limiting heating to the vertical portion parallel to the first edge 108 in the second area 106 of the substrate 102. This is achieved by using straight gate signal lines 118 aligned with gate driving lines 116 in the second area 106 of the substrate 102. The vertical heating portion has the highest retardation (e.g., greater than about 3 nm). However, this area does not lead to LLM as the azimuthal direction is parallel to the principal axes of the polarizers. The actual light leakage comes from the top left comer where the retardation has lower values (e.g., about 1.5 nm or less). In this area, due to the presence of share stress axy, the azimuthal direction deviates from the polarizer axes leading to LLM. Retardation with axy is generated at the top left comer, where tensile stress from both the vertical and the horizontal directions meets. As shown in map 400b of FIG. 5B, the top left corner retardation is substantially low since the heating is limited to the vertical direction. This leads to a substantially low LLM as shown in map 400c of FIG. 5C. It is noted that the slight LLM shown in map 400c of FIG. 5C is based on a simulation. In actual displays, the LLM may be substantially imperceptible to the human eye.

[0032] It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments of the present disclosure without departing from the spirit and scope of the disclosure. Thus it is intended that the present disclosure cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

What is claimed is:

1. An apparatus comprising:

a substrate comprising a first area and a second area;

a thin-film-transistor (TFT) array in the first area of the substrate;

a circuit in the second area of the substrate in electrical communication with the TFT array;

driving lines in the second area of the substrate between a first edge of the substrate and the circuit, the driving lines in electrical communication with the circuit; and

straight signal lines aligned with and in electrical communication with the driving lines in the second area of the substrate, the straight signal lines extending to a second edge of the substrate perpendicular to the first edge.

2. The apparatus of claim 1, further comprising:

further driving lines in the first area of the substrate in electrical communication with the TFT array.

3. The apparatus of claim 1, wherein joule heating of the straight signal lines is limited to a vertical portion parallel to the first edge in the second area of the substrate.

4. The apparatus of claim 1, wherein the substrate comprises a transparent material.

5. The apparatus of claim 3, wherein the substrate comprises glass.

6. The apparatus of claim 3, wherein the substrate comprises plastic.

7. A display comprising:

a substrate comprising a first area and a second area;

a thin-film-transistor (TFT) array in the first area of the substrate;

a row addressing circuit in the second area of the substrate in electrical communication with the TFT array;

gate driving lines in the second area of the substrate between a first edge of the substrate and the row addressing circuit, the gate driving lines in electrical communication with the row addressing circuit; straight gate signal lines aligned with and in electrical communication with the gate driving lines in the second area of the substrate, the straight gate signal lines extending to a second edge of the substrate perpendicular to the first edge;

source driving lines in the first area of the substrate and in electrical communication with the TFT array;

a printed circuit board (PCB); and

a chip-on-film (COF) film electrically coupling the PCB to the straight gate signal lines and the source driving lines.

8. The display of claim 7, wherein joule heating of the straight gate signal lines is limited to a vertical portion parallel to the first edge in the second area of the substrate.

9. The display of claim 7, further comprising:

a liquid crystal display (LCD) stack in electrical communication with the TFT array.

10. The display of claim 9, further comprising:

a backlight coupled to the substrate.

11. The display of claim 10, wherein the straight gate signal lines prevent light leakage mura.

12. The display of claim 7, wherein the substrate comprises a transparent material.

13. The display of claim 7, wherein the substrate comprises glass.

14. A display comprising:

a substrate comprising a first area and a second area;

a thin-film-transistor (TFT) array in the first area of the substrate;

a row addressing circuit in the second area of the substrate and in electrical communication with the TFT array;

a printed circuit board (PCB);

a first chip-on-film (COF) film electrically coupling the PCB to the straight gate signal lines; and

a second COF film electrically coupling the PCB to the source driving lines.

15. The display of claim 14, wherein joule heating of the straight gate signal lines is limited to a vertical portion parallel to the first edge in the second area of the substrate.

16. The display of claim 14, further comprising:

17. The display of claim 16, further comprising:

a backlight coupled to the substrate.

18. The display of claim 17, wherein the straight gate signal lines prevent light leakage mura.

19. The display of claim 14, wherein the substrate comprises a transparent material.

20. The display of claim 14, wherein the substrate comprises glass.