KR20110049094A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to form LOG signal lines in dual metal layer to minimize the distortion of driving voltage. CONSTITUTION: A liquid crystal display device comprises: a liquid crystal display panel(100) which is divided into a display region and a non-display region; plural gate driver ICs which drive plural gate lines(GL) and are placed on one side of the non-display region; plural data driver ICs which drive plural data lines and are placed on other side of the non-display region; and a PCB(Printed Circuit Board) which provides a driving signal and driving voltage to the gate and data driver ICs.

Description

Liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can improve the transmission efficiency of a scan signal and a power source by reducing the load of a LOG line disposed in a link portion of a non-display area of a liquid crystal display panel.

Recently, the liquid crystal display device is manufactured in a small and medium size, and is used in a GPS system that enables navigation services to aircraft, ships, and passenger cars, and devices made to enjoy multimedia while carrying images, music, and videos.

Such a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal display panel in which liquid crystal cells are arranged in a matrix by adjusting light transmittance of liquid crystal cells according to a video signal. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and a driving circuit for driving the liquid crystal display panel.

The driving circuit unit includes a gate driver supplying a scan signal to a gate line of the liquid crystal display panel, and a data driver supplying a data signal to a data line of the liquid crystal display panel. In this case, the data driver and the gate driver are integrated into a plurality of integrated circuit chips.

Each integrated data drive IC chip and gate drive IC chip are mounted on a tape carrier package (TCP) and connected to a liquid crystal display panel by a tape automated bonding (TAB) method and a TFT array substrate. There is a chip on glass (COG) method that directly mounts the drive IC chip.

Recently, in order to further reduce the size of the liquid crystal display by minimizing the size of the PCB, signal lines connected to the drive IC chips are being formed on a glass substrate in a line on glass (LOG) manner. By mounting the signal lines connected to the drive IC chips on the thin film transistor array substrate in the LOG method, the printed circuit board may be removed and the liquid crystal display panel may be further thinned.

In particular, since signal lines connected to gate drive ICs requiring relatively few signal lines are formed on the thin film transistor array substrate in a LOG method, a method of removing a gate printed circuit board is widely used.

In the LOG method in which the gate printed circuit board is removed, the gate drive ICs drive and control signals from a timing controller and a power supply mounted on the data printed circuit board through LOG signal lines formed on the thin film transistor array substrate. The voltages are supplied.

The LOG signal lines are formed on a non-display area of the liquid crystal display panel, and the LOG signal lines are formed using a mask process similarly to a plurality of gate lines and data lines formed on the liquid crystal display panel. In this case, the LOG signal lines supplied with the control signals and the driving voltages from the data printed circuit board and supplied to the gate drive IC formed on the thin film transistor array substrate are formed to fit the limited area of the non-display area. It is difficult to secure enough. As a result, distortion of a plurality of control signals and driving voltages supplied to the gate drive IC through the LOG signal line may result in deterioration of display quality of the liquid crystal display panel.

According to the present invention, the LOG signal lines formed in the link portion of the non-display area of the liquid crystal display panel are formed of a double metal layer to increase the cross-sectional area of the LOG signal line, thereby controlling and driving the control signals provided to the LOG signal line by line resistance. It is an object of the present invention to provide a liquid crystal display device capable of minimizing voltage distortion.

Another object of the present invention is to provide a liquid crystal display device capable of improving display quality.

According to an exemplary embodiment of the present invention, a liquid crystal display (LCD) includes a liquid crystal display panel divided into a display area in which liquid crystal cells are arranged in a matrix, and a non-display area except for the display area, and positioned on one side of the non-display area. A plurality of gate driver integrated circuits for driving, a plurality of data driver integrated circuits located on the other side of the non-display area and driving the plurality of data lines, and a driving signal and a driving voltage are provided to the gate and data driver integrated circuits. A printed circuit board, a flexible printed circuit board relaying between the liquid crystal panel and the printed circuit board, a printed circuit board, a flexible printed circuit board, and a non-display area of the liquid crystal panel; And driving a driving voltage to a first gate driver integrated circuit among the plurality of gate driver integrated circuits. A second LOG formed between the plurality of gate driver integrated circuits formed in the non-display area to provide a first LOG signal line and a driving signal and a driving voltage provided from the first gate driver integrated circuit to a next gate driver integrated circuit; A signal line is included, and the second LOG signal lines are formed in a double structure including first and second metal layers.

The liquid crystal display according to the present invention is formed by forming a LOG signal line formed on a link portion of a non-display area of a liquid crystal display panel by using a double metal layer formed of a first metal and a second metal formed on a layer different from the first metal, thereby forming the LOG signal. The display quality can be improved by minimizing distortion of the control signals and the driving voltage provided to the LOG signal line by the line resistance by increasing the cross-sectional area of the line.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other, and a liquid crystal cell Clc is disposed at an intersection thereof. A liquid crystal display panel 100 having a thin film transistor TFT for driving a light source, a gate driver 110 for supplying a scan signal to the gate lines GL1 to GLn, and a data line DL1 to DLm. A data driver 120 for supplying data, a timing controller 130 for controlling the gate driver 110 and the data driver 120, and a gate voltage generator for supplying a gate voltage to the gate driver 110. And a common voltage generator 150 supplying a common voltage to the common electrode of the liquid crystal display panel 100.

The liquid crystal display panel 100 has a liquid crystal formed between two glass substrates, and a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm cross each other on the lower glass substrate. The thin film transistor TFT formed at the intersection of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm is in response to a scan signal from the gate lines GL1 to GLn. The data from DLm is supplied to the liquid crystal cell Clc.

To this end, the gate electrode of the thin film transistor TFT is connected to the gate lines GL1 to GLn, and the source electrode is connected to the data lines DL1 to DLm. The drain electrode of the thin film transistor TFT is connected to the pixel electrode of the liquid crystal cell Clc.

In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line, or may be formed between the liquid crystal cell Clc and a separate common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to each pixel area in which the thin film transistors TFT are formed, and the gate lines GL1 to GLn border each other. And a black matrix covering the data lines DL1 to DLm, the thin film transistor TFT, and the like, and a common electrode covering all of them.

The gate driver 110 supplies a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 130. These multiple scan signals cause the multiple gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronization signal. The gate driver 110 may include a plurality of gate driver integrated circuits.

The data driver 120 generates a plurality of pixel data voltages whenever any one of the gate lines GL1 to GLn is enabled in response to the data control signals DCS from the timing controller 130. And a plurality of data lines DL1 to DLm on the liquid crystal display panel 100. The data driver 120 may include a plurality of data driver integrated circuits.

The timing controller 130 may enable data synchronization and synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown). The gate control signal GCS for controlling the gate driver 110 and the data control signal DCCS for controlling the data driver 120 are generated using the signal DE and the clock signal CLK.

In addition, the timing controller 130 arranges the image data Data input from an external system and supplies the sorted data to the data driver 120.

The gate voltage generator 140 generates a gate voltage using the power voltage Vdd supplied from a power supply (not shown) and supplies the gate voltage to the gate driver 110.

The common voltage generator 150 generates the common voltage Vcom by using the power voltage Vdd supplied from the power supply, and uses the common voltage Vcom as a common electrode of the liquid crystal display panel 100. Supply.

In this case, the timing controller 130, the gate voltage generator 140, and the common voltage generator 150 may be connected to the power supply unit on a data printed circuit board (not shown) on which the data driver 120 is mounted. In addition, it can be arranged.

FIG. 2 is a view schematically illustrating a part of the liquid crystal display of FIG. 1.

As shown in FIGS. 1 and 2, the liquid crystal display includes a liquid crystal display panel 100 in which a plurality of gate lines GL and a plurality of data lines DL are arranged, and the data lines DL. The first data driver integrated circuit 120a, the timing controller 130 of FIG. 1, the gate voltage generator 140, and the common voltage generator 150 of FIG. 1 are disposed. And a data printed circuit board 124 attached to one surface of the liquid crystal display panel 100.

The liquid crystal display panel 100 includes a thin film transistor array substrate 101 and a color filter substrate 103.

The thin film transistor array substrate 101 intersects the gate lines GL which are regularly spaced apart in the lateral direction and the data lines DL which are regularly spaced apart in the longitudinal direction intersect with each other, and the gate lines that cross each other. Pixels partitioned between the GLs and the data line DL are defined. The pixels are arranged on the thin film transistor array substrate 101 in a matrix form.

In addition, first and second gate driver integrated circuits 110a and 110b may be formed in the non-display area of the thin film transistor array substrate 101 to supply scan signals to the plurality of gate lines GL.

The color filter substrate 103 has red, green, and blue color filters formed at positions corresponding to the pixels, and a black matrix for preventing color interference of light passing through the color filter is formed outside the color filter. And a common electrode for applying an electric field to the liquid crystal layer together with the pixel electrode of the thin film transistor array substrate.

A pixel electrode and a common electrode are provided on an inner surface of the thin film transistor array substrate 101 and the color filter substrate 103 to drive the liquid crystal molecules of the liquid crystal layer by a voltage difference between the pixel electrode and the common electrode. The luminance of the image displayed on the liquid crystal display panel 100 is changed according to the size of the image information applied to the pixels.

In this case, the liquid crystal display panel 100 and the data printed circuit board 124 are electrically and physically connected to each other through a flexible printed circuit board (FPC) 128.

A first data driver integrated circuit 120a constituting the data driver 120 illustrated in FIG. 1 is mounted on the data printed circuit board 124, and a plurality of data lines DL electrically connected to the plurality of data lines DL. The data link line 125 is formed.

The plurality of data link lines 125 may be disposed between an output terminal of the first data driver integrated circuit 120a and a data line DL of the liquid crystal display panel 100 to provide the first data driver integrated circuit 120a. And an output terminal of the < RTI ID = 0.0 >) < / RTI >

In addition, a first LOG signal line 160 is formed on the data printed circuit board 124 and the flexible printed circuit board 128. The first LOG signal line 160 extends from the data printed circuit board 124 and the flexible printed circuit board 128 to be formed at one edge of the non-display area of the thin film transistor array substrate 101. The first LOG signal line 160 formed at one edge of the non-display area of the thin film transistor array substrate 101 is electrically connected to the first gate driver integrated circuit 110a.

In addition, a second LOG signal line 170 is formed between the first and second gate driver integrated circuits 110a and 110b in the non-display area of the thin film transistor array substrate 101.

The first LOG signal line 160 receives control signals and a clock signal from a timing controller (130 of FIG. 1) mounted on the data printed circuit board 124. In addition, the first LOG signal line 160 may include a gate voltage from a gate voltage generator (140 in FIG. 1) mounted on the data printed circuit board 124 and a power voltage from a power supply unit (not shown). Provide ground voltage.

The first LOG signal line 160 provides various signals (control signals and clock signals) and driving voltages (gate voltage, power supply voltage, and ground voltage) to the first gate driver integrated circuit 110a. The gate line GL electrically connected to the one gate driver integrated circuit 110a is driven. At the same time, the first LOG signal line 160 supplies the various signals and driving voltages to the second LOG signal line 170 electrically connected to the first gate driver integrated circuit 110a.

The second LOG signal line 170 is formed between the first gate driver integrated circuit 110a and the second gate driver integrated circuit 110b. In detail, the second LGO signal line 170 may include a gate link line electrically connecting the first and second gate driver integrated circuits 110a and 110b to the gate line GL of the liquid crystal display panel 100. It is formed in the gate link portion where 115 is located. In this case, the second LOG signal line 170 may be formed of a double metal layer due to the limited area of the gate link unit.

3 is a cross-sectional view of the second LOG signal line of FIG. 2.

As shown in FIGS. 2 and 3, the second LOG signal line 170 may include a first metal layer 170a formed on the thin film transistor array substrate 101 and a gate insulation formed on the first metal layer 170a. A layer 105, a second metal layer 170b formed on the gate insulating layer 105 and electrically connected to the first metal layer 170a, and a protective layer 107 formed on the second metal layer 170b. ).

The first metal layer 170a of the second LOG signal line 170 is formed of the same material as the gate line GL of the liquid crystal display panel 100 of FIG. 2 through the same process, and the second metal layer 170b. The same material as that of the data line DL of the liquid crystal display panel 100 is formed through the same process.

The second metal layer 170b formed on the gate insulating layer 105 by exposing a portion of the gate insulating layer 105 formed on the first metal layer 170a through an etching process is exposed through the etching process. Is electrically connected).

The gate insulating layer 105 and the protective layer are formed after the protective layer 107 is formed so that the second LOG signal line 170 of the double metal layer is formed in the same process as the pixel area of the liquid crystal display panel 100. A portion of the gate 107 may be etched to expose a portion of the gate insulating layer 105 to electrically connect the first and second metal layers 170a and 170b.

As such, when the second LOG signal line 170 formed in the gate link part having the limited area is formed of a double metal layer, the thickness of the second LOG signal line 170 becomes thicker than that of the conventional LOG signal line, thereby increasing the cross-sectional area. Will increase. When the cross-sectional area of the second LOG signal line 170 increases, various signals (control signals and clock signals) provided through the first LOG signal line 160 and the first gate driver integrated circuit 110a according to line resistances. And distortion of the driving voltages (gate voltage, power supply voltage, and ground voltage) are reduced.

Thus, the liquid crystal display according to the present invention can improve the display quality of the liquid crystal display panel 100. In addition, the liquid crystal display device according to the present invention is characterized by the various signals (control signals and clock signals) and driving voltages (gate voltage, power voltage and ground voltage) provided to the first and second LOG signal lines 160 and 170. The transmission efficiency can be improved.

4 is a cross-sectional view of the second LOG signal line of FIG. 2 formed according to another exemplary embodiment.

2 and 4, the second LOG signal line 270 according to another embodiment may include a first metal layer 270a and a first metal layer 270a formed on the thin film transistor array substrate 101. ) Is formed on the entire surface of the substrate 101, the gate insulating layer 205 formed on the substrate 101, the protective layer 207 formed on the gate insulating layer 205, and the protective layer 207. And a second metal layer 270b electrically connected to 270a.

The first metal layer 270a of the second LOG signal line 270 is formed of the same material as the gate line GL of the liquid crystal display panel 100 of FIG. 2 through the same process, and the second metal layer 270b. ) Is formed of the same material as the pixel electrode included in the pixel area of the liquid crystal display panel 100 through the same process.

A portion of the first metal layer 270a of the second LOG signal line 270 is exposed to the gate insulating layer 205 and the protective layer 207 sequentially formed on the first metal layer 270a through an etching process. And is electrically connected to the second metal layer 270b formed on the protective layer 207 through the exposed portion.

When the second LOG signal line 270 formed in the gate link part having the limited area is formed of a double metal layer including the first and second metal layers 270a and 270b electrically connected to the second LOG signal line 270, the second LOG signal line 270 is formed. The thicker the thickness of), the larger the cross-sectional area. When the cross-sectional area of the second LOG signal line 270 increases, various signals (controls) provided through the first LOG signal line 160 (FIG. 2) and the first gate driver integrated circuit (110a of FIG. 1) may be controlled according to line resistance. The distortion of the signal and the clock signal) and the driving voltage (gate voltage, power supply voltage and ground voltage) are reduced.

Thus, the liquid crystal display according to the present invention can improve the display quality of the liquid crystal display panel 100. In addition, the liquid crystal display according to the present invention is a device for controlling various signals (control signals and clock signals) and driving voltages (gate voltage, power voltage and ground voltage) provided to the first and second LOG signal lines 160 and 270. The transmission efficiency can be improved.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic view of a portion of the liquid crystal display of FIG. 1; FIG.

3 is a cross-sectional view of the second LOG signal line of FIG. 2;

4 is a cross-sectional view of the second LOG signal line of FIG. 2 formed in accordance with another embodiment.

Claims (5)

A liquid crystal display panel divided into a display area in which liquid crystal cells are arranged in a matrix and a non-display area except for the display area; A plurality of gate driver integrated circuits disposed on one side of the non-display area to drive the plurality of gate lines; A plurality of data driver integrated circuits located on the other side of the non-display area to drive the plurality of data lines; A printed circuit board providing a driving signal and a driving voltage to the gate and the data driver integrated circuit; A flexible printed circuit board relaying between the liquid crystal panel and the printed circuit board; A first LOG signal formed over the non-display area of the printed circuit board, the flexible printed circuit board, and the liquid crystal panel to provide the driving signal and the driving voltage to a first gate driver integrated circuit among the plurality of gate driver integrated circuits; line; And And a second LOG signal line formed between the plurality of gate driver integrated circuits formed in the non-display area to provide a driving signal and a driving voltage provided from the first gate driver integrated circuit to a next gate driver integrated circuit. And the second LOG signal lines are formed in a dual structure including first and second metal layers. According to claim 1, The first metal layer of the second LOG signal line is formed through the same process with the same material as the plurality of gate lines, and the second metal layer is formed through the same process with the same material as the plurality of data lines. LCD display device. According to claim 1, And an insulating layer between the first and second metal layers of the second LOG signal line. The method of claim 3, And first and second metal layers of the second LOG signal line are electrically connected to each other by exposing a portion of the insulating layer. According to claim 1, And the second LOG signal line is formed in a link portion in which gate link lines connecting the plurality of gate lines and the plurality of gate driver integrated circuits of the non-display area are arranged.

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