KR20050001248A - Liquid crystal display - Google Patents

Abstract

PURPOSE: An LCD device is provided to minimize voltage drop of gate driving voltages and delay and distortion of gate driving signals by directly transmitting the gate driving voltages or the gate driving signals to gate tape carrier packages(TCPs) through conductive tapes of low resistance or tapes with conductive patterns of low resistance. CONSTITUTION: An LCD device includes an LCD panel(410) having first and second substrates bonded to each other so that one short side and one long side of the first substrate are protruded to be greater than those of the second substrate, a plurality of gate TCPs(422) connected to the one short side of the first substrate, gate driving integrated circuits loaded in the gate TCPs, a plurality of data TCPs(432) connected to the one long side of the first substrate, data driving integrated circuits(433) loaded in the data TCPs, first line-on-glass lines(441A) loaded in an edge area where the one long side of the first substrate meets its one short side, a data printed circuit board(431) supplying image data to the data driving integrated circuits loaded in the data TCPs and supplying gate driving voltages and gate driving signals to the first line-on-glass lines through the data TCPs, gate signal lines(442,443) loaded in the gate TCPs, transmitting the gate driving voltages and the gate driving signals transmitted from the first line-on-glass lines to the gate driving integrated circuits, and a connecting means such as conductive tapes(450) connected to at least one of the gate signal lines, transmitting at least one of the gate driving voltages and the gate driving signals to its adjacent gate TCPs.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly to a line-on-glass in a line-on-glass (LOG) type liquid crystal display in which a gate printed circuit board (PCB) is removed. The present invention relates to a liquid crystal display device to stabilize driving voltages or control signals transmitted through wires.

In general, among the screen display devices that display image information on the screen, the thin-film flat panel display device has been the subject of intensive development in recent years because of its advantages of being light and easy to use anywhere. In particular, liquid crystal displays have high resolution and are fast in reaction speeds sufficient to realize moving images, and thus are the most active studies.

The principle of the liquid crystal display device is to use the optical anisotropy and polarization properties of the liquid crystal. That is, by artificially adjusting the alignment direction of liquid crystal molecules having directionality using polarization, light can be transmitted and blocked by optical anisotropy according to the alignment direction of the liquid crystal. This application is used as a display device. Currently, an active matrix liquid crystal display in which thin film transistors and pixel electrodes connected thereto are arranged in a matrix manner is most commonly used because it provides excellent image quality. Looking at the structure of a general liquid crystal display device in detail as follows.

On the color filter substrate of the liquid crystal display, red, green, and blue color filters are repeatedly disposed at positions of the pixels. A black matrix is formed in a mesh shape between the color filters. A common electrode is formed on the color filter.

On the thin film transistor array substrate of the liquid crystal display, pixel electrodes are arranged at positions of pixels designed in a matrix manner. Gate lines are formed along the horizontal direction of the pixel electrode, and data lines are formed along the vertical direction. In one corner of the pixels, a thin film transistor for driving the pixel electrode is formed. The gate electrode of the thin film transistor is connected to the gate line, and the source electrode of the thin film transistor is connected to the data line.

The gate pad part and the data pad part are formed at one end of the gate lines and the data lines.

The gate driver and the data driver are combined with the liquid crystal display panel to drive the liquid crystal display panel configured as described above.

The gate driver includes a plurality of integrated circuits (ICs) to apply a scan signal to the gate pad unit, and the data driver includes a plurality of ICs to provide image information to the data pad unit. Is authorized.

In general, the data driver ICs and the gate driver ICs are mounted on a tape carrier package (TCP) and connected to a liquid crystal display panel in a tap automated bonding (TAB) manner.

The data driver ICs and the gate driver ICs receive external control signals and DC voltages through signal lines of a printed circuit board (PCB) connected to TCP.

That is, the data driving ICs are connected in series through signal lines mounted on the data PCB, and are supplied with image information, control signals, and driving voltages applied from an external timing controller and a power supply.

The gate driving ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals and driving voltages applied from an external timing controller and a power supply.

1 is an exemplary view showing a general liquid crystal display device, and as shown therein, a liquid crystal display panel 110; Gate TCPs 122 connected between one side of the liquid crystal display panel 110 and the gate PCB 121; Gate driver ICs 123 mounted on the gate TCPs 122, respectively; Data TCPs 132 connected between the long side of one side of the liquid crystal display panel 110 and the data PCB 131; Data driver ICs 133 mounted on the data TCPs 132, respectively.

The liquid crystal display panel 110 is bonded to face the thin film transistor array substrate 111 and the color filter substrate 112 to have a constant cell gap, and a liquid crystal layer is formed at the cell gap.

One short side and one long side of the thin film transistor array substrate 111 protrude from the color filter substrate 112, and a gate pad portion and a data pad portion are provided in the protruding region of the thin film transistor array substrate 111. In addition, an image display unit 113 is provided in an area where the thin film transistor array substrate 111 and the color filter substrate 112 face each other.

In the image display unit 113 of the thin film transistor array substrate 111, a plurality of gate lines 120 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 130 are arranged in a vertical direction. It is connected to the data pad part. Accordingly, the gate lines 120 and the data lines 130 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersection thereof.

The image display unit 113 of the color filter substrate 112 includes a color filter of red, green, and blue colors which are separated and applied for each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 111.

Gate driver ICs 123 are mounted on the gate TCP 122, and input pads 124 and output pads 125 electrically connected to the gate driver ICs 123 are formed.

The input pads 124 of the gate TCP 122 are electrically connected to the gate PCB 121, and the output pads 125 are electrically connected to the gate pad portion of the thin film transistor array substrate 111.

The gate driving ICs 123 sequentially supply scan signals to the gate lines 120 of the liquid crystal display panel 110.

Meanwhile, data driver ICs 133 are mounted on the data TCP 132 and input pads 134 and output pads 135 electrically connected to the data driver ICs 133 are formed.

The input pads 134 of the data TCP 132 are electrically connected to the data PCB 131, and the output pads 135 are electrically connected to the data pad part of the thin film transistor array substrate 111.

The data driver ICs 133 convert image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 130 of the liquid crystal display panel 110.

Connectors 126 and 136 are formed in the gate PCB 121 and the data PCB 131, respectively, to control and drive the control signals through a flexible printed circuit (150, hereinafter, FPC) or other cable. Voltages are supplied.

However, the liquid crystal display configured as described above forms connectors 126 and 136 on the gate PCB 121 and the data PCB 131, respectively, and supplies control signals and driving voltages through the FPC 150 from the outside. The following problems arise because of receiving.

First, as the connectors 126 and 136 are formed on the thin gate PCB 121 and the data PCB 131, the thickness of the liquid crystal display is inevitably increased by the thickness of the connectors 126 and 136, thereby making the liquid crystal display thinner. It becomes a factor to inhibit.

Second, as the FPC 150 for electrically connecting the connectors 126 and 136 is provided, the number of processes for manufacturing the liquid crystal display is increased, which increases the manufacturing cost of the liquid crystal display.

Therefore, the wirings for supplying control signals and driving voltages to the gate PCB 121 and the data PCB 131 are mounted in the outer dummy region of the thin film transistor array substrate 111 to thereby connect the connectors 126 and 136. A line-on-glass liquid crystal display is proposed in which FPCs 150 are not required.

FIG. 2 is an exemplary view showing a typical line-on-glass type liquid crystal display device, and as shown therein, a liquid crystal display panel 210; A plurality of gate TCPs 222 connected between one short side of the liquid crystal display panel 210 and the gate PCB 221; Gate driver ICs 223 mounted on the gate TCPs 222, respectively; A plurality of data TCPs 232 connected between the long side of one side of the liquid crystal display panel 210 and the data PCB 231; Data driver ICs 233 mounted on the data TCPs 232, respectively.

The liquid crystal display panel 210 is bonded to face the thin film transistor array substrate 211 and the color filter substrate 212 so as to have a constant cell gap, and a liquid crystal layer is formed in the cell gap.

One short side and one long side of the thin film transistor array substrate 211 protrude from the color filter substrate 212, and a gate pad portion and a data pad portion are provided in the protruding region of the thin film transistor array substrate 211. Also, an image display unit 213 is provided in an area where the thin film transistor array substrate 211 and the color filter substrate 212 face each other.

In the image display unit 213 of the thin film transistor array substrate 211, a plurality of gate lines 220 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 230 are arranged in a vertical direction. It is connected to the data pad part. Accordingly, the gate lines 220 and the data lines 230 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersection thereof.

The image display unit 213 of the color filter substrate 212 includes a color filter of red, green, and blue colors which are separated and applied for each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 211.

The gate pad part and the data pad part provided at one short side and one long side of the thin film transistor array substrate 211 protruding from the color filter substrate 212 are formed to correspond to the image display unit 213.

Accordingly, a corner region where one short side and one long side of the thin film transistor array substrate 211 meet is a dummy region which is not used for any purpose. However, in the line-on-glass type liquid crystal display, the LOG wiring ( 241 are formed to supply control signals and driving voltages supplied from the outside to the gate PCB 221 from the data PCB 231.

Therefore, the connectors 126 and 136 of FIG. 1 need not be formed in the gate PCB 221 and the data PCB 231, and a flexible plate cable 150 for electrically connecting the connectors 126 and 136 needs to be formed. There is no.

Data driver ICs 233 are mounted on the data TCP 232, and input pads 234 and output pads 235 which are electrically connected to the data driver ICs 233 are formed.

The input pads 234 of the data TCP 232 are electrically connected to the data PCB 231, and the output pads 235 are electrically connected to the data pad portion of the thin film transistor array substrate 211. Accordingly, the data driver ICs 233 convert image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 230 of the liquid crystal display panel 210.

Gate signal transmission lines 243 are further formed on the data TCPs 232, and LOG signal lines 243 formed on the first data TCP 232 are mounted on the thin film transistor array substrate 211. 241 are electrically connected. The gate signal transmission lines 243 formed on the first data TCP 232 transmit gate control signals and gate driving voltages supplied from a timing controller and a power supply unit to the LOG lines 241.

Meanwhile, gate driver ICs 223 are mounted on the gate TCP 222, and input pads 224 and output pads 225 electrically connected to the gate driver ICs 223 are formed.

The input pads 224 of the gate TCP 222 are electrically connected to the gate PCB 221, and the output pads 225 are electrically connected to the gate pad portion of the thin film transistor array substrate 211.

Gate signal transmission lines 242 are further formed on the gate TCPs 222, and LOG signal transmission lines 242 formed on the first gate TCP 222 are mounted on the thin film transistor array substrate 211. And electrically connected to 241. Gate signal transmission lines 242 formed on the first gate TCP 222 are gate control signals and gate driving voltages supplied from the data PCB 231 through the gate signal transmission lines 243 and the LOG lines 241. Are transferred to the gate PCB 221.

Signal lines and power lines are formed on the gate PCB 221 to transmit the gate control signals and gate driving voltages to the input pads 224 of the gate TCP 222.

Accordingly, the gate driving ICs 223 receive the gate control signals and the gate driving voltages from the input pads 224 to receive the scan signals, that is, the gate high voltage signal Vgh and the gate low voltage signal Vgl, and the gate line 220. ) Sequentially.

On the other hand, the LOG wirings 241 may include a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground signal GND, and a power voltage signal Vdd supplied from an external power supply unit. The same DC voltage signals and gate control signals such as a gate start pulse GSP, a gate shift clock GSC, and a gate enable signal GOE supplied from an external timing controller are transmitted. In the process of forming the gate lines 220 or the data lines 230 on the 211 is formed by patterning at the same time.

As described above, the gate PCB 221 of the line-on-glass type liquid crystal display simply transmits gate control signals and gate driving voltages applied from the data PCB 231 to the gate TCPs 222. do.

However, in recent years, a LOG is configured to additionally configure gate signal transmission lines in the gate TCPs 222 and to connect the gate signal transmission lines in the gate TCPs 222 on the thin film transistor array substrate 211. Line-on-glass type liquid crystal display from which the gate PCB 221 is removed by additionally mounting wirings to transfer gate control signals and gate driving voltages applied from the data PCB 231 to the gate TCPs 222. The device was developed.

FIG. 3 is an exemplary view showing a line-on-glass type liquid crystal display device in which a gate PCB is removed, and as shown therein, a liquid crystal display panel 310; A plurality of gate TCPs 322 connected to one side of the liquid crystal display panel 310; Gate driver ICs 323 mounted on the gate TCPs 322, respectively; A plurality of data TCPs 332 connected between one long side of the liquid crystal display panel 310 and a data PCB 331; Data driver ICs 333 mounted to the data TCPs 332, respectively.

In the liquid crystal display panel 310, the thin film transistor array substrate 311 and the color filter substrate 312 are bonded to each other with a predetermined cell gap, and a liquid crystal layer is formed at the cell gap.

One short side and one long side of the thin film transistor array substrate 311 protrude from the color filter substrate 312, and a gate pad portion and a data pad portion are provided in the protruding region of the thin film transistor array substrate 311. Also, an image display unit 313 is provided in an area where the thin film transistor array substrate 311 and the color filter substrate 312 face each other.

In the image display unit 313 of the thin film transistor array substrate 311, a plurality of gate lines 320 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 330 are arranged in a vertical direction. It is connected to the data pad part. Therefore, the gate lines 320 and the data lines 330 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersections thereof.

The image display unit 313 of the color filter substrate 312 includes a color filter of red, green, and blue colors separated and applied to each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 311.

Meanwhile, LOG wirings 341 are formed in an edge region where one short side and one long side of the thin film transistor array substrate 311 meet to drive gates from the data PCB 331 to control signals and driving voltages supplied from the outside. Supply to IC 323.

Data driver ICs 333 are mounted on the data TCPs 332, and input pads 334 and output pads 335 electrically connected to the data driver ICs 333 are formed.

The input pads 334 of the data TCPs 332 are electrically connected to the data PCB 331, and the output pads 335 are electrically connected to the data pad portion of the thin film transistor array substrate 311. Accordingly, the data driver ICs 333 convert image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 330 of the liquid crystal display panel 310.

Gate signal transmission wirings 343 are further formed on the data TCPs 332, and LOG signal transmission lines 343 formed on the first data TCP 332 are mounted on the thin film transistor array substrate 311. 341) electrically. The gate signal transmission lines 343 formed on the first data TCP 332 transmit gate control signals and gate driving voltages supplied from a timing controller and a power supply unit to the LOG lines 341.

On the other hand, gate driver ICs 323 are mounted on the gate TCP 322, and gate signal transmission wirings 342 and output pads 325 electrically connected to the gate driver ICs 323 are formed.

The gate signal transmission lines 342 supply gate control signals and gate driving voltages supplied from the LOG lines 341 to the gate driving ICs 323. In this case, the gate control signals and the gate driving voltages are mounted on the respective gate TCPs 322 through LOG wirings 341 mounted on the thin film transistor array substrate 311 in a space where the respective gate TCPs 322 are spaced apart. The gate signal transmission lines 342 are transmitted.

The output pads 325 of the gate TCPs 322 are electrically connected to the gate pad part of the thin film transistor array substrate 311.

Accordingly, the gate driving ICs 323 receive gate control signals and gate driving voltages from the gate signal transmission lines 342 to receive a scan signal, that is, a gate high voltage signal Vgh and a gate low voltage signal Vgl. Sequentially supply to (320).

On the other hand, the LOG wirings 341 may include a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground signal GND, and a power voltage signal Vdd supplied from an external power supply. The same DC voltage signals and gate control signals such as a gate start pulse GSP, a gate shift clock GSC, and a gate enable signal GOE supplied from an external timing controller are transmitted. In the process of forming the gate lines 320 or the data lines 330 on the 311 is formed by patterning at the same time.

However, the liquid crystal display device having the conventional gate PCB removed as described above is formed of a metal material having high resistance values in the LOG lines 341 mounted on the thin film transistor array substrate 311.

That is, the LOG lines 341 are formed by simultaneously patterning a metal having the same material as the gate lines 320 or the data lines 330 in the process of forming the gate lines 320 or the data lines 330. The resistivity value (0.046) of the AlNd material is formed of a large metal material.

In addition, the LOG lines 341 mounted on the short side edges of the thin film transistor array substrate 311 in the space where the gate TCPs 322 are spaced apart are patterned to be finely spaced in a very narrow space.

Accordingly, the LOG wirings 341 have a high resistance value, and thus the gate high voltage signal Vgh, the gate low voltage signal Vgl, the common voltage signal Vcom, and the ground signal GND transmitted through the LOG wirings 341. The voltage drop of the DC voltage signals, such as the power supply voltage signal Vdd, is severely generated, which causes a problem of poor image quality or malfunction of the liquid crystal display.

In addition, gate control signals such as a gate start pulse GSP, a gate shift clock GSC, and a gate enable signal GOE transmitted through the LOG lines 341 are delayed or affect adjacent LOG lines 341. There is a problem in that the image quality is deteriorated as cross-talk or flicker occurs in the image displayed through the liquid crystal display.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to drive voltages transmitted through line-on-glass wires in a line-on-glass type liquid crystal display in which a gate PCB is removed. The present invention provides a liquid crystal display device capable of minimizing the voltage drop of the transistor and minimizing the delay and distortion of control signals transmitted through the line-on-glass lines.

1 is an exemplary view showing a general liquid crystal display device.

2 is an exemplary view showing a typical line-on-glass type liquid crystal display device.

3 is an exemplary view showing a line-on-glass type liquid crystal display with the gate PCB removed.

4 is an exemplary view showing a liquid crystal display device according to a first embodiment of the present invention.

Fig. 5 is an exemplary view showing another example in which the conductive tape is connected in Fig. 4;

6 is an exemplary view showing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 7 is an exemplary view showing another example in which a tape provided with a conductive pattern is connected in FIG. 6; FIG.

*** Explanation of symbols for main parts of drawing ***

410 liquid crystal display panel 411 thin film transistor array substrate

412: color filter substrate 413: image display unit

420: gate line 422: gate TCP

423: gate drive IC 425: output pad

430: data line 431: data PCB

432: data TCP 433: data drive IC

434: input pad 435: output pad

441A: 1st LOG wiring 441B: 2nd LOG wiring

442,443: gate signal transmission wiring 450: conductive tape

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal display panel in which a first substrate and a second substrate are bonded to each other so that one short side and one long side of the first substrate protrude relative to the second substrate; A plurality of gate tape carrier packages connected to one short side of the first substrate; Gate driver integrated circuits mounted on the gate tape carrier packages; A plurality of data tape carrier packages connected to one long side of the first substrate; Data driver integrated circuits mounted in the data tape carrier packages; First line-on-glass wirings mounted on corner regions where one long side and one short side of the first substrate meet each other; Supplying image information to data driving integrated circuits mounted in the data tape carrier packages, and supplying gate driving voltages and gate driving signals to the first line-on-glass wirings through the data tape carrier packages. A data printed circuit board; Gate signal transfer wirings mounted on the gate tape carrier packages to transfer gate driving voltages and gate driving signals transmitted from the first line-on-glass wirings to gate driving integrated circuits; And connection means connected to at least one gate signal transmission line mounted on the gate tape carrier packages to transmit at least one of the gate driving voltages and the gate driving signals to adjacent gate tape carrier packages. It is characterized by.

As the connection means, at least one conductive tape or a tape provided with at least one conductive pattern may be applied.

The liquid crystal display according to the present invention as described above will be described in detail with reference to the accompanying drawings.

FIG. 4 is an exemplary view showing a liquid crystal display device according to a first embodiment of the present invention, as shown in FIG. 4; A plurality of gate TCPs (422) connected to one side of the liquid crystal display panel (410); Gate driver ICs 423 mounted on the gate TCPs 422, respectively; A plurality of data TCPs 432 connected between one long side of the liquid crystal display panel 410 and a data PCB 431; The data driver ICs 433 are respectively mounted on the data TCPs 432.

The liquid crystal display panel 410 is composed of a thin film transistor array substrate 411 and a color filter substrate 412 bonded to each other with a predetermined cell gap, and a liquid crystal layer is formed in the cell gap.

One short side and one long side of the thin film transistor array substrate 411 protrude from the color filter substrate 412, and a gate pad part and a data pad part are provided in the protruding region of the thin film transistor array substrate 411. In addition, an image display unit 413 is provided in an area where the thin film transistor array substrate 411 and the color filter substrate 412 face each other.

In the image display unit 413 of the thin film transistor array substrate 411, a plurality of gate lines 420 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 430 are arranged in a vertical direction. It is connected to the data pad part. Accordingly, the gate lines 420 and the data lines 430 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersection thereof.

The image display unit 413 of the color filter substrate 412 includes a color filter of red, green, and blue colors separated and applied to each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 411.

On the other hand, first LOG wiring 441A is formed in a corner region where one short side and one long side of the thin film transistor array substrate 411 meet, and control signals and driving voltages supplied from the outside are transferred from the data PCB 431. Supply to gate driving ICs 423.

Data driver ICs 433 are mounted on the data TCPs 432, and input pads 434 and output pads 435 that are electrically connected to the data driver ICs 433 are formed.

The input pads 434 of the data TCPs 432 are electrically connected to the data PCB 431, and the output pads 435 are electrically connected to the data pad portion of the thin film transistor array substrate 411. Accordingly, the data driver ICs 433 convert the image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 430 of the liquid crystal display panel 410.

Gate signal transmission lines 443 are further formed on the data TCPs 432, and the first LOG on which the gate signal transmission lines 443 formed on the first data TCP 432 are mounted on the thin film transistor array substrate 411. It is electrically connected to the wirings 441A.

The gate signal transmission lines 443 formed on the first data TCP 432 transfer gate control signals and gate driving voltages supplied from a timing controller and a power supply to the first LOG lines 441A.

On the other hand, gate driver ICs 423 are mounted on the gate TCP 422, and gate signal transfer wirings 442 and output pads 425 are formed to be electrically connected to the gate driver ICs 423.

The gate signal transmission lines 442 supply gate control signals and gate driving voltages supplied from the first LOG lines 441A to the gate driving ICs 423. In this case, the gate control signals and the gate driving voltages are applied to the respective gate TCPs 422 through the second LOG wiring 441B mounted on the thin film transistor array substrate 411 in the space where the respective gate TCPs 422 are spaced apart. The mounted gate signal transmission lines 442 are transmitted.

The output pads 425 of the gate TCPs 422 are electrically connected to the gate pad part of the thin film transistor array substrate 411.

Accordingly, the gate driving ICs 423 receive gate control signals and gate driving voltages from the gate signal transmission lines 442 to receive a scan signal, that is, a gate high voltage signal Vgh and a gate low voltage signal Vgl. Sequentially feed lines 420.

The first and second LOG wires 441A and 441B and the gate signal transmission wires 442 and 443 may be provided with a gate high voltage signal Vgh, a gate low voltage signal Vgl, and a common voltage signal Vcom supplied from an external power supply. And DC voltage signals such as ground signal GND and power voltage signal Vdd, gate start pulse GSP, gate shift clock GSC, and gate enable signal GOE supplied from an external timing controller. The same gate control signals are transmitted, and the first and second LOG wires 441A and 441B are simultaneously patterned in the process of forming gate lines 420 or data lines 430 on the thin film transistor array substrate 411. It is formed.

Meanwhile, at least one conductive tape 450 connected to at least one gate signal transmission line 442 mounted on the gate TCPs 422 is provided between the gate TCPs 422. In this case, one or more conductive tapes 450 may be provided in consideration of driving conditions and process conditions of the liquid crystal display.

The conductive tapes 450 directly transmit at least one of gate driving voltages or gate driving signals transmitted to the respective gate TCPs 422 through the second LOG wiring 441B to the gate TCPs 422. In this case, the gate driving voltages or gate driving signals directly transmitted to the gate TCPs 422 through the conductive tapes 450 may include the gate high voltage signal Vgh, the gate low voltage signal Vgl, the common voltage signal Vcom, and the ground. DC voltage signals such as the signal GND and the power supply voltage signal Vdd, and gate control signals such as the gate start pulse GSP, the gate shift clock GSC, and the gate enable signal GOE may be applied.

The conductive tapes 450 are formed by simultaneously patterning a metal having the same material as the gate lines 420 or the data lines 430 on the thin film transistor array substrate 411 in the space where the gate TCPs 422 are spaced apart. The resistance value is lower than that of the second LOG lines 441B.

Accordingly, the voltage drop of the gate driving voltages directly transmitted to the gate TCPs 422 through the conductive tapes 450 may be minimized, and may be directly transmitted to the gate TCPs 422 through the conductive tapes 450. It is possible to minimize delay and distortion of the gate driving signals.

The number of second LOG wires 441B may be reduced by directly transmitting some of gate driving voltages or gate driving signals to the gate TCPs 422 through the conductive tapes 450. The line widths and the spacing intervals of the two LOG lines 441B can be widened to minimize the voltage drop of the gate driving voltages transmitted to the gate TCPs 422 through the second LOG lines 441B. The delay and distortion of the gate driving signals transmitted to the gate TCPs 422 through the 2 LOG lines 441B can be minimized.

On the other hand, the conductive tapes 450 are formed in the number corresponding to the gate signal transmission lines 442 so that all the gate driving voltages and the gate driving signals can be directly transmitted to the gate TCPs 422. The second LOG lines 441 may not be formed on the thin film transistor array substrate 411 in the space where the gate TCPs 422 are spaced apart from each other.

In addition, the conductive tapes 450 are connected to at least one gate signal transmission wiring 442 mounted on the gate TCPs 422 between the gate TCPs 422 as shown in the exemplary diagram of FIG. Each gate TCP 422 may be connected to at least one gate signal transmission line 422 in a region in which gate driving voltages and gate driving signals are input and output.

FIG. 6 is a diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention. As shown in FIG. 6, at least one conductive pattern 551 is provided instead of the conductive tapes 450 shown in FIG. 4. Tape 550 may be applied.

The conductive patterns 551 included in the tape 550 are connected to at least one gate signal transmission line 442 mounted on the gate TCPs 422 between the gate TCPs 422 to connect the second LOG lines 441B. Are directly transmitted to the gate TCPs 422 through at least one of the gate driving voltages or the gate driving signals transmitted to the respective gate TCPs 422. In this case, the gate driving voltages or gate driving signals directly transmitted to the gate TCPs 422 through the conductive patterns 551 provided on the tape 550 are the gate high voltage signal Vgh, the gate low voltage signal Vgl, and the common. DC voltage signals such as voltage signal Vcom, ground signal GND, power supply voltage signal Vdd, and gates such as gate start pulse GSP, gate shift clock GSC, and gate enable signal GOE. Control signals can be applied.

The conductive patterns 551 of the tape 550 are made of the same material as the gate lines 420 or the data lines 430 on the thin film transistor array substrate 411 in the space where the gate TCPs 422 are spaced apart. The resistance value is lower than that of the second LOG lines 441B formed by simultaneously patterning metal.

Accordingly, the voltage drop of the gate driving voltages directly transmitted to the gate TCPs 422 through the conductive patterns 551 provided on the tape 550 may be minimized, and the conductive patterns provided on the tape 550 may be minimized. Delays and distortions of the gate driving signals transmitted directly to the gate TCPs 422 through 551 may be minimized.

The number of second LOG wires 441B is transmitted by directly transmitting some of gate driving voltages or gate driving signals to the gate TCPs 422 through the conductive patterns 551 of the tape 550. Since the width of the second LOG lines 441B can be widened, the widths of the gate driving voltages transmitted to the gate TCPs 422 through the second LOG lines 441B can be reduced. The delay and distortion of the gate driving signals transmitted to the gate TCPs 422 through the second LOG wires 441B may be minimized.

On the other hand, the conductive patterns 551 of the tape 550 are formed in the number corresponding to the gate signal transmission lines 442 so that all gate driving voltages and gate driving signals are directly transmitted to the gate TCPs 422. In this case, the second TCP lines 441 may not be formed on the thin film transistor array substrate 411 in the space where the gate TCPs 422 are spaced apart from each other.

In addition, the conductive patterns 551 included in the tape 550 transmit at least one gate signal mounted on the gate TCPs 422 between the gate TCPs 422, as shown in the exemplary diagram of FIG. 7. The wiring 442 may be connected to the gate TCP 422, and may be connected to at least one gate signal transmission line 422 in the region where the gate driving voltages and the gate driving signals are input and output.

The tapes 550 including the conductive tapes 450 and the conductive patterns 551 illustrated in FIGS. 4 to 7 may be applied to the data TCPs 432 as well as the gate TCPs 422.

The liquid crystal display device according to the first and second embodiments of the present invention may be applied to various liquid crystal modes, for example, a liquid crystal through a vertical electric field or a horizontal electric field. It can be applied to the manner of driving.

As described above, the liquid crystal display according to the present invention uses the low resistance conductive tapes connected to the gate signal transmission lines mounted on the gate TCPs, or the gate driving voltages or the gate driving through the tapes having the low resistance conductive patterns. By directly transmitting the signals to the gate TCPs, the voltage drop of the gate driving voltages can be minimized and the delay and distortion of the gate driving signals can be minimized.

Further, the gate driving voltages or the gate driving signals are directly transmitted to the gate TCPs through the low resistance conductive tapes or the tapes having the low resistance conductive patterns on the thin film transistor array substrate. Since the number of second LOG wires mounted on the wires can be reduced, the line width and the spacing of the second LOG wires can be widened, thereby minimizing the voltage drop of the gate driving voltages transmitted to the gate TCPs. In addition, delay and distortion of the gate driving signals can be minimized.

Therefore, it is possible to prevent malfunction of the liquid crystal display device and to prevent image quality defects such as cross-talk and flicker from occurring in the image displayed through the liquid crystal display device.

Claims (10)

A liquid crystal display panel in which a first substrate and a second substrate are bonded to each other so that one side short side and one long side of the first substrate protrude relative to the second substrate; A plurality of gate tape carrier packages connected to one short side of the first substrate; Gate driver integrated circuits mounted on the gate tape carrier packages; A plurality of data tape carrier packages connected to one long side of the first substrate; Data driver integrated circuits mounted in the data tape carrier packages; First line-on-glass wirings mounted on corner regions where one long side and one short side of the first substrate meet each other; Supplying image information to data driving integrated circuits mounted in the data tape carrier packages, and supplying gate driving voltages and gate driving signals to the first line-on-glass wirings through the data tape carrier packages. A data printed circuit board; Gate signal transfer wirings mounted on the gate tape carrier packages to transfer gate driving voltages and gate driving signals transmitted from the first line-on-glass wirings to gate driving integrated circuits; And connection means connected to at least one gate signal transmission line mounted on the gate tape carrier packages to transmit at least one of the gate driving voltages and the gate driving signals to adjacent gate tape carrier packages. Liquid crystal display device characterized in that. The gate tape carrier package of claim 1, wherein the gate tape carrier packages are mounted in spaced spaces to transfer some of the gate driving voltages and the gate driving signals from a front gate tape carrier package to a rear gate tape carrier package. And second line-on-glass wires for transmitting. The gate driving circuit of claim 1, wherein the connection unit is connected to at least one gate signal transmission line between the gate tape carrier packages, and a gate input voltage and gate driving signals are input to each gate tape carrier package. And at least one gate signal transmission line in a region where the signal is formed. The liquid crystal display device according to claim 1, wherein the connection means is at least one conductive tape. 5. The liquid crystal display of claim 4, wherein the conductive tape has a number corresponding to gate signal transmission lines. 6. The liquid crystal display device according to claim 1, wherein the connection means is a tape provided with at least one conductive pattern. 7. The liquid crystal display of claim 6, wherein the conductive pattern has a number corresponding to gate signal transmission lines. A liquid crystal display panel; A plurality of tape carrier packages connected to one side of the liquid crystal display panel; Drive integrated circuits mounted on the tape carrier packages; First line-on-glass wires mounted on a corner of the liquid crystal display panel to transmit driving voltages and driving signals; Signal transmission wirings mounted on the tape carrier packages to transmit driving voltages and driving signals transmitted from the first line-on-glass wirings to driving integrated circuits; And connecting means connected to at least one signal transmission line mounted on the tape carrier packages to transmit at least one of the driving voltages and the driving signals to adjacent tape carrier packages. Display. 9. The second line of claim 8, wherein the tape carrier packages are mounted in spaces separated from each other to transfer some of the driving voltages and the driving signals from a front tape carrier package to a rear tape carrier package. And on-glass wirings. The liquid crystal display device according to claim 8, wherein the connection means is at least one conductive tape or a tape provided with at least one conductive pattern.