CN108873525A - A kind of measurement circuit of the grid line of array substrate - Google Patents
A kind of measurement circuit of the grid line of array substrate Download PDFInfo
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- CN108873525A CN108873525A CN201810785149.3A CN201810785149A CN108873525A CN 108873525 A CN108873525 A CN 108873525A CN 201810785149 A CN201810785149 A CN 201810785149A CN 108873525 A CN108873525 A CN 108873525A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a kind of measurement circuits of the grid line of array substrate.Array substrate includes the pixel electrode of multiple pixel regions of cascade multiple GOA units, a plurality of clock cable, a plurality of grid line, multiple data lines and grid line and data line cross arrangement restriction；Wherein, clock cable is connected with corresponding GOA unit respectively, and GOA unit is connected with corresponding grid line；Measurement circuit includes testing cushion, and testing cushion is arranged on the color membrane substrates or signal plate except array substrate, and whether the scanning signal that testing cushion is used to test on grid line is abnormal.By the above-mentioned means, the present invention, which does not need progress sliver operation, can test scanning signal, mode is simple, accuracy is high.
Description
Technical field
The present invention relates to field of liquid crystal display, more particularly to a kind of measurement circuit of the grid line of array substrate.
Background technique
Array substrate row driving (Gate Driver On Array, GOA) is collected in array substrate using Array processing procedure
At grid horizontal drive circuit, the gate driving IC originally in array substrate can be saved, reaching reduces production cost and realization
The purpose of narrow frame.
It include cascade multiple GOA units in existing GOA circuit, as shown in fig. 1, n-th grade of GOA unit includes：On
Draw control module 101, pull-up grade transmission module 102, bootstrap capacitor module 103, drop-down maintenance module 104 and pull-down module 105.This
A little module collective effects may be implemented n-th grade of scanning signal Gn and carry out the superior and the subordinate's transmitting in cascade GOA unit.It is specific next
It says, the n-th -2 grades scanning signal Gn-2 are by pulling up after control module 101 is pre-charged n-th grade of common signal point Qn, the
Make n-th grade of scanning signal Gn under n grades of common signal point Qn, bootstrap capacitor module 103 and pull-up 102 collective effect of grade transmission module
Export the current potential namely output high potential of clock signal CK, then, control of the drop-down maintenance module 104 in control signal LC1/LC2
Under system, pull-down module 105 make n-th grade of scanning signal Gn close and be maintained under the control of the n-th+2 grades scanning signal Gn+2
Low potential.
With the increase of panel size and gate driving line number, the series of GOA circuit is also increased accordingly, this is resulted in reality
In the production process of border, panel exception (irregular mura, horizontal band etc.) is easy to appear since the homogeneity of processing procedure has differences
The problem of.Once there is exception in panel, on the one hand it is difficult to confirm whether related to GOA circuit；On the other hand, due to GOA circuit
The superior and the subordinate pass and influence each other, it is also difficult to which directly confirmation is which rank of scanning signal produces exception.So, how accurately to survey
Examination scanning signal becomes urgent problem to be solved.
It is existing test scanning signal method be：By way of sliver, the upper plate CF glass in panel is raised, is led to
It crosses signal plate and applies driving signal to GOA circuit, the output end for pricking GOA unit at different levels in GOA circuit is removed with probe, to obtain
The scanning signal of GOA unit outputs at different levels.In this way, it is rather troublesome to go through all these formalities for one side sliver, is easy to produce during sliver
Raw spot, pollution device, cause test result inaccurate, on the other hand, probe is easy to puncture metal, leads to not obtain just
True test waveform.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of measurement circuit of the grid line of array substrate, do not need into
The operation of row sliver can test scanning signal, and mode is simple, accuracy is high.
In order to solve the above technical problems, one technical scheme adopted by the invention is that：A kind of test of array substrate is provided
Route, the array substrate include cascade multiple GOA units, a plurality of clock cable, a plurality of grid line, multiple data lines, with
And the pixel electrode of grid line and multiple pixel regions of data line cross arrangement restriction；Clock cable respectively with it is corresponding
GOA unit connection, GOA unit are connected with corresponding grid line, drive of the GOA unit for the clock signal on clock cable
Scanning signal is generated under dynamic on grid line with driving pixel electrode；Measurement circuit includes testing cushion, and testing cushion is arranged in array
On color membrane substrates or signal plate except substrate, whether the scanning signal that testing cushion is used to test on grid line is abnormal.
The beneficial effects of the invention are as follows：The measurement circuit of array substrate of the invention is cascaded by being arranged in array substrate
Multiple GOA units, a plurality of clock cable, a plurality of grid line, multiple data lines and grid line and data line cross arrangement
The pixel electrode of the multiple pixel regions limited；Wherein, clock cable is connected with corresponding GOA unit, GOA unit with it is corresponding
Grid line connection, and by the way that testing cushion is arranged on the color membrane substrates or signal plate except array substrate, from without
Scanning signal can be tested by carrying out sliver operation, and mode is simple, accuracy is high.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of GOA unit in the prior art；
Fig. 2 is the floor map of the measurement circuit of the grid line of the array substrate of first embodiment of the invention；
Fig. 3 is the diagrammatic cross-section of the measurement circuit of the grid line of the array substrate of first embodiment of the invention；
Fig. 4 is the circuit diagram of testing cushion and the first embodiment of pixel electrode in measurement circuit shown in Fig. 2；
Fig. 5 is control signal timing diagram when measurement circuit shown in Fig. 2 works normally；
Fig. 6 is control signal timing diagram when array substrate shown in Fig. 2 works normally；
Fig. 7 is the circuit diagram of testing cushion and the second embodiment of pixel electrode in measurement circuit shown in Fig. 2；
Fig. 8 is the structural schematic diagram of the measurement circuit of the grid line of the array substrate of second embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that the described embodiments are merely a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It is the measurement circuit of the grid line of the array substrate of first embodiment of the invention please also refer to Fig. 2 and Fig. 3, Fig. 2
Floor map, Fig. 3 is the diagrammatic cross-section of the measurement circuit of the grid line of the array substrate of first embodiment of the invention.Such as
Shown in Fig. 2, array substrate 20 includes cascade multiple GOA units 21, a plurality of clock cable CK, a plurality of grid line S (N), more
The pixel electrode for multiple pixel regions that data line D (M) and grid line S (N) and data line D (M) cross arrangement limit
22。
Clock cable CK is connected with corresponding GOA unit 21 respectively, and GOA unit 21 connects with corresponding grid line S (N)
It connects, GOA unit 21 is for generating scanning signal on grid line S (N) under the driving of the clock signal on clock cable CK
Gn is with driving pixel electrode 22.
In the present embodiment, the opposite sides of array substrate 20 is arranged in cascade multiple GOA units 21, along array substrate
Two GOA units 21 of 20 setting substantially symmetrical about its central axis drive same grid line S (N).That is, in the present embodiment, GOA
The GOA circuit that unit 21 is formed is bilateral single crystal drive circuit.In other embodiments, the GOA that cascade multiple GOA units 21 are formed
Circuit can also be two-sided dual-drive circuit or unilateral single crystal drive circuit, and invention is not limited thereto.
In the present embodiment, multiple clock cable CK include the first clock cable CK1, second clock signal wire CK2,
Third clock cable CK3 and the 4th clock cable CK4.In other embodiments, the quantity of multiple clock cable CK
It can be different from four in the present embodiment, such as when GOA circuit is unilateral single crystal drive circuit, multiple clock cable CK can be with
It only include the first clock cable CK1, second clock signal wire CK2.
In the present embodiment, the first clock cable CK1 is connect with first order GOA unit 21, second clock signal wire CK2
It is connect with second level GOA unit 21, third clock cable CK3 is connect with third level GOA unit 21, the 4th clock cable
CK4 is connect with fourth stage GOA unit 21, and then, the first clock cable CK1 is connect with level V GOA unit 21, second clock
Signal wire CK2 is connect with the 6th grade of GOA unit 21, and third clock cable CK3 is connect with the 7th grade of GOA unit 21, when the 4th
Clock signal wire CK4 is connect with the 8th grade of GOA unit 21 ... ..., and the rest may be inferred.
Please also refer to Fig. 3, measurement circuit includes testing cushion 31, and the color film except array substrate 20 is arranged in testing cushion 31
On substrate 40, testing cushion 31 is used for when array substrate operation irregularity, and whether the scanning signal Gn in test grid line S (N) is different
Often.Wherein, testing cushion 31 is multiple, and testing cushion 31 is corresponded and overlapped with pixel electrode 22.
Please also refer to Fig. 4, testing cushion 31 is electrically connected with one end of capacitor C, the other end electricity of pixel electrode 22 and capacitor C
Connection.Wherein, capacitor C is specially the plate condenser formed between pixel electrode 22 and testing cushion 31.
In the present embodiment, testing cushion 31 is a part of color membrane substrates side public electrode 41.It changes for an angle, test
Color membrane substrates side public electrode 41 on pad 31 and color membrane substrates 40 is integrally formed.
In the present embodiment, when 20 operation irregularity of array substrate, controlling the clock signal on clock cable CK is the
Whether the pulse signal of one frequency is abnormal to test scanning signal Gn in testing cushion 31 by capacitor C；When 20 work of array substrate
When making normal, the pulse signal that the clock signal on clock cable CK is second frequency is controlled so that GOA unit 21 is in clock
Scanning signal Gn is generated under the driving of signal CK normally to show with driving pixel electrode 22；Wherein, first frequency is higher than the second frequency
Rate.
As shown in figure 5, when 20 operation irregularity of array substrate, the first clock cable CK1, second clock signal wire CK2,
Apply the pulse signal of first frequency on third clock cable CK3, the 4th clock cable CK4.Preferably, first frequency
Pulse signal is the pulse signal of hyperfrequency, wherein first frequency is that hyperfrequency refers to that first frequency is more than or equal to 120Hz.This
The technical staff in field is appreciated that due to forming capacitor C between pixel electrode 22 and testing cushion 31, when on clock cable CK
Clock signal be hyperfrequency pulse signal when, the scanning signal Gn generated on grid line S (N) namely pixel electrode 22 is
Therefore the AC signal of one high frequency can be can detecte identical as on pixel electrode 22 by capacitor C in testing cushion 31
Scanning signal Gn, without carrying out sliver operation can efficiently and accurately judge whether scanning signal Gn abnormal, into
And the abnormal whether related with GOA circuit of array substrate can be confirmed.
In the present embodiment, the first clock cable CK1, second clock signal wire CK2, third clock cable CK3,
The pulse signal non-overlap of the first frequency applied on four clock cable CK4 is arranged.That is, the first clock cable
CK1, second clock signal wire CK2, third clock cable CK3, the 4th clock cable CK4 pulse signal sequentially generate,
The pulse spacing of same serial number is arranged, and overlapping region is not present.
Wherein, in order to reduce the interference between signal, when the arteries and veins that the clock signal on clock cable CK is first frequency
When rushing signal, the signal on data line D (M) is earth signal, and color membrane substrates side public electrode 41 is in vacant state.
As shown in fig. 6, when array substrate 20 is working properly, the first clock cable CK1, second clock signal wire CK2,
Apply the pulse signal of second frequency on third clock cable CK3, the 4th clock cable CK4.Preferably, second frequency is
The pulse signal of low frequency, second frequency for example can be 60Hz.
Wherein, the first clock cable CK1, second clock signal wire CK2, third clock cable CK3, the 4th clock letter
The pulse signal of the second frequency applied on number line CK4 partly overlaps setting, to realize the preliminary filling between scanning signal Gn at different levels
Electricity.
Wherein, when the clock signal on clock cable CK is the pulse signal of second frequency, on data line D (M)
Signal is the digital signal of high frequency, and color membrane substrates side public electrode 41 is identical as the current potential of array substrate side public electrode, locates
In reference potential.
Preferably, array substrate 20 can further include DBS public electrode 23, wherein DBS public electrode 23 be
The top of data line D (M) is covered with the cabling of ITO (tin indium oxide), and the width of these ITO cablings is slightly wider than data line D (M),
And it connects the public electrode wire of array substrate and is formed.When array substrate works normally, the electric field that these ITO cablings are formed can
So that liquid crystal molecule keeps the state not deflected, to play the purpose of shading, and then data line D in liquid crystal display panel can be saved
(M) black matrix" of corresponding position increases aperture opening ratio.
It is arranged between testing cushion 31 and pixel electrode 22 please also refer to 7, DBS public electrode 23, wherein pixel electrode
22, DBS public electrode 23 and testing cushion 31 overlap.Capacitor C includes first capacitor C1 and the second capacitor C2, testing cushion 31 with
One end of first capacitor C1 connects, and the other end of first capacitor C1 is connect with DBS public electrode 23 respectively, DBS public electrode 23
It is connected with one end of the second capacitor C2, the other end of the second capacitor C2 is electrically connected with pixel electrode 22.Wherein, when array substrate 20
When operation irregularity, control the clock signal on clock cable CK be the pulse signal of first frequency with by first capacitor C1 and
Whether the second capacitor C2 tests scanning signal Gn in testing cushion 31 abnormal.Wherein, in order to reduce the interference between signal, at that time
When clock signal on clock signal wire CK is the pulse signal of first frequency, the signal on data line D (M) is earth signal, color film
Substrate-side public electrode 41, DBS public electrode 23 are in vacant state.
It will be understood to those skilled in the art that no matter whether array substrate includes DBS public electrode 23, in this hair
Within bright protection scope.
Fig. 8 is the structural schematic diagram of the measurement circuit of the grid line of the array substrate of second embodiment of the invention.Fig. 8 and figure
The difference of the measurement circuit of the grid line of the array substrate of first embodiment shown in 2 is：Array substrate 20 ' includes virtual number
According to line 30 '.Measurement circuit includes testing cushion 31 ', and testing cushion 31 ' is arranged on signal plate 50.Wherein, signal plate 50 is arranged in battle array
Except column substrate 20 ', for providing driving signal, data-signal etc. to array substrate 20 '.
Wherein, virtual data line 30 ' and data line D (M) is arranged in parallel, and virtual data line 30 ' is electrically connected with testing cushion 31 '
It connects.
Wherein, when 20 ' operation irregularity of array substrate, pass through laser machine welding virtual data line 30 ' and grid line S (N)
Lap position so that grid line S (N) and virtual data line 30 ' are connected, and then test S (N) on grid line by testing cushion 31 '
Scanning signal Gn it is whether abnormal.
In the present embodiment, virtual data line 30 ' includes the first virtual data line 301 ' and the second virtual data line 302 ',
The opposite sides of array substrate, the first virtual data line 301 ' and the second virtual data is arranged in cascade multiple GOA units 21
The GOA unit 21 in left side is arranged in respectively close to the setting of GOA unit 21 of two sides namely the first virtual data line 301 ' for line 302 '
Between data line D (1), the second virtual data line 302 ' is arranged between the GOA unit 21 on right side and data line D (M).Test
Pad 31 ' includes the first testing cushion 311 ' and the second testing cushion 312 '.Wherein, the first virtual data line 301 ' and the first testing cushion
311 ' electrical connections, the second virtual data line 302 ' and the electrical connection of the second testing cushion 312 '.In other embodiments, virtual data line
30 ' quantity may also be distinct from that shown in Fig. 8, such as virtual data line can be only one, a virtual data line setting
Between GOA unit 21 and data line D (1) or it is arranged between GOA unit 21 and data line D (M).
For example, when whether the scanning signal G4 for needing to test grid line S (4) output is abnormal, by the first virtual number
It can measure scanning signal G4's according to the lap position welding of line 301 ' and grid line S (4), and then by the first testing cushion 311 '
Signal waveform.
It will be understood to those skilled in the art that testing scanning signal Gn using this kind of mode, do not need to carry out sliver yet
Operation can efficiently and accurately judge whether scanning signal Gn is abnormal.
In the present embodiment, when array substrate 20 ' works normally, the current potential of virtual data line 30 ' is equal to array substrate
The current potential of side public electrode, to reduce interference of the virtual data line 30 ' to other signals line.
In the present embodiment, when array substrate 20 ' is working properly or testing cushion 31 ' is used to test scanning signal,
Signal waveform is controlled as shown in fig. 6, for the sake of brief, details are not described herein.
It will be understood to those skilled in the art that no matter whether array substrate includes DBS public electrode 23, in this hair
Within bright protection scope.
The beneficial effects of the invention are as follows：The measurement circuit of the grid line of array substrate of the invention passes through in array substrate
Cascade multiple GOA units, a plurality of clock cable, a plurality of grid line, multiple data lines and grid line and data line are set
The pixel electrode for multiple pixel regions that cross arrangement limits；Wherein, clock cable is connected with corresponding GOA unit respectively,
GOA unit is connected with corresponding grid line, and color membrane substrates or signal by testing cushion being arranged in except array substrate
On plate, scanning signal can be tested without carrying out sliver operation, mode is simple, accuracy is high.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (10)
1. a kind of measurement circuit of the grid line of array substrate, which is characterized in that the array substrate includes cascade multiple GOA
Unit, a plurality of clock cable, a plurality of grid line, multiple data lines and the grid line and the data line cross arrangement
The pixel electrode of the multiple pixel regions limited；
Wherein, the clock cable is connected with the corresponding GOA unit respectively, the GOA unit and the corresponding grid
Polar curve connection, the GOA unit under the driving of the clock signal on the clock cable on the grid line for producing
Raw scanning signal is to drive the pixel electrode；
The measurement circuit includes testing cushion, and color membrane substrates or signal plate except the array substrate are arranged in the testing cushion
On, whether the scanning signal that the testing cushion is used to test on the grid line is abnormal.
2. measurement circuit according to claim 1, which is characterized in that when the testing cushion is arranged on the color membrane substrates
When, the testing cushion be it is multiple, the testing cushion is corresponded and is overlapped with the pixel electrode, the testing cushion with it is electric
One end of appearance is electrically connected, and the pixel electrode is electrically connected with the other end of the capacitor.
3. measurement circuit according to claim 2, which is characterized in that the array substrate further comprises DBS common electrical
Pole, the capacitor include first capacitor and the second capacitor, wherein DBS public electrode setting is in the testing cushion and described
Between pixel electrode, the pixel electrode, the DBS public electrode and the testing cushion are overlapped, the testing cushion and institute
One end electrical connection of first capacitor is stated, the other end of the first capacitor is electrically connected with DBS public electrode respectively, and the DBS is public
The electrical connection of one end of common electrode and second capacitor, the other end of second capacitor are electrically connected with the pixel electrode.
4. measurement circuit according to claim 2 or 3, which is characterized in that
When the array substrate operation irregularity, the arteries and veins that the clock signal on the clock cable is first frequency is controlled
Whether rush signal abnormal to test the scanning signal in the testing cushion by the capacitor；
When the array substrate is working properly, controls the pulse that the clock signal on the clock cable is second frequency and believe
Number so that the GOA unit generates the scanning signal under the driving of the clock signal to drive the pixel electrode normal
Display；
Wherein, the first frequency is higher than the second frequency.
5. measurement circuit according to claim 4, which is characterized in that the testing cushion is color membrane substrates side public electrode
A part.
6. measurement circuit according to claim 5, which is characterized in that when the clock signal on the clock cable
For first frequency pulse signal when, the signal on the data line is earth signal, and color membrane substrates side public electrode is in
Vacant state.
7. measurement circuit according to claim 4, which is characterized in that when the clock signal on the clock cable
For first frequency pulse signal when, pulse signal non-overlap setting on a plurality of clock cable.
8. measurement circuit according to claim 4, which is characterized in that the first frequency is more than or equal to 120Hz.
9. measurement circuit according to claim 1, which is characterized in that when the testing cushion is arranged on the signal plate,
The array substrate further comprises virtual data line, and the virtual data line is arranged in parallel with the data line, described virtual
Data line is electrically connected with the testing cushion；
When the array substrate operation irregularity, pass through the overlapping bit of virtual data line and the grid line described in laser machine welding
It sets so that the grid line is connected with the virtual data line, and then is tested by the testing cushion described on the grid line
Whether scanning signal is abnormal.
10. measurement circuit according to claim 9, which is characterized in that when the cascade GOA unit is arranged in array base
When the opposite sides of plate, the virtual data line be two, the testing cushion be two, two virtual data lines respectively with
Two testing cushions are correspondingly connected with, and two virtual data lines are arranged respectively close to the cascade GOA unit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810785149.3A CN108873525B (en) | 2018-07-17 | 2018-07-17 | A kind of measurement circuit of the grid line of array substrate |
| PCT/CN2018/107557 WO2020015163A1 (en) | 2018-07-17 | 2018-09-26 | Testing circuit of gate lines of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810785149.3A CN108873525B (en) | 2018-07-17 | 2018-07-17 | A kind of measurement circuit of the grid line of array substrate |
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| Publication Number | Publication Date |
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| CN108873525A true CN108873525A (en) | 2018-11-23 |
| CN108873525B CN108873525B (en) | 2019-09-20 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110187531A (en) * | 2019-05-29 | 2019-08-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and its detection mode |
| CN110246443A (en) * | 2019-06-18 | 2019-09-17 | 京东方科技集团股份有限公司 | Array substrate and its test method |
| CN110288931A (en) * | 2019-06-12 | 2019-09-27 | 北海惠科光电技术有限公司 | The undesirable detection method of grid line, display panel and readable storage medium storing program for executing |
| CN110428760A (en) * | 2019-06-27 | 2019-11-08 | 重庆惠科金渝光电科技有限公司 | A kind of display panel test method, display panel and display device |
| CN110570795A (en) * | 2019-09-04 | 2019-12-13 | 深圳市华星光电技术有限公司 | Test method of display panel |
| CN110796975A (en) * | 2019-11-25 | 2020-02-14 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN111240113A (en) * | 2020-03-11 | 2020-06-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2021189486A1 (en) * | 2020-03-27 | 2021-09-30 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2021195933A1 (en) * | 2020-03-31 | 2021-10-07 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
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