CN107689366B - 半导体芯片和具有半导体芯片的半导体封装体 - Google Patents

半导体芯片和具有半导体芯片的半导体封装体 Download PDF

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CN107689366B
CN107689366B CN201710933867.6A CN201710933867A CN107689366B CN 107689366 B CN107689366 B CN 107689366B CN 201710933867 A CN201710933867 A CN 201710933867A CN 107689366 B CN107689366 B CN 107689366B
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semiconductor
structural body
semiconductor substrate
semiconductor chip
penetration
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CN107689366A (zh
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李承烨
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SK Hynix Inc
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Abstract

本发明公开了一种半导体芯片，包括半导体基板和屏蔽层，半导体基板具有一个表面、背对一个表面的另一表面和形成在一个表面上的集成电路，屏蔽层形成在半导体基板中以对应于另一表面。

Description

半导体芯片和具有半导体芯片的半导体封装体
本申请是申请号为201310384376.2、申请日为2013年8月29日、发明名称为“半导体芯片和具有半导体芯片的半导体封装体”的中国专利申请的分案申请。本申请的母案申请要求了于2012年8月30提交韩国知识产权局的韩国专利申请第10-2012-95311号的优先权，其全文引用结合于此。
技术领域
本发明总体上涉及半导体装置，更具体涉及适合于改善EMI(电磁干扰)特性的半导体芯片以及具有该半导体芯片的半导体封装体。
背景技术
当前，电子工业倾向于以低成本制造高可靠性的产品，从而实现体轻、小型化、高速运行、多功能和高性能。封装装配技术被认为是用于实现设计这样产品的目的的重要技术之一。封装装配技术是要保护具有形成于其中的集成电路的半导体芯片不受外部环境的影响，以及易于将半导体芯片安装到基板，从而可保证半导体芯片的运行可靠性。
近来，由于半导体装置的运行速度的增加，半导体芯片中产生大量的电磁波，使得采用半导体芯片制造的电子设备的可靠性可能下降。就是说，具有高速运行的集成电路的半导体芯片中不可避免地产生电磁波。在这样的半导体芯片用于电子设备中的情况下，由于从半导体芯片产生的电磁波被辐射，在安装到该电子设备的其它电子产品中可能导致电磁干扰(EMI)。结果，在其中使用半导体芯片的电子设备中可能产生电磁噪声或诸如误操作的失效，由此电子设备的可靠性可能劣化。具体地，随着半导体芯片的响应速度增加并且半导体芯片具有高容量，归因于电磁波辐射的电磁干扰问题变得严重。
作为阻挡这样的电磁波的方法，已经提出在将半导体芯片组装成半导体封装体之后在半导体封装体的模制部件上形成屏蔽层的方法。然而，即使在此情况下，产生的问题也在于半导体封装体的尺寸由于存在形成于半导体封装体的模制部件上的屏蔽层而增加。另外，不可能解决半导体封装体中半导体芯片之间以及半导体芯片与基板之间的电磁干扰问题。
发明内容
各种实施例涉及适于改善EMI(电磁干扰)特性且实现重量轻、薄型、紧凑和小型化的半导体芯片。
再者，实施例涉及具有半导体芯片的半导体封装体。
在实施例中，半导体芯片包括：半导体基板，具有一个表面、背对该一个表面的另一表面、以及形成在该一个表面上的集成电路；以及屏蔽层，形成在半导体基板中以对应于该另一表面。
半导体芯片还可包括穿透半导体基板和屏蔽层并且与集成电路电连接的第一穿透电极；以及使第一穿透电极和屏蔽层彼此电隔离的电介质层。半导体基板可分成其中设置有集成电路的核心区域和限定在核心区域之外的周边区域，并且第一穿透电极可形成在核心区域中。
半导体芯片还可包括穿过半导体基板和屏蔽层并且与屏蔽层电连接的第二穿透电极。半导体基板可分成其中设置有集成电路的核心区域和限定在核心区域之外的周边区域，并且第二穿透电极形成在周边区域中。多个第二穿透电极可沿着核心区域的边缘形成。
屏蔽层可形成为与半导体基板的另一表面以预定距离分离开。与此不同，屏蔽层形成为暴露在半导体基板的另一表面上。
半导体芯片还可包括：附加屏蔽层，其形成在半导体基板的侧表面上且与屏蔽层电连接；以及形成在附加屏蔽层和半导体基板的侧表面之间的电介质层。
半导体基板还可具有凹槽，其限定在半导体基板的侧表面上，使一个表面和另一表面彼此连接并使屏蔽层暴露。半导体芯片还可包括：形成在凹槽中且与屏蔽层电连接的附加屏蔽层；以及形成在屏蔽层和半导体基板之间的电介质层。
在实施例中，半导体封装体包括半导体芯片，该半导体芯片包括：半导体基板，具有一个表面、背对一个表面的另一表面、以及形成在一个表面上的集成电路；以及屏蔽层，形成在半导体基板中以对应于另一表面。
半导体芯片还可包括：第一穿透电极，穿透半导体基板和屏蔽层并且与集成电路电连接；以及第二穿透电极，穿透半导体基板和屏蔽层并且与屏蔽层电连接。
半导体封装体还可包括结构体，该结构体具有与第一穿透电极电连接的连接电极和与第二穿透电极电连接的接地电极。
半导体芯片可设置为使半导体基板的另一表面面对结构体而半导体基板的一个表面背对结构体。与此不同，半导体芯片可设置为使半导体基板的一个表面面对结构体而半导体基板的另一表面背对结构体。
多个半导体芯片可借由第一和第二穿透电极被堆叠。半导体封装体还可包括结构体，其具有与堆叠的半导体芯片当中最下面的半导体芯片的第一穿透电极电连接的连接电极和与最下面半导体芯片的第二穿透电极电连接的接地电极。
堆叠的半导体芯片可设置为使得每个半导体基板的另一表面面对结构体而每个半导体基板的一个表面背对结构体。与此不同，堆叠的半导体芯片可设置为使得每个半导体基板的一个表面面对结构体而每个半导体基板的另一表面背对结构体。另外，堆叠的半导体芯片当中的最下面的半导体芯片可设置为使得半导体基板的另一表面面对结构体而半导体基板的一个表面背对结构体，而堆叠的半导体芯片当中最上面的半导体芯片可设置为使得半导体基板的一个表面面对结构体而半导体基板的另一表面背对结构体。
附图说明
图1是示出根据实施例的半导体芯片的截面图。
图2是示出图1的半导体芯片的平面图。
图3是示出根据实施例的半导体芯片的截面图。
图4是示出图3的半导体芯片的平面图。
图5是示出根据实施例的半导体芯片的平面图。
图6是示出根据实施例的半导体芯片的平面图。
图7是示出根据实施例的半导体封装体的截面图。
图8是示出根据实施例的半导体封装体的截面图。
图9是示出根据实施例的半导体封装体的截面图。
图10是示出根据实施例的半导体封装体的截面图。
图11是示出根据实施例的半导体封装体的截面图。
图12是示出具有根据实施例的半导体封装体的电子设备的立体图。
图13是示出具有根据实施例的半导体封装体的电子设备的示例的模块图。
具体实施方式
在下文，将参考附图详细描述各种实施例。
这里应理解，附图不必按比例，并且在某些情况下可夸大比例以更加清晰地描述本发明的某些特征。
图1是示出根据实施例的半导体芯片的截面图，而图2是示出图1的半导体芯片的平面图。
在与图1和图2相关的实施例中，半导体芯片10A可包括半导体基板100和屏蔽层200。此外，半导体芯片10A还可包括第一穿透电极300和第二穿透电极400。
半导体基板100可分成核心区域CORE和周边区域PERI，并且可具有一个表面110、另一表面120、侧表面130、集成电路140和接合衬垫150。
一个表面110背对另一表面120，并且侧表面130使一个表面110和另一表面120彼此连接。集成电路140形成在一个表面110上的核心区域CORE中，并且可包括诸如晶体管、电容器和电阻器等用于存储、处理和传输数据的元件。接合衬垫150可以为集成电路140的用于连接到外部的电接触，可形成在一个表面110上的核心区域CORE中。
屏蔽层200可用于阻挡电磁波，从而防止集成电路140中产生的电磁波向外辐射，或者防止外部装置中产生的电磁波进入集成电路140。屏蔽层200可形成在半导体基板100中以对应于半导体基板100的另一表面120，并且可使集成电路140与另一表面120彼此阻隔开。
在相关于图1和图2的实施例中，屏蔽层200可形成为与半导体基板100的另一表面120分离预定距离D。屏蔽层200从顶部看与半导体基板100具有基本上相同的形状，并且根据这样的事实，半导体基板100由屏蔽层200分成两个部分。
尽管在与图1和图2相关的实施例中示出且说明了屏蔽层200可形成为与半导体基板100的另一表面120分离，但是屏蔽层120可形成为接触半导体基板100的另一表面120，并且在此情况下，屏蔽层200在半导体基板100的另一表面120上暴露。
屏蔽层200例如可通过注入工艺向半导体基板100中注入金属或非金属离子穿过半导体基板100的另一表面120而形成。半导体基板100的另一表面120与屏蔽层200之间的距离D可通过离子注入能量控制。金属离子可通过与半导体基板100中包含的半导体物质反应而形成金属物质，并且可包括铜(Cu)、铝(Al)等。非金属离子通过与半导体基板100中包含的半导体物质耦合可产生空穴或额外的电子。由于非金属离子与半导体基板100中包含的半导体物质耦合，因此可形成导电屏蔽层。尽管附图中没有示出，但是电介质层可附加地形成在半导体基板100和屏蔽层200之间。
第一穿透电极300用于从集成电路140输入信号以及输出信号至集成电路140，并且穿透核心区域CORE中的半导体基板100和屏蔽层200，并且与集成电路140电连接。为了使得第一穿透电极300和屏蔽层200彼此电隔离，电介质层310可形成在第一穿透电极300和屏蔽层200之间。
第二穿透电极400用于施加接地电压GND到屏蔽层200。在与图1和图2相关的实施例中，第二穿透电极400穿过周边区域PERI中的半导体基板100和屏蔽层200，并且与屏蔽层200电连接。尽管与图1和图2相关的实施例中示出且说明了第二穿透电极400仅形成在周边区域PERI中，但是第二穿透电极400也可形成在核心区域CORE中。在此情况下，为了使集成电路140和第二穿透电极400彼此电隔离，电介质层(未示出)附加地形成在集成电路140与第二穿透电极400之间。
接地电压GND可通过第二穿透电极400施加到屏蔽层200。根据这样的事实，集成电路140中产生的电磁波被屏蔽层200阻挡，而不向半导体基板100的另一表面120辐射，并且入射到半导体基板100的另一表面120上的电磁波由屏蔽层200阻挡，而不传送到集成电路140。
图3上示出根据实施例的半导体芯片的截面图，而图4是示出图3的半导体芯片的平面图。
参见图3和图4，根据实施例的半导体芯片10B可具有这样的结构，其中附加屏蔽层210可添加到以上参考图1和图2描述的根据实施例的半导体芯片10A。从而，除了附加屏蔽层210之外，根据与图3和图4相关的实施例的半导体芯片10B和根据与图1和图2相关的实施例的半导体芯片10A可具有基本上相同的结构。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的附图标记用于指代相同的构件部分。
参见图3和图4，除了根据与图1和图2相关的实施例的半导体芯片10A的结构之外，半导体芯片10B还可包括附加屏蔽层210。
屏蔽层200可形成为暴露于半导体基板100的侧表面130上。附加屏蔽层210可形成在半导体基板100的侧表面上，并且可与屏蔽层200电连接。
附加屏蔽层210可通过在半导体基板100的侧表面130上沉积金属层而形成。尽管附图中没有示出，但是为了使得附加屏蔽层210与半导体基板100彼此电隔离，电介质层可附加形成在半导体基板100的侧表面与附加屏蔽层210之间。
根据与图3和图4相关的实施例，因为通过半导体基板100的侧表面130辐射或发射的电磁波被附加屏蔽层210阻挡，所以可进一步改善阻挡电磁波的效果。
图5是示出根据实施例的半导体芯片的平面图。
与以上参考图3和图4描述的根据实施例的半导体芯片10B不同，根据与图5相关实施例的半导体芯片10C可具有这样的结构，凹槽160附加限定在半导体基板100上，并且附加屏蔽层210可形成于凹槽160中。因此，除了基板100和附加屏蔽层210之外，根据与图5相关的实施例的半导体芯片10C与根据与图3和图4相关的实施例的半导体芯片10B可具有基本上相同的结构。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的附图标记用于指代相同的构件部分。
参见图5，半导体芯片10C的半导体基板100可具有限定在侧表面130上的凹槽160。附加地，凹槽160可形成在半导体基板100的侧表面130上以彼此连接一个表面110和另一表面120并且暴露屏蔽层210。附加屏蔽层210可形成在凹槽160中并且可与屏蔽层200电连接。
根据参考图5描述的实施例，因为附加屏蔽层210可设置在限定于半导体基板100上的凹槽160中，所以不会引起由于存在附加屏蔽层210而能够增加半导体芯片尺寸的问题，并且因此在实现轻、薄、紧凑和小型化结构方面提供优点。
图6是示出根据实施例的半导体芯片的平面图。
与上面参考图1和图2描述的根据实施例的半导体芯片10A不同，根据与图6相关的实施例的半导体芯片10D具有多个第二穿透电极400沿着核心区域CORE的边缘形成的结构。因此，除了第二穿透电极400之外，根据与图6相关的实施例的半导体芯片10D和根据与图1和图2相关的实施例的半导体芯片10A具有基本上相同的结构。
参见图6，在本实施例中，多个第二穿透电极400沿着核心区域CORE的边缘形成在周边区域PERI中，并且防止电磁波发射和辐射穿过半导体基板100的侧表面130。为了提高阻挡电磁波的效果，可密集地形成第二穿透电极400。
下面，将描述具有上述半导体芯片的半导体封装体。
图7是示出根据实施例的半导体封装体的截面图。
参见图7，在制备了具有屏蔽层200以及第一穿透电极300和第二穿透电极400的半导体芯片10A之后，半导体芯片10A可安装到结构体80上，使得第一穿透电极300与结构体80的连接电极82电连接，而第二穿透电极400可与结构体80的接地电极84电连接。结构体80可包括印刷电路板。在实施例中，半导体芯片10A可设置为使半导体基板100的一个表面110面对结构体80，而半导体基板100的另一表面120背对结构体80。因此，由于半导体芯片10A的集成电路140与半导体封装体的上部由屏蔽层200彼此阻隔开，所以能有利地防止半导体芯片10A与半导体封装体的上部之间的电磁干扰。
导电连接构件90可形成在半导体芯片10A的第一穿透电极300和结构体80的连接电极82之间以及半导体芯片10A的第二穿透电极400和结构体80的接地电极84之间，以使得第一穿透电极300和连接电极82彼此电连接以及第二穿透电极400和接地电极彼此电连接。粘合构件92可形成在半导体芯片10A和结构体80之间以使半导体芯片10A和结构体80彼此粘附。
导电连接构件90可采用包括铜、锡和银中至少一种的金属形成，而粘合构件92可包括非导电膜(NCF)、非导电膏(NCP)、各向异性导电膜(ACF)、各向异性导电膏(ACP)和聚合物中的任何一种。
图8是示出根据实施例的半导体封装体的截面图。
与上面参考图7描述的根据实施例的半导体封装体不同，根据与图8相关的实施例的半导体封装体具有这样的结构，半导体芯片10A设置为使得半导体基板100的另一表面120面对结构体80而半导体基板100的一个表面110背对结构体80。因此，除了半导体芯片10A的布局结构之外，根据与图8相关的实施例的半导体封装体和根据与图7相关的实施例的半导体封装体具有基本上相同的结构。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的附图标记用于指代相同的构件部分。
参见图8，在制备具有屏蔽层200以及第一穿透电极300和第二穿透电极400的半导体芯片10A之后，半导体芯片10A可安装到结构体80上，使得第一穿透电极300与结构体80的连接电极82电连接，而第二穿透电极400与结构体80的接地电极84电连接。在与图8相关的实施例中，半导体芯片10A可设置为使半导体基板100的另一表面120面对结构体80，而半导体基板100的一个表面110背对结构体80。因此，由于半导体芯片10A的集成电路140和结构体80由屏蔽层200彼此阻隔开，所以能有利地防止半导体芯片10A和结构体80之间的电磁干扰。
图9是示出根据实施例的半导体封装体的截面图。
参见图9，在制备多个半导体芯片10Ai至10Aiii(每一个半导体芯片具有屏蔽层200以及第一穿透电极300和第二穿透电极400)之后，另一半导体芯片10Aii可堆叠在一个半导体芯片10Ai上使得另一半导体芯片10Aii的第一穿透电极300和第二穿透电极400与一个半导体芯片10Ai的第一穿透电极300和第二穿透电极400电连接。这样，多个半导体芯片，例如三个半导体芯片10Ai至10Aiii被堆叠。
导电连接构件20可形成在堆叠的半导体芯片10Ai至10Aiii的第一穿透电极300之间以及堆叠的半导体芯片10Ai至10Aiii的第二穿透电极400之间，以电连接上部和下部半导体芯片10Ai至10Aiii的第一穿透电极300和第二穿透电极400。粘合构件30可形成在堆叠的半导体芯片10Ai至10Aiii之间，以使上部和下部半导体芯片10Ai至10Aiii彼此粘附。导电连接构件20可采用包括铜、锡和银中至少一种的金属形成，而粘合构件30可包括非导电膜(NCF)、非导电膏(NCP)、各向异性导电膜(ACF)、各向异性导电膏(ACP)和聚合物中的任何一种。
堆叠的半导体芯片10Ai至10Aiii可安装到结构体80上，使得最下面的半导体芯片10Ai的第一穿透电极300可与结构体80的连接电极82电连接，并且最下面的半导体芯片10Ai的第二穿透电极400可与结构体80的接地电极84电连接。在与图9相关的实施例中，半导体芯片10Ai至10Aiii可设置为使得每个半导体基板100的一个表面110面对结构体80而半导体基板100的另一表面120背对结构体80。因此，由于堆叠的半导体芯片10Ai至10Aiii的集成电路140由屏蔽层200彼此阻隔开，并且最上面的半导体芯片10Aiii的集成电路140与半导体封装体的上部由屏蔽层200彼此阻隔开，所以能有利地防止半导体芯片10Ai至10Aiii之间以及最上面的半导体芯片10Aiii与半导体封装体的上部之间的电磁干扰。
导电连接构件90可形成在最下面的半导体芯片10Ai的第一穿透电极300和结构体80的连接电极82之间以及最下面的半导体芯片10Ai的第二穿透电极400和结构体80的接地电极84之间，以使接最下面的半导体芯片10Ai的第一穿透电极300和结构体80的连接电极82彼此电连，并且最下面的半导体芯片10Ai的第二穿透电极400和结构体80的接地电极84彼此电连接。粘合构件92可形成在最下面的半导体芯片10Ai和结构体80之间以使最下面的半导体芯片10A和结构体80彼此粘附。导电连接构件90可采用包括铜、锡和银中至少一种的金属形成，而粘合构件92可包括非导电膜(NCF)、非导电膏(NCP)、各向异性导电膜(ACF)、各向异性导电膏(ACP)和聚合物中的任何一种。
图10是示出根据实施例的半导体封装体的截面图。
与上面参考图9描述的根据实施例的半导体封装体不同，根据与图10相关的实施例的半导体封装体具有这样的结构，半导体芯片10Ai至10Aiii设置为使得各个半导体基板100的另一表面120面对结构体80而半导体基板100的一个表面110背对结构体80。从而，除了半导体芯片10Ai至10Aiii的布局结构之外，根据与图10相关的实施例的半导体封装体和根据与图9相关的实施例的半导体封装体具有基本上相同的结构。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的附图标记用于指代相同的构件部分。
参见图10，在制备多个半导体芯片10Ai至10Aiii(每一个多个半导体芯片具有屏蔽层200以及第一穿透电极300和第二穿透电极400)之后，另一半导体芯片10Aii可堆叠在一个半导体芯片10Ai上，使得另一半导体芯片10Aii的第一和第二穿透电极300和400与一个半导体芯片10Ai的第一和第二穿透电极300和400电连接。这样，多个半导体芯片，例如三个半导体芯片10Ai至10Aiii被堆叠。
导电连接构件20可形成在堆叠的半导体芯片10Ai至10Aiii的第一穿透电极300之间以及堆叠的半导体芯片10Ai至10Aiii的第二穿透电极400之间，以电连接上部和下部半导体芯片10Ai至10Aiii的第一和第二穿透电极300和400。粘合构件30可形成在堆叠的半导体芯片10Ai至10Aiii之间，以使上部和下部半导体芯片10Ai至10Aiii彼此粘附。
堆叠的半导体芯片10Ai至10Aiii可安装到结构体80上，使得最下面的半导体芯片10Ai的第一穿透电极300与结构体80的连接电极82电连接，并且最下面的半导体芯片10Ai的第二穿透电极400与结构体80的接地电极84电连接。
在与图10相关的实施例中，半导体芯片10Ai至10Aiii可设置为使每个半导体基板100的另一表面120面对结构体80，而半导体基板100的一个表面110背对结构体80。因此，由于堆叠的半导体芯片10Ai至10Aiii的集成电路140由屏蔽层200彼此阻隔开，并且最下面的半导体芯片10Aiii的集成电路140和结构体80由屏蔽层200彼此阻隔开，因此能有利地防止半导体芯片10Ai至10Aiii之间以及最下面的半导体芯片10Aiii和结构体80之间的电磁干扰。
图11是示出根据实施例的半导体封装体的截面图。
参见图11，在制备了多个半导体芯片10Ai至10Aiii(每一个半导体芯片具有屏蔽层200以及第一穿透电极300和第二穿透电极400)之后，另一半导体芯片10Aii堆叠在一个半导体芯片10Ai上，从而另一半导体芯片10Aii的第一穿透电极300和第二穿透电极400可与一个半导体芯片10Ai的第一穿透电极300和第二穿透电极400电连接。这样，堆叠了多个半导体芯片，例如，三个半导体芯片10Ai至10Aiii。
导电连接构件20可形成在堆叠的半导体芯片10Ai至10Aiii的第一穿透电极300之间以及堆叠的半导体芯片10Ai至10Aiii的第二穿透电极400之间，以电连接上部和下部半导体芯片10Ai至10Aiii的第一和第二穿透电极300和400。粘合构件30可形成在堆叠的半导体芯片10Ai至10Aiii之间，以使上部和下部半导体芯片10Ai至10Aiii彼此粘附。
堆叠的半导体芯片10Ai至10Aiii可安装到结构体80上，使得最下面的半导体芯片10Ai的第一穿透电极300可与结构体80的连接电极82电连接，而最下面的半导体芯片10Ai的第二穿透电极400可与结构体80的接地电极84电连接。在与图11相关的实施例中，最下面的半导体芯片10Ai可设置为使得半导体基板100的另一表面120面对结构体80而半导体基板100的一个表面110背对结构体80，而最上面的半导体芯片10Aiii可设置为使得半导体基板100的一个表面110面对结构体80而半导体基板100的另一表面120背对结构体80。因此，由于最下面的半导体芯片10Ai的集成电路140和结构体80由屏蔽层200彼此阻隔开，并且最上面的半导体芯片10Aiii和半导体封装体的上部由屏蔽层200彼此阻隔开，所以能有利地防止半导体芯片10Ai至10Aiii和结构体80之间以及半导体芯片10Ai至10Aiii和半导体封装体的上部之间的电磁干扰。
尽管上面参考图7至11描述的实施例中说明了结构体80可包括印刷电路板，但是应注意结构体80可包括半导体封装体或插入体。
尽管上面参考图7至11示出且说明了半导体封装体可采用图1和图2所示的半导体芯片10A构造，但是本实施例不限于此，并且本领域的普通技术人员应理解，半导体封装体可采用图3至图6所示的半导体芯片10B、10C和10D取代图1和图2所示的半导体芯片10A来构造。
前述的半导体封装体可应用于各种电子设备。
图12是示出具有根据实施例的半导体封装体的电子设备的立体图。
参见图12，根据实施例的半导体封装体可应用于诸如便携式电话的电子设备1000。因为根据实施例的半导体封装体可提供EMI特性被改善且能实现轻、薄、紧凑和小型化结构的优点，所以对改善电子设备1000的性能是有利的。电子设备1000不限于图12所示的便携式电话，而是可包括各种电子设备，例如，移动电子设备、膝上电脑、笔记本电脑、便携式多媒体播放器(PMP)、MP3播放器、便携式摄像机、网络写字板、无线电话、导航仪和个人数字助理(PDA)等。
图13是示出具有根据实施例的半导体封装体的电子设备的示例的模块图。
参见图13，电子系统1300可包括控制器1310、输入/输出单元1320和存储器1330。控制器1310、输入/输出单元1320和存储器1330可通过总线1350彼此连接。总线1350用作数据移动的通路。例如，控制器1310可包括至少一个微处理器、至少一个数字信号处理器、至少一个微控制器和能与这些部件执行相同功能的逻辑装置中的至少任何一种。控制器1310和存储器1330可包括根据本发明的半导体封装体。输入/输出单元1320可包括选自键板、键盘和显示装置等当中的至少一种。存储器1330是用于存储数据的装置。存储器1330可存储由控制器1310执行的指令和/或数据等。存储器1330可包括易失性存储装置和/或非易失性存储装置。另外，存储器1330可由闪存构成。例如，采用本发明技术的闪存可安装到诸如移动终端或台式计算机的信息处理系统。闪存可由固态驱动器(SSD)构成。在此情况下，电子系统1300可在闪存系统中稳定地存储大量的数据。电子系统1300还可包括接口1340，构造为传输数据到通信网络以及从通信网络接收数据。接口1340可为有线类型或无线类型。例如，接口1340可包括天线或者有线或无线收发器。此外，尽管没有示出，但是本领域的技术人员容易理解，电子系统1300可附加地提供有应用芯片集、相机图像处理器(CIS)、输入/输出单元等。
由上面的描述可见，根据实施例，由于屏蔽层可形成在半导体芯片中，不会引起由于存在屏蔽层而可能增加半导体封装体尺寸的问题，所以能够提供具有轻、薄、紧凑和小型化结构的半导体封装体。此外，不仅半导体封装体和外部装置之间的电磁干扰可被防止，而且存在于半导体封装体中的半导体芯片之间以及半导体芯片与下层结构体(例如，印刷电路板、封装体、插入体等)之间的电磁干扰也可被防止，因此可改善EMI特性。
尽管为了示例的目的已经描述了各种实施例，但是本领域的技术人员应理解，在不脱离如所附权利要求中公开的本发明的范围和精神的情况下，各种修改、增加和替代是可能的。

Claims (8)

1.一种包含多个半导体芯片的半导体封装体，半导体芯片中的每一个包括：
半导体基板，所述半导体基板具有一个表面、背对所述一个表面的另一表面，以及所述一个表面上形成的集成电路；
屏蔽层，所述屏蔽层形成在所述半导体基板中，以对应于所述另一表面；
第一穿透电极，所述第一穿透电极穿透所述半导体基板和所述屏蔽层，并且与所述集成电路电连接；以及
第二穿透电极，所述第二穿透电极穿透所述半导体基板和所述屏蔽层，并且与所述屏蔽层电连接，
其中所述多个半导体芯片由所述第一穿透电极和所述第二穿透电极的介质堆叠，
其中所述半导体芯片的第二穿透电极彼此连接并构成所述半导体芯片的接地屏蔽层的接地通路。
2.根据权利要求1所述的半导体封装体，还包括：
结构体，所述结构体具有与所述第一穿透电极电连接的连接电极和与所述第二穿透电极电连接的接地电极。
3.根据权利要求2所述的半导体封装体，其中所述半导体芯片设置为使得所述半导体基板的所述另一表面面对所述结构体，且所述半导体基板的所述一个表面背对所述结构体。
4.根据权利要求2所述的半导体封装体，其中所述半导体芯片设置为使得所述半导体基板的所述一个表面面对所述结构体，且所述半导体基板的所述另一表面背对所述结构体。
5.根据权利要求1所述的半导体封装体，还包括：
结构体，所述结构体具有连接电极和接地电极，所述连接电极与所述堆叠的半导体芯片当中最下面的半导体芯片的所述第一穿透电极电连接，并且所述接地电极与所述最下面的半导体芯片的所述第二穿透电极电连接。
6.根据权利要求5所述的半导体封装体，其中所述堆叠的半导体芯片设置为使得每个半导体基板的所述另一表面面对所述结构体，且每个半导体基板的所述一个表面背对所述结构体。
7.根据权利要求5所述的半导体封装体，其中所述堆叠的半导体芯片设置为使得每个半导体基板的所述一个表面面对所述结构体，且每个半导体基板的所述另一表面背对所述结构体。
8.根据权利要求5所述的半导体封装体，其中所述堆叠的半导体芯片的最下面的半导体芯片设置为使得所述半导体基板的所述另一表面面对所述结构体，且所述半导体基板的所述一个表面背对所述结构体，并且所述堆叠的半导体芯片的最上面的半导体芯片设置为使得所述半导体基板的所述一个表面面对所述结构体，且所述半导体基板的所述另一表面背对所述结构体。
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CN103681551A (zh) 2014-03-26
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CN107689366A (zh) 2018-02-13
CN103681551B (zh) 2017-11-03
KR20140028643A (ko) 2014-03-10

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