CN107665819B - 半导体管芯切割及由此形成的结构 - Google Patents

半导体管芯切割及由此形成的结构 Download PDF

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CN107665819B
CN107665819B CN201710629551.8A CN201710629551A CN107665819B CN 107665819 B CN107665819 B CN 107665819B CN 201710629551 A CN201710629551 A CN 201710629551A CN 107665819 B CN107665819 B CN 107665819B
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sidewall
die
semiconductor
dielectric layers
semiconductor substrate
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CN107665819A (zh
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张富程
黄震麟
陈文明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种示例性方法包括提供晶圆，该晶圆包括第一集成电路管芯、第二集成电路管芯以及位于第一集成电路管芯和第二集成电路管芯之间的划线区。该方法还包括在划线区中形成切口，并且在形成切口之后，使用机械锯切工艺将第一集成电路管芯与第二集成电路管芯完全分离。该切口延伸穿过多个介电层进入到半导体衬底中。本发明实施例涉及半导体管芯切割及由此形成的结构。

Description

半导体管芯切割及由此形成的结构
技术领域
本发明实施例涉及半导体管芯切割及由此形成的结构。
背景技术
由于许多电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断提高，半导体产业经历了快速增长。在大多数情况下，集成密度的改进是由最小部件尺寸的反复减小引起的，这允许将更多的组件集成到给定区域中。随着对缩小的电子器件的需求的增长，已经出现了对更小和更具创造性的半导体管芯封装技术的需求。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，在底部半导体封装件的顶部上堆叠顶部半导体封装件以提供高水平的集成和组件密度。PoP技术通常使得能够在印刷电路板(PCB)上产生具有增强的功能和小的占用面积的半导体器件。
发明内容
根据本发明的一个实施例，提供了一种形成半导体器件的方法，包括：接收晶圆，所述晶圆包括第一集成电路管芯；第二集成电路管芯；以及划线区，位于所述第一集成电路管芯和所述第二集成电路管芯之间；以及在所述划线区中形成切口，其中，所述切口延伸穿过多个介电层至半导体衬底内，以及其中，所述切口包括：位于所述多个介电层与所述半导体衬底之间的界面处的第一宽度；以及位于所述多个介电层的与所述半导体衬底相对的表面处的第二宽度，其中，所述第一宽度与所述第二宽度的比率至少为0.6。
根据本发明的另一实施例，还提供了一种形成半导体器件的方法，包括：从晶圆切割半导体管芯，其中，切割所述半导体管芯包括：使用多个激光束在与所述半导体管芯相邻的划线区中形成切口，其中，所述切口延伸穿过多个介电层并且部分地延伸至半导体衬底内；将锯片与所述切口对准，其中，在所述多个介电层和所述半导体衬底之间的界面处，所述锯片比所述切口更窄；以及使用所述锯片锯穿所述半导体衬底的由所述切口暴露的底部。
根据本发明的又一实施例，还提供了一种半导体器件，包括：第一半导体管芯，其中，所述第一半导体管芯包括：半导体衬底；多个介电层，与所述半导体衬底具有界面；第一侧壁；以及第二侧壁，位于所述第一侧壁下方并且设置在所述第一半导体管芯的与所述第一侧壁相同的一侧上，其中，所述第一侧壁与所述第二侧壁横向间隔开；以及底部填充物，沿着所述第一半导体管芯的所述第二侧壁延伸。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A至图1C示出根据一些实施例的晶圆中的半导体管芯的不同视图；
图2至图5示出根据一些实施例的切割半导体管芯的各个中间步骤的截面图；以及
图6A和图6B示出根据一些实施例的半导体器件封装件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
在特定上下文中描述了各个实施例，即，衬底上晶圆上芯片(CoWoS)封装件中的半导体管芯。然而，各个实施例可应用于其他封装件配置中的半导体管芯切割。
图1A示出根据一些实施例的管芯100的截面图。管芯100可以是半导体管芯并且可以是诸如处理器、逻辑电路、存储器、模拟电路、数字电路、复合信号等任何类型的集成电路。尽管通篇称为管芯，但管芯100是较大晶圆200(参见图1B)的部分时，可能发生对管芯100的一些或全部处理。例如，晶圆200包括多个管芯100(例如，每个管芯具有如相对于图1A所描述的部件)，并且可以沿着相邻管芯100之间的划线区202应用切割工艺以分离管芯100，如下面更详细描述的。
管芯100可以包括衬底102、有源器件104以及位于衬底上方的互连结构106。例如，衬底102可以包括掺杂或未掺杂的块状硅或者绝缘体上半导体(SOI)衬底的有源层。通常，SOI衬底包括形成在绝缘体层上的半导体材料(诸如硅)的层。例如，绝缘层可以是埋氧(BOX)层或氧化硅层。在诸如硅或玻璃衬底的衬底上提供绝缘层。可选地，衬底102可以包括诸如锗的另一元素半导体；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP的合金半导体；或它们的组合。还可以使用诸如多层衬底或梯度衬底的其他衬底。
可以在衬底102的顶面处形成诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等的有源器件104。可以在有源器件104和衬底102上方形成互连结构106。互连结构106可以包括层间介电(ILD)层和/或金属间介电(IMD)层，层间电介质(ILD)和/或金属间电介质(IMD)包含使用任何合适的方法形成的导电部件108(例如，导线和导电通孔)。ILD和IMD层可以包括具有例如低于约4.0的k值的低k介电材料或者具有设置在这种导电部件之间的例如低于约2.0的k值的极低k(ELK)介电材料。在一些实施例中，例如，ILD层和IMD层可以由磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等制成，通过诸如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)的任何合适的方法来形成。
可以通过诸如单镶嵌工艺或双镶嵌工艺的镶嵌工艺形成导电部件108。导电部件108由导电材料(例如，包括铜、铝、钨、它们的组合等)形成，并且导电部件108可以用扩散阻挡层和/或粘附层(未示出)衬里。可以由TaN、Ta、TiN、Ti、CoW等的一层或多层形成扩散阻挡层。互连结构106中的导电部件108电连接各个有源器件104以在管芯100内形成功能电路。通过这种电路提供的功能可以包括存储结构、处理结构、感应器、放大器、功率分布、输入/输出电路等。本领域普通技术人员将理解，所提供的上述实例仅用于说明性目的，以进一步解释各个实施例的应用，并且不意味着以任何方式限制各个实施例。其他电路可以适当地用于给定应用。
还应当注意，一个或多个蚀刻停止层(未示出)可位于ILD层和IMD层的相邻层之间。通常，当形成通孔和/或接触件时蚀刻停止层提供停止蚀刻的机制。蚀刻停止层由具有与相邻层(例如，下面的衬底102和上面的互连结构106)不同的蚀刻选择性的介电材料形成。在实施例中，蚀刻停止层可以由SiN、SiCN、SiCO、CN、它们的组合等形成，可通过CVD或PECVD技术来沉积。
还如图1A所示，互连结构106还包括一个或多个密封环110，密封环110还可以延伸穿过与导电部件108相邻的ILD层和IMD层。密封环110可以为管芯100的部件(例如，导电部件108)提供保护使管芯100的部件(例如，导电部件108)免受在管芯100的处理期间可能存在的水、化学品、残余物和/或污染物的损坏。每个密封环110可以沿着管芯100的外围形成，并且可以形成为围绕管芯100的功能电路区120(例如，管芯100的具有形成在那里的有源器件104和导电部件108的区域)的连续结构，如图1C中提供的管芯100的顶视图所示。在图1C中，示出单个密封环110，但是可以包括多个密封环(例如，参见图1A)。此外，在图1C中，密封环110的形状大致为矩形，但是在其他实施例中，在顶视图中密封环110可以具有不同的形状。如图1B所示，通过划线区202(例如，设置在相邻管芯100的密封环110之间)来分离晶圆200中的管芯100。
再次参考图1A，密封环110可以由导电材料形成。在实施例中，密封环110由与导电部件108相同的材料并且通过相同的工艺同时形成。例如，密封环110可以包括各个ILD和IMD层中的导线部分，其中导电通孔部分连接ILD和IMD层之间的导线部分。
在各个实施例中，密封环110可以与有源器件104电隔离，并且密封环110可以不与有源器件104形成任何功能电路。可以通过最小间隔将密封环110与管芯100的功能电路区119隔开。通过包括密封环110和功能电路之间的最小间隔，可以减小在形成密封环110期间损坏导电部件108的风险。此外，尽管图1A示出停止在衬底102的顶面处的密封环110，但是在其他实施例中，密封环110可以延伸到衬底102内。在一些实施例中，密封环110的底部可以与衬底102中的有源器件区(例如，源极/漏极区104')的底部大致齐平或低于衬底102中的有源器件区(例如，源极/漏极区104')的底部。
管芯100还包括诸如铝焊盘的焊盘114，建立至该焊盘的外部连接。焊盘114可以通过导电部件108提供至有源器件104的电连接。焊盘114位于可称为管芯100的相应有源侧上。在互连结构106上方且在焊盘114的部分上设置钝化膜112。钝化膜112可以包括单个钝化层或多层结构。在一些实施例中，钝化膜112可以包括与下面的ILD层和IMD层(例如，低k电介质)类似的材料。在其他实施例中，钝化膜112可以由诸如氧化硅、未掺杂的硅酸盐玻璃、氮氧化硅等的非有机材料形成。还可以使用其他合适的钝化材料。
可以穿过钝化膜112图案化开口以暴露焊盘114的相应中心部分。焊盘116形成在穿过钝化膜112的开口中，并且可以称为凸块下金属(UBM)116。在所示实施例中，焊盘116形成为穿过钝化膜112中的开口至焊盘114。作为形成焊盘116的实例，在钝化膜112上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。可通过旋涂等形成光刻胶并且可将光刻胶暴露于光从而用于图案化。光刻胶的图案对应于焊盘116和可选地对应于位于钝化膜112上方的密封环110的部分。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中且在晶种层的暴露部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后，去除光刻胶以及去除晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘116。晶种层的剩余部分可以可选地进一步提供位于钝化膜112之上的密封环110的部分。在不同地形成焊盘116的实施例中，可以利用更多的光刻胶和图案化步骤。
在UBM 116上形成导电连接件118。导电连接件118可以是BGA连接件、焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。连接件118可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等方法形成焊料层来形成导电连接件118。一旦已经在结构上形成焊料层，就可以实施回流，以将材料成型为期望的凸块形状。在另一实施例中，导电连接件118是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有大致垂直的侧壁。在一些实施例中，在金属柱连接件118的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍钯金、镍金等或它们组合并且可通过镀工艺来形成。
图2示出晶圆200的划线区202。在相邻管芯100的密封环110之间设置划线区202。每个管芯100可以具有与图1A、图1B和图1C中所描述的类似的部件，其中相同的附图标记表示使用相似的工艺形成的相同的元件。例如，每个管芯100包括半导体衬底102、介电层120(例如，包括互连结构106和钝化膜112的低k介电层，参见图1A)和密封环110。在一些实施例中，介电层120的厚度T1可以是约10μm。在其他实施例中，介电层120可以具有不同的尺寸。尽管示出单个划线区202，但是在晶圆200(未示出)的顶视图中，每个管芯100可以在所有侧(例如四个侧)上被划线区202围绕。如下所述的实施例，切割工艺可以应用于每个管芯100的所有侧，以将管芯100与晶圆200中的其他部件完全分离。
图3至图5公开了根据一些实施例的用于将管芯100与晶圆200中的其他部件(例如，其他管芯100)分离的切割工艺。切割工艺可以包括用于形成穿过介电层120并且部分地延伸到半导体衬底102中的切口的激光烧蚀工艺。激光烧蚀工艺可以包括使用激光束的多次通过，以提供具有合适配置的切口。在形成切口之后，可以通过切口应用机械锯切工艺以完全切割管芯100。
首先参考图3，在划线区202中对晶圆200施加激光烧蚀工艺。激光烧蚀工艺可以包括对介电层120和衬底102施加的多个激光束204(标记为204A至204I)。控制每个激光束的位置、功率、数量和/或类型以便实现所得切口的期望轮廓。在实施例中，施加至少九个激光束(例如，标记为204A至204I)以提供具有合适轮廓的切口。已观察到，当对晶圆200施加至少九个激光束时，作为后续机械锯切工艺(参见图5)的结果，可能发生较少的制造缺陷。在其他实施例中，可以对晶圆200施加诸如大于九或小于九的不同数量的激光束。
可以从后续形成的切口的外周向内对晶圆200施加激光束204A至204I。每个激光束204A至204I可以延伸穿过介电层120并且部分地延伸到衬底102内。激光束204A至204I可以不完全穿过衬底102，并且激光束204A至204I可以停止在衬底102的顶面和底面之间的中间点处。在使用外-内切口形成工艺的实施例中，在激光束204B之前施加激光束204A；在激光束204C之前施加激光束204B；在激光束204E之前施加激光束204D；在激光束204F之前施加激光束204E；在激光器204G之前施加激光束204F；在激光束204H之前施加激光束204G；并且在激光束204I之前施加激光束204H。在其他实施例中，可以以不同的顺序对晶圆200施加激光束。例如，在另一实施例中，可以从后续形成的切口的中心向外对晶圆200施加激光束204A至204I。在使用内-外切口形成工艺的实施例中，在激光束204G或204H之前施加激光束204I；在激光束204E或204F之前施加激光束204G和204H；在激光束204C或204D之前施加激光束204E和204F；以及在激光束204A或204B之前施加激光束204C和204D。此外，可以在约0.1瓦(W)至约6W的功率处施加每个激光束204A至204I。
图4示出使用相对于图3描述的激光烧蚀工艺形成的所得切口206。切口206延伸穿过介电层120并且部分地延伸到衬底102内。在各个实施例中，切口206不完全延伸穿过衬底102，并且切口206的底面暴露衬底102的材料。在一些实施例中，切口206延伸到晶圆200中约13μm或更大的深度T2。在其他实施例中，切口206可以延伸到晶圆200中不同的深度。
此外，作为激光烧蚀工艺的结果，重铸区208可以形成在介电材料120的侧壁和衬底102上。由于在切口206的形成期间由激光束204(参见图3)照射的材料(例如，介电材料120和/或衬底102的材料)再沉积而形成这些重铸区208，并且可以通过重铸区208限定切口206的侧壁。尽管重铸区208示出为对称的(例如，在切口206的相对侧壁上具有相同的形状)，但是在一些实施例中，重铸区208在切口206的每个侧壁上可以具有不同的轮廓。重铸区208在约5μm至约15μm的最宽点处可以具有宽度W1。此外，从第一密封环110至第一重铸区208的横向距离W2可以是约10μm或更大，并且从第二密封环110至第二重铸区208的横向距离W3可以是约10μm或更大。第一密封环110/第一重铸区208可以设置在切口206的相对侧上以作为第二密封环110/第二重铸区208。横向距离W2和W3可以相同或不同。在其他实施例中，重铸区208可以具有不同的尺寸并且可以设置成距离密封环110不同的距离。
切口206形成为具有特定的轮廓和/或尺寸，以减少由切割引起的制造缺陷。例如，切口206在介电层120的顶面处在相对的重铸区208之间具有第一宽度W4，并且切口206在介电层120的底面/衬底102的顶面处在相对的重铸区208之间具有第二宽度W5。在各个实施例中，宽度W4与宽度W5的比率可以至少为约0.6。此外，切口206的底面和切口206的侧壁之间的角度θ可以为约90°至约135°。已经观察到，通过使用激光烧蚀工艺来形成具有该轮廓的切口206，可以减少在后续的机械锯切工艺(例如，参见图5)期间介电层120的剥离/破裂。例如，通过将切口206配置为在介电层120的底面处相对宽并且具有相对垂直(或钝角)的侧壁，可以减少或至少避免在后续机械锯切工艺(例如，通过锯片)期间对介电层120的暴露表面的冲击。通过在后续机械锯切工艺中减小锯片的冲击面积，可以减少这些工艺期间的介电层120的剥离和/或破裂。此外，由于增加了切口206的整体尺寸和角度θ，可以增加用于施加锯片的工艺窗口，而大致不增加冲击介电层120的风险。因此，可以减少制造缺陷并且还可以提高产量。例如，在使用上述工艺的实验中，已经观察到半导体器件的产量提高了25％。
图5示出切割工艺中的下一步骤。如图所示，在机械锯切步骤中采用锯片210以完成切割工艺。锯片210与由上述激光烧蚀工艺形成的切口206对准。锯片210用于完全锯穿衬底102的剩余底部。在示出的实施例中，锯片具有宽度W6。在一些实施例中，在介电层120的底面处，宽度W6小于切口206的宽度W5(参见图4)。在实施例中，例如，宽度W6可以是约10μm至约100μm，但是根据宽度W5还可以使用宽度W6的其他值。在其他实施例中，锯片210可以具有不同的厚度。此外，在其他实施例中，可以使用多个锯片(例如，具有相同或不同的厚度)和多个机械锯切步骤来完成切割工艺。
如图5所示，锯片210形成衬底102的侧壁102A。在实施例中，在介电层120的顶面处，侧壁重铸区208可以与侧壁102A间隔开横向距离W7，并且在介电层120的底面处，重铸区208的侧壁可以与侧壁102A间隔开距离W8。在一些实施例中，距离W7为约10μm或更大，而距离W8为约10μm至约20μm。已经观察到，当切口206(参见图4)的宽度W4/W5和/或距离W7/W8在上述范围内时，由使用锯片210的切割引起较少的制造缺陷(例如，介电层120的剥离/破裂)。
在使用实施例切割工艺切割管芯100之后，管芯100可以与器件封装件中的其他器件部件一起封装。例如，图6A和6B示出具有切割的管芯100的器件封装件300。在各个实施例中，可以切割多个管芯100(例如，从相同的晶圆或不同的晶圆切割)并将其封装在单个器件封装件300中。管芯100可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、功率管理管芯(例如，功率管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。此外，在一些实施例中，管芯100可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其他实施例中，管芯100可以具有相同的尺寸(例如，相同的高度和/或表面积)。
可以使用任何合适的接合技术(例如，使用管芯100的导电连接件118的翻转芯片接合)将管芯100最初接合至管芯302，而管芯302是较大晶圆(未示出)的部分。在一些实施例中，管芯302是没有有源器件并且具有延伸穿过衬底材料(例如，硅、具有或不具有填料的聚合物材料、它们的组合等)的导电通孔306的插入器。导电通孔306提供从管芯302的表面(管芯100接合在该表面上)至管芯302的相对表面的电布线。例如，导电通孔306提供管芯302的导电连接件118和导电连接件308之间的电布线。导电连接件308可以是BGA连接件、焊球、金属柱、C4凸块、微凸块、ENEPIG形成的凸块等。导电连接件308可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，通过最初通过诸如蒸发、电镀、印刷焊料转移、球放置等通常使用的方法形成焊料层来形成导电连接件308。一旦已经在该结构上形成焊料层，就可以实施回流，以将材料成型为期望的凸块形状。在另一实施例中，导电连接件308是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有大致垂直的侧壁。在一些实施例中，在金属柱连接件308的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍钯金、镍金等或它们组合并且通过镀工艺形成。
此外，管芯302还可以可选地包括包括导电部件的再分布层(未明确示出)，其提供不同管芯100之间且穿过管芯302的电布线。在其他实施例中，管芯302可以具有不同的配置。例如，管芯302可以是具有设置在其中的有源器件、无源器件、功能电路、它们的组合等的半导体器件管芯。
在管芯100接合至管芯302之后，可至少部分地在管芯100周围且在管芯100与管芯302之间形成密封剂304。密封剂304可以包括模塑料、环氧树脂、底部填充物等，并且可以通过压缩模制、传递模制、毛细作用力等来施加。密封剂304可以设置在导电连接件118周围，以向封装件300中的导电连接件118提供结构支撑。此外，密封剂304可以部分地沿着管芯100的侧壁延伸。在所示实施例中，管芯100延伸高于密封剂304。在其他实施例中，密封剂304可以延伸高于管芯100或者具有与管芯100的顶面大致齐平的顶面。
由于用于切割管芯100的切割工艺，管芯的其他侧壁可具有如图6B所示的轮廓。图6B示出封装件300的区域300A(还参见图6A)。如图6B所示，管芯100包括在区域300A中并且设置在管芯100的同一侧上的第一侧壁100A和第二侧壁100B。第一侧壁100A的材料可以是衬底102的材料，而第二侧壁100B的材料可以是重铸区208的材料。管芯100的底面100C将第一侧壁100A连接至第二侧壁100B。第一侧壁100A在介电层120和衬底102之间的界面处与第二侧壁100B横向间隔开距离W8，并且第一侧壁100A在介电层120的与衬底102相对的表面处与第二侧壁100B横向间隔开距离W7。在一些实施例中，距离W7为约10μm或更大，而距离W8为约10μm至约20μm。密封剂304沿着第二侧壁100B延伸，并且在一些实施例中可以进一步沿着第一侧壁100A的至少部分延伸。在这种实施例中，密封剂304可接触底面100C。在其他实施例中，密封剂304可以具有与管芯100的相对表面不同的形状和/或尺寸。
再次参考图6A，在形成密封剂304之后，可以从晶圆(未示出)中的其他部件切割管芯302。在一些实施例中，切割工艺可以大致类似于对管芯100施加的切割工艺。在其他实施例中，可以对切割的管芯302施加不同类型的切割工艺(例如，使用或不使用激光束)。
在切割管芯302之后，管芯302可以接合至封装衬底312。封装衬底312可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷镓、磷化镓铟、它们的组合等的化合物材料。额外地，封装衬底312可以是SOI衬底。通常，封装衬底312包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料的层。在一个可选实施例中，封装衬底312是基于绝缘芯，诸如玻璃纤维增强的树脂芯。一种示例性芯材料是诸如FR4的玻璃纤维树脂。用于芯材料的可选材料包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，其他PCB材料或膜。诸如ABF的构建膜或其他层压件可用于封装衬底312。
封装衬底312可以包括有源器件和无源器件(图6A中未示出)。本领域中的普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于产生用于封装件300的设计的结构和功能需求。可以使用任何合适的方法来形成器件。
封装衬底312还可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘。金属化层可以形成在有源器件和无源器件上方并且设计为连接各个有源器件以形成功能电路。金属化层可以由具有互连导电材料层的通孔的介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)来形成。在一些实施例中，封装衬底312大致没有有源器件和无源器件。
在一些实施例中，可以回流管芯302上的导电连接件308以将管芯302附接至封装衬底312的接合焊盘。在回流导电连接件308之前，导电连接件308可以具有形成在其上的环氧树脂焊剂(未示出)，其中在将管芯302附接至封装衬底312之后环氧树脂焊剂的环氧树脂部分的至少一些剩余。剩余的环氧树脂部分可以用作底部填充物以减少应力并保护由于回流导电连接件308而引起的接头。在一些实施例中，底部填充物310可以形成在管芯302和封装衬底312之间并且围绕导电连接件308。底部填充物可以在附接管芯302之后通过毛细管流动工艺形成，或者可以在附接管芯302之前通过合适的沉积方法形成。
封装衬底312中的导电部件可以将管芯302和管芯100电连接至设置在封装衬底312的与管芯302相对侧上的导电连接件314。在一些实施例中，导电连接件314是C4凸块、BGA球、微凸块等，并且导电连接件314可以用于将封装件300电连接至诸如另一封装件、另一封装衬底、另一插入器、母板等的其他半导体部件。
如本文所描述的，切割工艺可用于从晶圆中的其他部件(例如，其他半导体管芯)切割半导体管芯。切割工艺可以包括首先使用激光烧蚀工艺以在合适轮廓的晶圆中形成切口。可以控制激光烧蚀工艺的参数(例如，所施加的激光束的数量、功率、位置、所施加的激光束的顺序)以便提供合适的切口。例如，切口可以延伸穿过多个介电层到半导体衬底内。切口可以在介电层的相对横向表面处具有特定宽度，以提供较大的工艺窗口，从而用于后续的切割工艺。后续地，可以施加机械锯切工艺以将管芯从晶圆完全分离。已经观察到，通过控制切口以具有如上所述的轮廓，在机械锯切工艺期间可以减少制造缺陷(例如，介电层剥离和/或破裂)。因此，可以提高切割工艺的可靠性和产量。
根据实施例，一种方法包括提供晶圆，该晶圆包括第一集成电路管芯、第二集成电路管芯以及位于第一集成电路管芯和第二集成电路管芯之间的划线区。该方法还包括使用激光烧蚀工艺在划线区中形成切口，并且在形成切口之后，使用机械锯切工艺将第一集成电路管芯与第二集成电路管芯完全分离。该切口延伸穿过多个介电层至半导体衬底内。切口包括在多个介电层和半导体衬底之间的界面处的第一宽度，以及在多个介电层的与半导体衬底相对的表面处的第二宽度。第一宽度与第二宽度的比率至少为约0.6。
根据实施例，一种方法包括从晶圆切割半导体管芯。切割半导体管芯包括使用多个激光束在与半导体管芯相邻的划线区中形成切口。该切口延伸穿过多个介电层并且部分地延伸至半导体衬底内。切割半导体管芯还包括将锯片与切口对准并且使用锯片锯穿半导体衬底的由切口暴露的底部。在多个介电层和半导体衬底之间的界面处锯片比切口更窄。该方法还包括在切割半导体管芯之后，使用多个导电连接件将半导体管芯接合至另一管芯。在接合半导体管芯之后，半导体管芯包括第一侧壁和位于第一侧壁下方的第二侧壁。第一侧壁与第二侧壁横向间隔开。
根据实施例，器件封装件包括第一半导体管芯。第一半导体管芯包括：半导体衬底；多个介电层，与半导体衬底具有界面的；第一侧壁；以及位于第一侧壁下方并且设置在第一半导体管芯的与第一侧壁同一侧上的第二侧壁。第一侧壁横向延伸经过第二侧壁。器件封装件还包括通过多个导电连接件接合至第一半导体管芯的第二半导体管芯。器件封装件还包括设置在多个导电连接件周围的底部填充物。底部填充物沿着第一半导体管芯的第二侧壁延伸。
根据本发明的一个实施例，提供了一种形成半导体器件的方法，包括：接收晶圆，所述晶圆包括第一集成电路管芯；第二集成电路管芯；以及划线区，位于所述第一集成电路管芯和所述第二集成电路管芯之间；以及在所述划线区中形成切口，其中，所述切口延伸穿过多个介电层至半导体衬底内，以及其中，所述切口包括：位于所述多个介电层与所述半导体衬底之间的界面处的第一宽度；以及位于所述多个介电层的与所述半导体衬底相对的表面处的第二宽度，其中，所述第一宽度与所述第二宽度的比率至少为0.6。
在上述方法中，所述切口的底面与所述切口的侧壁之间的角度为90°至135°。
在上述方法中，还包括在形成所述切口之后，使用机械锯切工艺以将所述第一集成电路管芯与所述第二集成电路管芯完全分离。
在上述方法中，所述机械锯切工艺包括使用具有第三宽度的锯片，其中，所述第三宽度小于所述第一宽度。
在上述方法中，在所述划线区中形成所述切口包括激光烧蚀工艺。
在上述方法中，所述激光烧蚀工艺还在所述多个介电层的侧壁上和所述半导体衬底的侧壁上形成重铸区。
在上述方法中，所述激光烧蚀工艺包括：在所述划线区中的第一位置处施加第一激光束；在施加所述第一激光束之后，在所述划线区中的第二位置处施加第二激光束；以及在施加所述第二激光束之后，在所述划线区中的第三位置处施加第三激光束，其中，所述第二位置在所述第一位置和所述第三位置之间。
在上述方法中，所述激光烧蚀工艺包括：在所述划线区中的第一位置处施加第一激光束；在施加所述第一激光束之后，在所述划线区中的第二位置处施加第二激光束；以及在施加所述第二激光束之后，在所述划线区中的第三位置处施加第三激光束，其中，所述第三位置在所述第一位置和所述第二位置之间。
根据本发明的另一实施例，还提供了一种形成半导体器件的方法，包括：从晶圆切割半导体管芯，其中，切割所述半导体管芯包括：使用多个激光束在与所述半导体管芯相邻的划线区中形成切口，其中，所述切口延伸穿过多个介电层并且部分地延伸至半导体衬底内；将锯片与所述切口对准，其中，在所述多个介电层和所述半导体衬底之间的界面处，所述锯片比所述切口更窄；以及使用所述锯片锯穿所述半导体衬底的由所述切口暴露的底部。
在上述方法中，还包括在切割所述半导体管芯之后，使用多个导电连接件将所述半导体管芯接合至另一管芯，其中，在接合所述半导体管芯之后，所述半导体管芯包括：第一侧壁；以及第二侧壁，位于所述第一侧壁下方，其中，所述第一侧壁与所述第二侧壁横向间隔开。
在上述方法中，还包括在所述多个导电连接件周围形成密封剂，其中，所述密封剂沿着所述第二侧壁延伸。
在上述方法中，所述第一侧壁在所述多个介电层与所述半导体衬底之间的所述界面处与所述第二侧壁横向间隔开第一距离，其中，所述第一侧壁在所述多个介电层的与所述半导体衬底相对的表面处与所述第二侧壁间隔开第二距离，其中，所述第一距离在10μm至20μm之间，以及其中，所述第二距离至少为10μm。
在上述方法中，所述切口在所述多个介电层和所述半导体衬底之间的所述界面处具有第一宽度，其中，所述切口在所述多个介电层的与所述半导体衬底相对的表面处具有第二宽度，以及其中，所述第一宽度与所述第二宽度的比率至少为0.6。
在上述方法中，还包括使用所述多个激光束在所述多个介电层的侧壁上和所述半导体衬底上形成重铸区，其中，所述重铸区包括由所述多个激光束照射的再沉积的材料。
在上述方法中，所述半导体管芯包括环绕所述半导体管芯的功能电路区的密封环，并且其中，所述密封环设置在所述划线区和所述功能电路区之间，并且其中，所述密封环在所述多个介电层的顶面之上延伸同时切割所述半导体管芯。
根据本发明的又一实施例，还提供了一种半导体器件，包括：第一半导体管芯，其中，所述第一半导体管芯包括：半导体衬底；多个介电层，与所述半导体衬底具有界面；第一侧壁；以及第二侧壁，位于所述第一侧壁下方并且设置在所述第一半导体管芯的与所述第一侧壁相同的一侧上，其中，所述第一侧壁与所述第二侧壁横向间隔开；以及底部填充物，沿着所述第一半导体管芯的所述第二侧壁延伸。
在上述半导体器件中，还包括通过多个导电连接件接合至所述第一半导体管芯的第二半导体管芯，其中，所述底部填充物设置在所述多个导电连接件周围。
在上述半导体器件中，所述第一侧壁在所述多个介电层和所述半导体衬底之间的所述界面处与所述第二侧壁横向间隔开第一距离，其中，所述第一侧壁在所述多个介电层的与所述半导体衬底相对的表面处与所述第二侧壁间隔开第二距离，其中，所述第一距离在10μm至20μm之间，并且其中，所述第二距离至少为10μm。
在上述半导体器件中，所述第一侧壁的材料是所述半导体衬底的材料，其中，所述第二侧壁的材料是重铸区的材料，并且其中，所述重铸区包括所述多个介电层的材料。
在上述半导体器件中，所述第一半导体管芯还包括将所述第一侧壁连接至所述第二侧壁的底面，并且其中，所述第二侧壁和所述底面之间的角度为90°至130°。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
接收晶圆，所述晶圆包括
第一集成电路管芯；
第二集成电路管芯；以及
划线区，位于所述第一集成电路管芯和所述第二集成电路管芯之间；以及
在所述划线区中形成切口，其中，所述切口延伸穿过多个介电层至半导体衬底内，以及其中，所述切口包括：
位于所述多个介电层与所述半导体衬底之间的界面处的第一宽度；以及
位于所述多个介电层的与所述半导体衬底相对的表面处的第二宽度，其中，所述第二宽度与所述第一宽度的比率至少为0.6，其中，在所述多个介电层至所述半导体衬底的方向上，所述切口的相对侧壁之间的宽度的变化趋势为先增大后减小。
2.根据权利要求1所述的方法，其中，所述切口的底面与所述切口的侧壁之间的角度为90°至135°。
3.根据权利要求1所述的方法，还包括在形成所述切口之后，使用机械锯切工艺以将所述第一集成电路管芯与所述第二集成电路管芯完全分离。
4.根据权利要求3所述的方法，其中，所述机械锯切工艺包括使用具有第三宽度的锯片，其中，所述第三宽度小于所述第一宽度。
5.根据权利要求1所述的方法，其中，在所述划线区中形成所述切口包括激光烧蚀工艺。
6.根据权利要求5所述的方法，其中，所述激光烧蚀工艺还在所述多个介电层的侧壁上和所述半导体衬底的侧壁上形成重铸区。
7.根据权利要求5所述的方法，其中，所述激光烧蚀工艺包括：
在所述划线区中的第一位置处施加第一激光束；
在施加所述第一激光束之后，在所述划线区中的第二位置处施加第二激光束；以及
在施加所述第二激光束之后，在所述划线区中的第三位置处施加第三激光束，其中，所述第二位置在所述第一位置和所述第三位置之间。
8.根据权利要求5所述的方法，其中，所述激光烧蚀工艺包括：
在所述划线区中的第一位置处施加第一激光束；
在施加所述第一激光束之后，在所述划线区中的第二位置处施加第二激光束；以及
在施加所述第二激光束之后，在所述划线区中的第三位置处施加第三激光束，其中，所述第三位置在所述第一位置和所述第二位置之间。
9.一种形成半导体器件的方法，包括：
从晶圆切割半导体管芯，其中，切割所述半导体管芯包括：
使用多个激光束在与所述半导体管芯相邻的划线区中形成切口，其中，所述切口延伸穿过多个介电层并且部分地延伸至半导体衬底内；
将锯片与所述切口对准，其中，在所述多个介电层和所述半导体衬底之间的界面处，所述锯片比所述切口更窄；以及
使用所述锯片锯穿所述半导体衬底的由所述切口暴露的底部，其中，在所述多个介电层至所述半导体衬底的方向上，所述切口的相对侧壁之间的宽度的变化趋势为先增大后减小。
10.根据权利要求9所述的方法，还包括在切割所述半导体管芯之后，使用多个导电连接件将所述半导体管芯接合至另一管芯，其中，在接合所述半导体管芯之后，所述半导体管芯包括：
第一侧壁；以及
第二侧壁，位于所述第一侧壁下方，其中，所述第一侧壁与所述第二侧壁横向间隔开。
11.根据权利要求10所述的方法，还包括在所述多个导电连接件周围形成密封剂，其中，所述密封剂沿着所述第二侧壁延伸。
12.根据权利要求10所述的方法，其中，所述第一侧壁在所述多个介电层与所述半导体衬底之间的所述界面处与所述第二侧壁横向间隔开第一距离，其中，所述第一侧壁在所述多个介电层的与所述半导体衬底相对的表面处与所述第二侧壁间隔开第二距离，其中，所述第一距离在10μm至20μm之间，以及其中，所述第二距离至少为10μm。
13.根据权利要求9所述的方法，其中，所述切口在所述多个介电层和所述半导体衬底之间的所述界面处具有第一宽度，其中，所述切口在所述多个介电层的与所述半导体衬底相对的表面处具有第二宽度，以及其中，所述第二宽度与所述第一宽度的比率至少为0.6。
14.根据权利要求9所述的方法，还包括使用所述多个激光束在所述多个介电层的侧壁上和所述半导体衬底上形成重铸区，其中，所述重铸区包括由所述多个激光束照射的再沉积的材料。
15.根据权利要求9所述的方法，其中，所述半导体管芯包括环绕所述半导体管芯的功能电路区的密封环，并且其中，所述密封环设置在所述划线区和所述功能电路区之间，并且其中，所述密封环在所述多个介电层的顶面之上延伸同时切割所述半导体管芯。
16.一种半导体器件，包括：
第一半导体管芯，其中，所述第一半导体管芯包括：
半导体衬底；
多个介电层，与所述半导体衬底具有界面；
第一侧壁；以及
第二侧壁，位于所述第一侧壁下方并且设置在所述第一半导体管芯的与所述第一侧壁相同的一侧上，其中，所述第一侧壁与所述第二侧壁横向间隔开；以及
底部填充物，沿着所述第一半导体管芯的所述第二侧壁延伸，其中，所述第一侧壁与所述第二侧壁横向间隔开的距离的变化趋势为先增大后减小。
17.根据权利要求16所述的半导体器件，还包括通过多个导电连接件接合至所述第一半导体管芯的第二半导体管芯，其中，所述底部填充物设置在所述多个导电连接件周围。
18.根据权利要求16所述的半导体器件，其中，所述第一侧壁在所述多个介电层和所述半导体衬底之间的所述界面处与所述第二侧壁横向间隔开第一距离，其中，所述第一侧壁在所述多个介电层的与所述半导体衬底相对的表面处与所述第二侧壁间隔开第二距离，其中，所述第一距离在10μm至20μm之间，并且其中，所述第二距离至少为10μm。
19.根据权利要求16所述的半导体器件，其中，所述第一侧壁的材料是所述半导体衬底的材料，其中，所述第二侧壁的材料是重铸区的材料，并且其中，所述重铸区包括所述多个介电层的材料。
20.根据权利要求16所述的半导体器件，其中，所述第一半导体管芯还包括将所述第一侧壁连接至所述第二侧壁的底面，并且其中，所述第二侧壁和所述底面之间的角度为90°至130°。
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US10720360B2 (en) 2020-07-21
TW201818456A (zh) 2018-05-16
KR20180013685A (ko) 2018-02-07
US20200350209A1 (en) 2020-11-05
US10510605B2 (en) 2019-12-17

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