CN107546222A - 包括ldmos晶体管的半导体装置 - Google Patents

包括ldmos晶体管的半导体装置 Download PDF

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CN107546222A
CN107546222A CN201710485102.0A CN201710485102A CN107546222A CN 107546222 A CN107546222 A CN 107546222A CN 201710485102 A CN201710485102 A CN 201710485102A CN 107546222 A CN107546222 A CN 107546222A
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semiconductor device
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substrate
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CN107546222B (zh
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A.比尔纳
M.布劳恩
H.布雷赫
C.埃克尔
M.齐格尔德伦
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Infineon Technologies AG
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Abstract

本发明涉及包括LDMOS晶体管的半导体装置。在实施例中，一种半导体装置包括：半导体衬底，具有体电阻率ρ ≥ 100 Ohm.cm、前表面和后表面；至少一个LDMOS晶体管，位于半导体衬底中；和RESURF结构。RESURF结构包括掺杂掩埋层，掺杂掩埋层被布置在半导体衬底中，与前表面和后表面分隔开一定距离，并且与LDMOS晶体管的沟道区域和主体接触区域中的至少一个区域耦合。

Description

包括LDMOS晶体管的半导体装置
背景技术
持续地需要适应于在越来越高的频率(包括微波频率)操作的固态电路。如本文中所使用，术语“微波”旨在表示在大约300 MHz或高于大约300 MHz(例如，在300 MHz和3 GHz之间)的频率。已创建能够在这种频率范围中提供增益的各种晶体管结构。LDMOS(侧向扩散金属氧化物半导体)晶体管是这种晶体管结构的示例。
对于具有较快开关速度的功率放大器电路而言，期望具有高击穿电压和低接通电阻的LDMOS晶体管。然而，以相反的方式影响这些参数。例如，通过增加漂移长度，提高击穿电压，但增加接通电阻。
因此，期望用于在较高的频率为晶体管装置提供提高的性能的进一步改进。
发明内容
在实施例中，一种半导体装置包括：半导体衬底，具有体电阻率ρ ≥ 100 Ohm.cm、前表面和后表面；至少一个LDMOS晶体管，位于半导体衬底中；和RESURF结构。RESURF结构包括掺杂掩埋层，掺杂掩埋层被布置在半导体衬底中，与前表面和后表面分隔开一定距离，并且与LDMOS晶体管的沟道区域和主体接触区域中的至少一个区域耦合。
在实施例中，一种半导体装置包括：半导体衬底，具有体电阻率ρ ≥ 100 Ohm.cm、前表面和后表面；至少一个LDMOS晶体管，位于半导体衬底中，LDMOS晶体管包括源极区域、漏极区域、沟道区域、漂移区域和主体接触区域，其中源极区域被耦合到衬底的后表面上的导电层；掺杂掩埋层，被布置在衬底中，与前表面和后表面分隔开一定距离，并且与LDMOS晶体管的主体接触区域耦合；栅极屏蔽，从栅极朝着LDMOS晶体管的源极区域延伸；和场板，从栅极朝着LDMOS晶体管的漏极区域延伸。
在实施例中，一种方法包括：在具有体电阻率ρ ≥ 100 Ohm.cm的半导体衬底内注入具有第一导电型的掺杂物浓度的自耗尽层；以及在衬底的前表面中形成LDMOS晶体管，以使得源极区域、沟道区域、漂移区域和漏极区域通过衬底的一部分而与自耗尽层分隔开，其中所述主体接触区域延伸到自耗尽层并且与自耗尽层耦合。
本领域技术人员将会在阅读下面的详细描述时并且在观看附图时意识到另外的特征和优点。
附图说明
附图的元件未必相对于彼此按照比例绘制。相同标号指定对应类似部分。各种示出的实施例的特征能够被组合，除非它们彼此排斥。在附图中描绘示例性实施例并且在下面的描述中详述示例性实施例。
图1图示包括具有RESURF结构的LDMOS晶体管的半导体装置。
图2图示包括具有RESURF结构的LDMOS晶体管的半导体装置。
图3图示包括具有RESURF结构的LDMOS晶体管的半导体装置。
图4图示包括具有RESURF结构的LDMOS晶体管的半导体装置。
图5图示包括具有RESURF结构的LDMOS晶体管的半导体装置。
图6图示包括具有RESURF结构的LDMOS晶体管的半导体装置。
图7图示用于加工具有RESURF结构的LDMOS晶体管的方法的流程图。
具体实施方式
在下面的详细描述中，参照附图，附图形成所述详细描述的一部分并且在附图中作为说明示出了可实施本发明的特定实施例。在这个方面，参照正在描述的(一个或多个)附图的方位使用方向术语，诸如“顶”、“底”、“前”、“后”、“首”、“尾”等。因为实施例的部件能够位于许多不同方位，所以方向术语被用于说明的目的，而绝不是限制性的。应理解，在不脱离本发明的范围的情况下，可使用其它实施例并且可实现结构或逻辑改变。不应在限制性意义上理解下面的详细描述，并且由所附权利要求定义本发明的范围。
将在以下解释许多示例性实施例。在这种情况下，相同的结构特征由附图中的相同或相似的标号识别。在本描述的上下文中，“侧向”或“侧向方向”应该被理解为意指大体上平行于半导体材料或半导体载体的侧向范围而延伸的方向或范围。侧向方向因此大体上平行于这些表面或侧面而延伸。与此相比，术语“垂直”或“垂直方向”被理解为意指大体上垂直于这些表面或侧面而延伸并且因此垂直于侧向方向而延伸的方向。垂直方向因此沿半导体材料或半导体载体的厚度方向延伸。
如本说明书中所采用，当元件(诸如，层、区域或衬底)被称为“位于另一元件上”或“延伸到另一元件上”时，它能够直接位于所述另一元件上或直接延伸到所述另一元件上，或者也可存在中间元件。相比之下，当元件被称为“直接位于另一元件上”或“直接延伸到另一元件上”时，不存在中间元件。
如本说明书中所采用，当元件被称为“连接”或“耦合”到另一元件时，它能够直接连接或耦合到所述另一元件，或者可存在中间元件。相比之下，当元件被称为“直接连接”或“直接耦合”到另一元件时，不存在中间元件。
如本文中所使用，各种装置类型和/或掺杂半导体区域可被识别为具有n型或p型，但这仅是为了描述的方便并且不旨在是限制性的，并且这种识别可被具有“第一导电型”或“第二相反导电型”的更一般描述替换，其中第一类型可以是n或p型而第二类型则是p或n型。
本领域技术人员将会理解，(一个或多个)有源装置(诸如，LDMOS晶体管)可根据(一个或多个)装置的性质而被形成在衬底上或形成在衬底上方或者完全形成在衬底内或者部分地形成在衬底内并且部分地形成在衬底上或形成在衬底上方。因此，如本文中针对(一个或多个)有源装置所使用，术语“在衬底中”、“在半导体衬底中”和等同物旨在包括所有这种变化。
图1图示根据实施例的半导体装置10。半导体装置10包括半导体衬底11，半导体衬底11具有前表面12和后表面13。半导体衬底11具有体电阻率ρ，体电阻率ρ大于或等于100Ohm.cm。半导体装置10包括位于半导体衬底11中的至少一个LDMOS(侧向扩散金属氧化物半导体)晶体管14。半导体装置10还包括RESURF结构15，RESURF结构15包括布置在半导体衬底11中的掺杂掩埋层16。掺杂掩埋层16与前表面12分隔开一定距离，并且与半导体衬底11的后表面13分隔开一定距离。掺杂掩埋层16与LDMOS晶体管14的沟道区域17和/或主体接触区域18耦合。
LDMOS晶体管中的RESURF结构15(降低表面场结构)用于降低在半导体衬底11的前表面12的电场并且在高击穿电压和低接通电阻之间实现改进的折衷。
半导体衬底11具有大于或等于100 Ohm.cm的体电阻率ρ，并且可被描述为具有高电阻。在一些实施例中，半导体衬底11包括硅并且可包括硅单晶。
当半导体衬底的体电阻率等于或大于预定水平时，衬底相关电感和电容寄生效应能够减小。期望的预定水平有益地等于或大于100 Ohm.cm电阻率，方便地等于或大于大约500 Ohm.cm电阻率，更方便地等于或大于大约1000 Ohm.cm电阻率。如本文中所使用，术语“体电阻率”涉及衬底60的位于装置区域之外(例如，位于LDMOS晶体管的掺杂区域和任何关联的RESURF结构之外)的那些部分。
提供RESURF结构15的掺杂掩埋层16以减小在半导体衬底11的前表面12的电场以及特别是，在栅极21的漏极侧边缘28处以及在沿漏极区域20的方向从栅极21的漏极侧边缘28开始的区域中的在半导体衬底11的前表面12的电场。掺杂掩埋层16还可被配置为自耗尽并且源极接地。掺杂掩埋层16用于通过使漏极结较少突变来限制漏极-源极泄漏，并且帮助在漏极结的偏置期间耗尽漂移区域。
如本文中所使用，术语“LDMOS晶体管”表示包括源极、栅极和漏极的单LDMOS晶体管结构。单LDMOS晶体管结构也可被称为基元或片段。LDMOS晶体管14包括：源极区域19，被利用第二导电型(例如，n+)高度掺杂；和漏极区域20，被利用第二导电型(例如，n+)高度掺杂。源极区域19和漏极区域20在半导体衬底11的前表面12被不对称地布置在栅极21周围，栅极21被布置在前表面12上。
漂移区域22沿漏极区域20的方向从栅极21延伸到前表面12中，并且可掺杂有第二导电型(例如，n)。与漏极区域20相比，漂移区域22更深地延伸到半导体衬底11中。漂移区域掺杂有第二导电型(例如，n)，并且具有比漏极区域20和源极区域19的掺杂物浓度小的掺杂物浓度。与沟道区域17相比，漂移区域22在半导体衬底11中延伸更大的距离，但通过半导体衬底11的一部分而与掺杂掩埋层16分隔开。
LDMOS晶体管14还包括：沟道区域17，在源极区域19下方从漂移区域22延伸；和主体接触区域18，掺杂有第一导电型，并且与沟道区域17相比从前表面12更深地延伸到半导体衬底11中。由延伸到掺杂掩埋层16并且与掺杂掩埋层16交叠的第二导电型的高度掺杂阱提供主体接触区域18。
在一些实施例中，半导体衬底11可包括利用第一导电型(例如，p--)轻掺杂的硅。掩埋掺杂层16可掺杂有第一导电型(例如，p)，沟道层17可掺杂有第一导电型(例如，p)，并且主体接触区域18可利用第一导电型(例如，p+)进行高度掺杂。
LDMOS晶体管14是多个晶体管基元或片段之一，由此晶体管基元的相同的电极通过布置在前表面12上的未示出的金属化结构以电气方式耦合在一起以形成单个开关装置。在对称结构中，漏极区域20被提供在中心线23周围，并且为两个邻近的晶体管基元或片段提供共同的漏极区域20。然而，也可使用非对称布置。
漏极区域20具有有益地至少5.1019 cm-3的掺杂浓度，方便地至少1.1020 cm-3的掺杂浓度，以及更方便地至少3.1020 cm-3的掺杂浓度，但也可使用更高或更低的掺杂浓度。漂移区域22在对称结构中沿侧向紧挨着漏极区域20，并且具有有益地处于1.1016 cm-3到1.1018 cm-3的范围中，方便地处于7.1016 cm-3到3.1017 cm-3的范围中，并且更方便地处于1.1017 cm-3到2.1017 cm-3的范围中的掺杂浓度，但也可使用更高或更低的掺杂浓度。相对于中心线23的漂移区域22的侧向外侧是沟道区域17，沟道区域17位于栅极21的至少一部分下面。沟道区域17具有有益地处于1.1017 cm-3到2.1018 cm-3的范围中，方便地处于3.1017 cm-3到1.1018 cm-3的范围中，并且更方便地处于5.1017 cm-3到9.1017 cm-3的范围中的掺杂浓度，但也可使用更高或更低的掺杂浓度。沟道区域17的侧向外侧是源极区域19。源极区域19具有有益地至少5.1019 cm-3，方便地至少1.1020 cm-3，并且更方便地至少3.1020 cm-3的掺杂浓度，但也可使用更高或更低的掺杂浓度。源极区域19的侧向外侧是主体接触区域18。主体接触区域18具有有益地处于1.1018 cm-3到1.1020 cm-3的范围中，方便地处于2.1018 cm-3到7.1019 cm-3的范围中，并且更方便地处于5.1018 cm-3到5.1019 cm-3的范围中的掺杂浓度，但也可使用更高或更低的掺杂浓度。衬底11可具有处于1.1017 cm-3到2.1018 cm-3的范围中的掺杂浓度。掺杂掩埋层可具有处于1.1013 cm-3到2.1015 cm-3的范围中的掺杂浓度。
当栅极21被合适地偏置时，导电沟道17形成在源极区域19和漏极区域20之间。以上提出的示例性导电型适合于形成N沟道结构，但本领域技术人员将会理解，通过各种掺杂区域的导电型的适当互换和栅极21上的偏置的适当修改，也能够形成P沟道结构。
LDMOS晶体管14的源极区域19可被耦合到半导体衬底11的后表面13。源极区域19和后表面13之间的导电路径可具有不同形式。
在一些实施例中，提供导电通孔，所述导电通孔从前表面12穿过半导体衬底11延伸到后表面13。导电通孔可被定位，从而主体接触区域18包围导电通孔的上部。导电通孔可铺衬有金属(诸如，钨或铜)。在一些实施例中，导电通孔的底部填充有高纯铜，并且所述通孔的上部包括包围空隙的高纯铜包层侧壁。所述通孔的顶部可被密封以在衬底通孔的上部内提供腔或间隙。
包括一个或多个金属层的接触结构可基本上在半导体衬底11的整个后表面13上方延伸。后表面13上的接触结构可通过例如导电通孔以电气方式耦合到半导体衬底11的相对的前表面12中的源极区域19。
通过使用适当地构造的掩模和掺杂物离子经半导体衬底11的前表面12进行离子注入并且通过随后对注入的区域进行扩散，可形成掺杂掩埋层16、沟道区域17、主体接触区域18、漂移区域22、源极区域19和漏极区域20。
在一些实施例(诸如，图2中示出的实施例)中，源极区域19包括双阱结构，并且漏极区域20包括双阱结构。漏极20的第二阱23可包围更加高度掺杂的阱24，由此两个阱都掺杂有第二导电型。
源极区域19的更加高度掺杂的阱25可延伸到栅极21的源极侧26，并且延伸到主体接触区域18的侧向范围之外。与更加高度掺杂的阱25相比，源极区域19的更加轻度掺杂的阱27更深地延伸到衬底11中，并且延伸的距离比沟道区域17延伸的距离稍小，并且可完全位于主体接触区域18内。LDMOS晶体管14和RESURF结构15的其余部分与图1中示出的实施例相同。
在图1和2中示出的实施例中，RESURF结构15的掺杂掩埋层16连续地延伸贯穿半导体衬底11的侧向区域，并且连续地在LDMOS晶体管14的源极区域19、栅极21和漏极区域20下方延伸。掺杂掩埋层16通过半导体衬底11的一部分而与漂移区域22和沟道区域17分隔开。掺杂掩埋层16具有比半导体衬底11的掺杂物浓度大并且比沟道区域17的掺杂物浓度小的掺杂物浓度。
提供RESURF结构15以减小在半导体衬底11的前表面12的电场以及特别地是，在栅极21的漏极侧边缘28处以及沿漏极区域20的方向的在半导体衬底11的前表面12的电场。RESURF结构15可被用于增加晶体管的击穿电压，同时保持低接通电阻。
除了掺杂掩埋层16之外，RESURF结构15还可包括另外的特征以减小在半导体衬底11的前表面12的电场。在一些实施例中，RESURF结构包括至少一个场板。场板可从栅极21朝着漏极区域20延伸。场板、掺杂掩埋层16的尺寸和位置、掺杂掩埋层16和漂移区域22的掺杂水平和轮廓可被选择以在前表面12产生低于期望阈值(例如，0.5 MV/cm)的电场。
图3图示具有RESURF结构15的半导体装置10，RESURF结构15包括掺杂掩埋层16并且另外包括场板33。半导体装置10包括位于半导体衬底11的前表面12上的第一介电层30(例如，TEOS层)。第一介电层30被构造并且具有：位于漏极接触区域23上方的开口，在所述开口中形成漏极金属接触部31；和位于源极区域25上方的开口，在所述开口中形成源极金属接触部32。第一介电层30覆盖栅极21，并且在源极侧栅极边缘26和源极金属接触部32之间以及在漏极侧栅极边缘28和漏极金属接触部31之间延伸。
RESURF结构包括场板33，场板33位于栅极21上方的第一介电层30上，沿漏极金属接触部31的方向在第一介电层30上延伸。
第二介电层34被沉积，以使得它在源极金属接触部32、第一介电层30的位于源极金属接触部32和场板33之间的部分上方、在栅极21上方、在场板33、第一介电层30的在场板33和漏极金属接触部31之间延伸的部分上方以及在漏极金属接触部31上方延伸。第二介电层34可包括两个或更多个子层，例如氮氧化硅(SiON)的第一子层和第一子层上的二氧化硅(SiO2)的第二子层。
栅极屏蔽35被布置在栅极21上方的第二介电层34上，并且沿源极区域19的方向延伸。栅极屏蔽35可被共形地沉积在第二介电层34上，并且可部分地与场板33的栅极侧端交叠。
在这个实施例中，RESURF结构15包括掺杂掩埋层16、轻掺杂漏极区域22和场板33。图4图示RESURF结构15和LDMOS晶体管结构的尺寸，所述尺寸可被优化以便减小在前表面12(特别地，在栅极21的漏极侧边缘28)的电场。
为了减小在前表面12以及特别是在栅极21的漏极侧边缘28的给定晶体管结构(诸如，图2中示出的晶体管结构)的电场，栅极21的漏极侧边缘28和场板33的漏极侧边缘36之间的场板的长度LFP、栅极21的长度LG、栅极21的漏极侧边缘28和漏极金属接触部31的栅极侧边缘37之间的漂移区的长度LLDD、漂移区上方的场板的高度DFP、漂移区相对于前表面12的深度DLDD和掺杂掩埋层16相对于前表面12的深度D可被合适地选择和优化。
晶体管结构的合适的尺寸可根据晶体管装置的电压等级而不同。对于28 V到30 V的电压等级，长度LFP可处于0.8 μm到1.2 μm的范围中，长度LG可处于0.2 μm到0.5 μm的范围中，长度LLDD可处于2.5 μm到3.2 μm的范围中，高度DFP可处于0.1 μm到0.2 μm的范围中，深度DLDD可处于0.1 μm到0.5 μm的范围中，并且掺杂掩埋层的深度D可处于0.5 μm到2.5 μm的范围中。
对于18V的电压等级，长度LFP可处于0.4 μm到1.0 μm的范围中，长度LG可处于0.15μm到0.3 μm的范围中，长度LLDD可处于0.8 μm到2.5 μm的范围中，高度DFP可处于0.05 μm到0.15 μm的范围中，深度DLDD可处于0.1 μm到0.5 μm的范围中，并且掺杂掩埋层的深度D可处于0.3 μm到2.0 μm的范围中。
对于50V的电压等级，长度LFP可处于0.8 μm到2.0 μm的范围中，长度LG可处于0.3μm到0.8 μm的范围中，长度LLDD可处于3.0 μm到8.0 μm的范围中，高度DFP可处于0.15 μm到0.35 μm的范围中，深度DLDD可处于0.1 μm到1.0 μm的范围中，并且掺杂掩埋层的深度D可处于0.5 μm到3.0 μm的范围中。
半导体装置可表现出至少60伏特的击穿电压，同时支持至少0.15 A/mm的饱和电流。
源极区域19可被耦合到半导体衬底11的后表面13，并且特别地，耦合到布置在后表面13上的导电层37。导电层37可提供用于将半导体装置10安装到衬底和/或封装的地平面上的接触垫。在一些实施例中，源极区域19和半导体衬底11的后表面13之间的连接由至少部分地位于半导体衬底11内的导电路径提供。图5和6图示可使用的导电路径的示例。
图5图示提供衬底通孔(TSV) 40的实施例，TSV 40从半导体衬底11的前表面12延伸到半导体衬底11的后表面13。TSV 40可包括填充TSV 40的导电材料41(诸如，钨)。TSV 40可包括最外面的介电衬里以将位于TSV 40内的导电路径与半导体衬底11的掺杂区域电绝缘。提供粘合促进的一个或多个衬里层、扩散阻挡层和/或种子层被布置在定义TSV 40的侧壁的半导体衬底11的材料和导电材料41之间。导电材料41可通过布置在衬底11的前表面12上的金属化结构42的一部分而以电气方式耦合到源极区域19。TSV 40延伸穿过布置在前表面12上的介电层43，并且被耦合到布置在介电层43上的金属层44，金属层44又通过另一导电通孔45而被耦合到源极区域19，所述另一导电通孔45延伸穿过介电层43到达源极金属接触部32。金属层44可包括铝。
图6图示根据另一实施例的衬底通孔(TSV) 50的结构，TSV 50从半导体衬底11的前表面12延伸到半导体衬底11的后表面13。插图图示LDMOS晶体管14和与TSV 50的电连接的放大视图。
TSV 50包括位于它的底部的第一导电部分51，第一导电部分51包括导电材料(诸如，高纯铜)。在底部，导电材料填充TSV 50的体积并且形成后表面13的一部分，以使得它与位于半导体衬底11的后表面13上的导电层37直接接触。TSV 50还包括共形导电层52，共形导电层52被布置在通孔的侧壁上并且至少布置在位于通孔的底部的导电部分51的上表面的周界上。共形导电层52还可包括高纯铜。导电层52可在TSV 50的上部内定义空隙53，空隙53可例如由导电层或半导体层或介电层54在顶部密封以在TSV 50的上部内形成间隙55。
TSV 50的上区域由主体接触区域17包围。TSV 50可以是按照行或阵列布置在衬底的在邻近LDMOS晶体管之间的区域中的多个TSV之一。所述一个TSV或多个TSV可被耦合到两个邻近LDMOS晶体管的源极区域。
共形导电层52还可在半导体衬底11的前表面12上方延伸，并且可被直接布置在导电层56上并且以电气方式与导电层56耦合，导电层56在与源极区域19相邻的位置耦合到源极金属接触部32。
一个或多个另外的层可被布置在TSV 50的壁上，用作粘合促进层、扩散阻挡层和/或种子层，例如，可使用物理气相沉积和/或化学气相沉积技术来沉积Ti、TiN和Cu种子层，并且通过电沉积技术来沉积第一部分51和共形导电层52。
在这个实施例中，可使用双镶嵌技术形成共形导电层52。可使用电镀技术形成共形导电层52和导电部分51。例如，用于电沉积第一导电部分51的条件可不同于用于在第一导电部分51上面电沉积共形导电层52的那些条件。
第一导电部分51和共形导电层52可具有不同微观结构，例如不同平均晶粒尺寸。
图7图示根据本文中描述的一个或多个实施例的用于加工具有RESURF结构的LDMOS晶体管的方法的流程图80，其中所述RESURF结构包括掺杂掩埋层。
在块81中，所述方法包括：在具有体电阻率ρ ≥ 100 Ohm.cm的半导体衬底内注入具有第一导电型的掺杂物浓度的自耗尽层；以及在块82中，在衬底的前表面中形成LDMOS晶体管，以使得源极区域、沟道区域、漂移区域和漏极区域通过衬底的一部分而与自耗尽层分隔开并且主体接触区域延伸到自耗尽层并且与自耗尽层耦合。
自耗尽层可被注入，以使得它连续地延伸贯穿衬底的侧向区域。衬底、沟道层和自耗尽层掺杂有第一导电型，以使得自耗尽层的掺杂物浓度大于衬底的掺杂物浓度并且小于沟道区域的掺杂浓度。主体接触区域掺杂有第一导电型，并且具有比沟道区域的掺杂物浓度大的掺杂物浓度。可通过从前表面注入和随后扩散来形成沟道层和主体接触区域。可通过从前表面注入和随后扩散来形成漂移区域。
源极区域、漂移区域和漏极区域具有第二导电型的掺杂物浓度，第二导电型与第一导电型相反。与漂移区域相比，源极区域和漏极区域被更加高度地掺杂。也可通过从前表面注入来形成源极区域、漂移区域和漏极区域。
在形成LDMOS晶体管之后，所述方法可进一步前进至块83，并且包括将盲通孔或封闭式通孔插入到衬底的前表面中，以使得主体接触区域包围通孔，在块84中，将导电材料插入到盲通孔中，并且在块85中，以电气方式将导电材料耦合到源极区域。
在一些实施例中，将导电材料插入到通孔中包括：将导电材料插入到通孔中并且在通孔的底部形成填充通孔的第一部分，并且将导电材料插入到通孔的上部中，所述导电材料铺衬通孔的侧壁以包围空隙。所述方法可进一步前进至块86，并且包括去除衬底的后表面的一部分以在后表面露出通孔内的导电材料，并且在块87中，将导电层施加于后表面和导电材料。
根据本文中描述的任何一个实施例的包括一个或多个LDMOS晶体管的一个或多个半导体装置可被用于高频功率放大电路，诸如以700 MHz到3.6 GHz的范围中的频率操作的用于蜂窝通信的RF功率放大电路、蜂窝通信网络中的功率转换和多尔蒂(Doherty)配置放大电路。
空间相对术语(诸如，“在…下面”、“在...下方”、“下”、“在...上方”、“上”等)为了容易描述而被使用以解释一个元件相对于第二元件的定位。这些术语旨在包括除了与附图中描绘的那些方位不同的方位之外的所述装置的不同方位。另外，诸如“第一”、“第二”等的术语也被用于描述各种元件、区域、部分等，并且也不旨在是限制性的。相同的术语在描述中始终表示相同的元件。
如本文中所使用，术语“具有”、“含有”、“包含”、“包括”等是开放式术语，所述开放式术语指示陈述的元件或特征的存在，但不排除另外的元件或特征。冠词“a (一)”、“an(一个)”和“the (该)”旨在包括复数以及单数，除非上下文清楚地另外指示。应理解，除非另外具体地指出，否则本文中描述的各种实施例的特征可彼此组合。
虽然已在本文中图示和描述了特定实施例，但本领域普通技术人员将会理解，在不脱离本发明的范围的情况下，各种替代和/或等同实现方式可替换示出和描述的特定实施例。本申请旨在包括本文中讨论的特定实施例的任何修改或变化。因此，旨在本发明仅由权利要求及其等同物限制。

Claims (27)

1.一种半导体装置，包括：
半导体衬底，具有体电阻率ρ ≥ 100 Ohm.cm、前表面和后表面；
至少一个LDMOS(侧向扩散金属氧化物半导体)晶体管，位于半导体衬底中；和
RESURF结构，包括掺杂掩埋层，掺杂掩埋层被布置在半导体衬底中，与前表面和后表面分隔开一定距离，并且与LDMOS晶体管的沟道区域和主体接触区域中的至少一个区域耦合。
2.如权利要求1所述的半导体装置，其中所述掺杂掩埋层连续地延伸贯穿半导体衬底的侧向区域。
3.如权利要求1所述的半导体装置，其中所述掺杂掩埋层在LDMOS晶体管的源极区域、栅极和漏极区域下方连续地延伸。
4.如权利要求1所述的半导体装置，其中所述衬底、所述沟道层和所述掺杂掩埋层掺杂有第一导电型，并且掩埋层的掺杂物浓度大于衬底的掺杂物浓度并且小于沟道区域的掺杂物浓度。
5.如权利要求4所述的半导体装置，其中所述主体接触区域掺杂有第一导电型，并且具有比沟道区域的掺杂物浓度大的掺杂物浓度。
6.如权利要求1所述的半导体装置，其中所述掺杂掩埋层是自耗尽的并且被源极接地。
7.如权利要求1所述的半导体装置，其中所述RESURF结构还包括从栅极朝着LDMOS晶体管的漏极区域延伸的轻掺杂区域。
8.如权利要求1所述的半导体装置，其中所述RESURF结构还包括至少一个场板。
9.如权利要求1所述的半导体装置，其中所述RESURF结构被确定尺寸，以使得在栅极和漏极区域之间的区域中的在前表面的电场小于0.5 MV/cm。
10.如权利要求1所述的半导体装置，还包括：场板，具有从栅极的漏极侧边缘到漏极的栅极侧边缘的0.8 μm到1.2 μm的长度LFP和漂移区上方的0.1 μm到0.2 μm的高度DFP，其中所述栅极具有0.2 μm到0.5 μm的长度LG，漂移区具有从栅极的漏极侧边缘到漏极金属接触部的栅极侧边缘的2.5 μm到3.2 μm的长度LLDD和相对于前表面的0.1 μm到0.5 μm的深度DLDD，并且所述掺杂掩埋层具有相对于前表面的0.5 μm到2.5 μm的深度D。
11.如权利要求1所述的半导体装置，还包括：场板，具有从栅极的漏极侧边缘到漏极的栅极侧边缘的0.4 μm到1.0 μm的长度LFP和漂移区上方的0.05 μm到0.15 μm的高度DFP，其中所述栅极具有0.15 μm到0.3 μm的长度LG，漂移区具有从栅极的漏极侧边缘到漏极金属接触部的栅极侧边缘的0.8 μm到2.5 μm的长度LLDD和相对于前表面的0.1 μm到0.5 μm的深度DLDD，并且所述掺杂掩埋层具有相对于前表面的0.3 μm到2.0 μm的深度D。
12.如权利要求1所述的半导体装置，还包括：场板，具有从栅极的漏极侧边缘到漏极的栅极侧边缘的0.8 μm到2.0 μm的长度LFP和漂移区上方的0.15 μm到0.35 μm的高度DFP，其中所述栅极具有0.3 μm到0.8 μm的长度LG，漂移区具有从栅极的漏极侧边缘到漏极金属接触部的栅极侧边缘的3.0 μm到8.0 μm的长度LLDD和相对于前表面的0.1 μm到1.0 μm的深度DLDD，并且所述掺杂掩埋层具有相对于前表面的0.5 μm到3.0 μm的深度D。
13.如权利要求1所述的半导体装置，其中所述半导体装置具有至少60伏特的击穿电压，同时支持至少0.15 A/mm的饱和电流。
14.如权利要求1所述的半导体装置，还包括：导电通孔，从衬底的前表面延伸到衬底的后表面。
15.如权利要求14所述的半导体装置，其中所述导电通孔被耦合到LDMOS晶体管的源极区域。
16.如权利要求14所述的半导体装置，其中所述导电通孔延伸穿过主体接触区域。
17.如权利要求14所述的半导体装置，其中所述导电通孔包括填充通孔的与后表面相邻的第一导电部分和布置在第一部分上的第二导电部分，第二导电部分铺衬通孔的侧壁并且包围空隙。
18.一种方法，包括：
在包括体电阻率ρ ≥ 100 Ohm.cm的半导体衬底内注入具有第一导电型的掺杂物浓度的自耗尽层；以及
在衬底的前表面中形成LDMOS晶体管，以使得源极区域、沟道区域、漂移区域和漏极区域通过衬底的一部分而与自耗尽层分隔开，其中所述主体接触区域延伸到自耗尽层并且与自耗尽层耦合。
19.如权利要求18所述的方法，其中所述自耗尽层连续地延伸贯穿衬底的侧向区域。
20.如权利要求18所述的方法，其中所述衬底、沟道层和自耗尽层掺杂有第一导电型，并且自耗尽层的掺杂物浓度大于衬底的掺杂物浓度并且小于沟道区域的掺杂浓度。
21.如权利要求20所述的方法，其中所述主体接触区域掺杂有第一导电型，并且具有比沟道区域的掺杂物浓度大的掺杂物浓度。
22.如权利要求18所述的方法，还包括：将通孔插入到衬底的前表面中，以使得主体接触区域包围通孔；
将导电材料插入到通孔中；以及
以电气方式将导电材料耦合到源极区域。
23.如权利要求22所述的方法，其中将导电材料插入到通孔中包括：将导电材料插入到通孔中以在通孔的底部形成填充通孔的第一部分；并且将导电材料插入到通孔的上部中，所述导电材料铺衬通孔的侧壁以形成包围空隙的第二部分。
24.如权利要求22所述的方法，还包括：
去除衬底的后表面的一部分以在后表面露出通孔内的导电材料；以及
将导电层施加于后表面和导电材料。
25.一种半导体装置，包括：
半导体衬底，具有体电阻率ρ ≥ 100 Ohm.cm、前表面和后表面；
至少一个LDMOS晶体管，位于半导体衬底中，所述LDMOS晶体管包括源极区域、漏极区域、沟道区域、漂移区域和主体接触区域，其中源极区域被耦合到衬底的后表面上的导电层；
掺杂掩埋层，被布置在衬底中，与前表面和后表面分隔开一定距离，并且与LDMOS晶体管的主体接触区域耦合；
栅极屏蔽，从栅极朝着LDMOS晶体管的源极区域延伸；和
场板，从栅极朝着LDMOS晶体管的漏极区域延伸。
26.如权利要求25所述的半导体装置，还包括：导电衬底通孔，以电气方式将LDMOS晶体管的源极区域耦合到后表面上的导电层。
27.如权利要求26所述的半导体装置，其中所述导电通孔包括填充通孔的与后表面相邻的第一导电部分和布置在第一部分上的第二导电部分，第二导电部分铺衬通孔的侧壁并且包围空隙。
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