CN107527887A - 一种堆叠封装方法及结构 - Google Patents

一种堆叠封装方法及结构 Download PDF

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CN107527887A
CN107527887A CN201710725688.3A CN201710725688A CN107527887A CN 107527887 A CN107527887 A CN 107527887A CN 201710725688 A CN201710725688 A CN 201710725688A CN 107527887 A CN107527887 A CN 107527887A
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conductive pole
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任玉龙
孙鹏
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明提供了一种堆叠封装方法及结构，其中，方法包括：在晶圆内成型的第一芯片上制备第一导电柱；在第一芯片的上方设置一个或者多个第二芯片，第二芯片上设置有第二导电柱；在晶圆的表面进行封装，形成封装层；将封装层进行减薄，减薄至第一导电柱和第二导电柱的端部露出；在封装层上制备线路层，线路层连接第一导电柱和第二导电柱；在线路层上制备凸点。这种堆叠封装方法先分别制作芯片和晶圆的导电柱，之后在进行堆叠封装，具有制作工艺简单、生产成本低、可靠性高和封装尺寸小的优点。

Description

一种堆叠封装方法及结构
技术领域
本发明涉及半导体封装领域，具体涉及一种堆叠封装方法及结构。
背景技术
三维(Three-Dime，3D)堆叠技术是把不同功能的芯片或结构，通过堆叠技术和过孔互连等微机械加工技术，使其在Z轴方向上形成立体集成和信号连通以及圆片级、芯片级、硅帽封装等封装和可靠性技术为目标的三维立体堆叠加工技术,用于微系统集成，是继片上系统(System On a Chip，SOC)、多芯片模块(Multi Chip Module，MCM)之后发展起来的系统级封装(System In a Package，SIP)的先进制造新技术。
目前有多种基于3D堆叠方法，主要包括：芯片与芯片的堆叠(D2D)、芯片与圆片的堆叠(D2W)以及圆片与圆片的堆叠(W2W)。D2W堆叠方式利用芯片分别与圆片相应功能位置3D堆叠，该种方式主要利用倒装(Flip-Chip，FC)方式和置球(Bump)键合方式实现芯片与圆片电极的互联。从成品率角度考虑，由于D2W方式可以通过筛选，实现合格芯片(Know-Good-Die，KGD)之间的堆叠，因此成品率较高。D2W堆叠方式之间的层间互连主要采用硅通孔(TVS)技术实现，TSV通孔的直径和深度通常较小，对刻蚀技术有较高的要求，制作工艺较复杂，生产成本较高以及封装尺寸大。
发明内容
因此，本发明要解决的技术问题在于克服现有技术中的芯片与圆片的堆叠制作工艺复杂、生产成本高和封装尺寸大至少之一的缺陷。
为此，本发明提供一种堆叠封装方法，包括如下步骤：在晶圆内成型的第一芯片上制备第一导电柱；在所述第一芯片的上方设置一个或者多个第二芯片，所述第二芯片上设置有第二导电柱；在所述晶圆的表面进行封装，形成封装层；将所述封装层进行减薄，减薄至所述第一导电柱和所述第二导电柱的端部露出；在所述封装层上制备线路层，所述线路层连接所述第一导电柱和所述第二导电柱；在所述线路层上制备凸点。
可选地，当所述第二芯片为多个时,所述第二芯片可以为相同的芯片,也可以为不同的芯片。
可选地，所述第一导电柱的高度不小于所述第二芯片的厚度。
可选地，所述第一导电柱底部的尺寸不小于第一焊盘的尺寸。
可选地，所述第二导电柱底部的尺寸不小于第二焊盘的尺寸。
可选地，所述将所述封装层进行减薄，减薄至所述第一导电柱和所述第二导电柱的端部露出的步骤中，所述第一导电柱和第二导电柱低于或者高于所述封装层表面。
可选地,所述在所述线路层上制备凸点的步骤之后，还包括：将所述晶圆进行切割，形成单颗半导体器件。
本发明还提供一种使用上述方法制备的半导体器件。
本发明还提供一种半导体器件结构，包括依次层叠的第一芯片和第二芯片以及用于将所述第一芯片和第二芯片进行键合的键合层，所述第一芯片和第二芯片上方有封装层，所述第一芯片具有第一焊盘，所述第二芯片具有第二焊盘，在所述封装层内部成型有连接所述第一焊盘的第一导电柱和连接所述第二焊盘的第二导电柱，且所述第一导电柱和第二导电柱贯穿所述封装层，所述封装层上有线路层，所述线路层连接所述第一导电柱和第二导电柱，所述线路层上设置有凸点，所述凸点连接所述线路层。
可选地，所述第一导电柱的高度不小于所述第二芯片的厚度。
可选地，当所述第二芯片为多个时，所述第二芯片可以为相同的芯片，也可以为不同的芯片。
本发明技术方案，具有如下优点：
1.本发明提供的堆叠封装方法，包括：在晶圆内成型的第一芯片上制备第一导电柱；在所述第一芯片的上方设置一个或者多个第二芯片，所述第二芯片上设置有第二导电柱；在所述晶圆的表面进行封装，形成封装层；将所述封装层进行减薄，减薄至所述第一导电柱和所述第二导电柱的端部露出；在所述封装层上制备线路层，所述线路层连接所述第一导电柱和所述第二导电柱；在所述线路层上制备凸点。这种堆叠封装方法先分别制作芯片和晶圆的导电柱，之后在进行堆叠封装，具有制作工艺简单、生产成本低、可靠性高和封装尺寸小的优点。
2.本发明提供的半导体器件，包括依次层叠的第一芯片和第二芯片以及用于将所述第一芯片和第二芯片进行键合的键合层，所述第一芯片和第二芯片上方有封装层，所述第一芯片具有第一焊盘，所述第二芯片具有第二焊盘，在所述封装层内部成型有连接所述第一焊盘的第一导电柱和连接所述第二焊盘的第二导电柱，且所述第一导电柱和第二导电柱贯穿所述封装层，所述封装层上有线路层，所述线路层连接所述第一导电柱和第二导电柱，所述线路层上设置有凸点，所述凸点连接所述线路层。这种半导体器件的封装尺寸小、可靠性高、制备简单以及生产成本低。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例1中堆叠封装方法的一个具体示例的流程图；
图2为本发明实施例1中堆叠封装方法的另一个具体示例的流程图；
图3-图20为本发明实施例1中堆叠封装方法的具体步骤示意图；
图21为本发明实施例2中半导体器件的一个具体示例的结构图；
图22为本发明实施例2中半导体器件的另一个具体示例的结构图；
图23为本发明实施例2中半导体器件的另一个具体示例的结构图；
图24为本发明实施例2中半导体器件的另一个具体示例的结构图。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
本实施例提供一种堆叠封装方法，流程图如图1所示。作为本实施例的一个优选方案，流程图如图2所示，包括如下步骤：
S01：在晶圆01内成型的第一芯片10上制备第一导电柱12。晶圆10已经预先制备好，晶圆01内形成若干第一芯片10，如图3所示。在本实施例中，如图4所示，第一芯片10具有两个第一焊盘11，在其它的实施方案中，第一焊盘11还可以为一个或者多个，根据需要合理设置即可；第一焊盘11上方设置有第一导电柱12，为了增加第一焊盘11连接的可靠性，第一导电柱12底部的尺寸大于第一焊盘11的尺寸，在其它的实施例中，第一导电柱12底部的尺寸可以等于第一焊盘11的尺寸，第一导电柱12底部的尺寸也可以小于第一焊盘11的尺寸,根据需要合理设置即可；第一导电柱12的高度大于第一芯片10的厚度，这样可以保证后续减薄工艺后第一导电柱12能够完全露出以及提高连接的可靠性，在其它的实施例中，第一导电柱12的高度可以等于第一芯片10的厚度，根据需要合理设置即可。
S02：在第一芯片10的上方设置一个或者多个第二芯片20，第二芯片20上设置有第二导电柱22。在本实施例中，如图5所示，第二芯片20具有两个第二焊盘21，在其它的实施方案中，第二焊盘21还可以为一个或者多个，根据需要合理设置即可；第二焊盘21上方设置有第二导电柱22，为了增加第二焊盘21连接的可靠性，第二导电柱22底部的尺寸大于第二焊盘21的尺寸，在其它的实施例中，第二导电柱22底部的尺寸可以等于第二焊盘21的尺寸，第二导电柱22底部的尺寸也可以小于第二焊盘21的尺寸，根据需要合理设置即可；第二导电柱22的高度根据需要合理设置即可。在本实施例中，如图6所示，在第一芯片10的上方放置一个第二芯片20，第一芯片10和第二芯片20之间通过粘合材料连接，粘合材料形成键合层30，在其它的实施例中，第一芯片10上方可以放置两个或者更多个第二芯片20，具体个数根据第一芯片10和第二芯片20的实际大小确定，第一芯片10和第二芯片20之间的连接形式也可以是本领域公知的芯片与晶圆的连接方式，如金属键合等，根据需要合理设置即可。当第二芯片20为多个时,以放置两个第二芯片20为例，第二芯片20可以为相同的芯片,如图7所示；也可以为不同的芯片，如图8所示，根据需要合理设置即可。
S03：在晶圆01的表面进行封装，形成封装层40。在本实施例中,封装层40将第一导电柱12和第二导电柱22覆盖，如图9所示，这样制作使得操作简单，对第一导电柱12和第二导电柱22的要求相对较低；当然，在其它实施例中，也可以将封装层40覆盖至第一导电柱12和第二导电柱22平齐位置，这样需要保证第一导电柱12和第二导电柱22的端部在同一水平面，这样可以省去后续减薄的工序步骤，但会增加第一导电柱12和第二导电柱22的制作难度，对控制精度要求较高，可靠性降低，封装尺寸也较大，根据需要合理选择即可。
S04：将封装层40进行减薄，减薄至第一导电柱12和第二导电柱22的端部露出。在本实施例中，减薄后露出第一导电柱12和第二导电柱22的端部，如图10所示，当然，在其它实施例中，减薄后的晶圆01的厚度可以不同，减薄后的厚度越小最终得到的产品封装尺寸也越小，减薄后的厚度根据需要合理选择即可，可以减薄至第二芯片20的第二焊盘22露出，如图11所示，这样得到的产品封装尺寸小，此种情况下，可以省去第二芯片20上制备第二导电柱22的过程，制作过程简单，但减薄过程的控制精度要求较高，根据实际需要合理选择即可。为了便于后续工艺的对准识别，在本实施例中，第一导电柱12和第二导电柱22低于封装层40表面，以第一导电柱12低于封装层40表面为例，如图12所示，其局部A的放大图如图13所示，第二导电柱22与第一导电柱12类似，在此，不再赘述；当然，在其它实施例中，第一导电柱12和第二导电柱22也可以高于封装层40表面，以第一导电柱12高于封装层40表面为例，如图14所示，其局部A的放大图如图15所示，第二导电柱22与第一导电柱12类似，在此，不再赘述；不同的形式实现的难易程度不同，根据需要合理设置即可。
S05：在封装层40上制备线路层50，线路层50连接第一导电柱12和第二导电柱22，如图16所示。
S06：在线路层50上制备凸点60，如图17所示。可选地，还包括在线路层50上制备绝缘层，绝缘层上面再制备凸点60，绝缘层对线路层50起到保护作用，可以增加可靠性及延长使用寿命。
S07：将晶圆01进行切割，形成单颗半导体器件，在本实施例中，在第一芯片10上放置一个第二芯片20，最终得到的单颗半导体器件如图18所示，当然，在其它实施例中，在第一芯片10上放置两个第二芯片20，这两个第二芯片20相同，最终得到的单颗半导体器件如图19所示，这两个第二芯片20不相同，最终得到的单颗半导体器件如图20所示，在其它实施例中，第一芯片10上放置的第二芯片20的个数根据需要合理设置即可，第二芯片20可以设置为相同也可以设置为不相同，根据需要合理设置即可。
本发明提供的堆叠封装方法，包括：在晶圆01内成型的第一芯片10上制备第一导电柱12；在第一芯片10的上方设置一个或者多个第二芯片20，第二芯片20上设置有第二导电柱22；在晶圆01的表面进行封装，形成封装层40；将封装层40进行减薄，减薄至第一导电柱12和第二导电柱22的端部露出；在封装层40上制备线路层50，线路层50连接第一导电柱12和第二导电柱22；在线路层50上制备凸点60。这种堆叠封装方法先分别制作芯片和晶圆的导电柱，之后在进行堆叠封装，具有制作工艺简单、生产成本低、可靠性高和封装尺寸小的优点。
本实施例中的堆叠封装方法，在第一芯片的上方设置一个或者多个第二芯片的步骤之后，还可以包括在第二芯片的上方设置一个或者多个第三芯片，第三芯片上设置有第三导电柱，形成三层堆叠，后续工艺步骤与本实施例公开的堆叠封装方法相同。当然，在第三芯片上方还可以堆叠第四芯片，形成四层堆叠，也可以在第四芯片上方再堆叠，按照这种堆叠方法依次类推，可以形成多层堆叠，在此不再赘述，堆叠层数越多，可以提高集成密度，相应的工艺难度会增加，根据需要合理设置堆叠层数即可。
此外，本实施例中还提供一种半导体器件，采用上述方法制备而成，通过上述方法制备出的半导体器件，可靠性高，封装尺寸小，整体性能好，且制备过程简单，生产效率高及成本低。
实施例2
本施例提供一种半导体器件，如图21所示，包括依次层叠的第一芯片10和第二芯片20以及用于将第一芯片10和第二芯片20进行键合的键合层30，第一芯片10和第二芯片20上方有封装层40，第一芯片10具有第一焊盘11，第二芯片20具有第二焊盘21，在封装层40内部成型有连接第一焊盘11的第一导电柱12和连接第二焊盘21的第二导电柱22，且第一导电柱12和第二导电柱22贯穿封装层40，第一导电柱12的高度大于第二芯片20的厚度，封装层40上有线路层50，线路层50连接第一导电柱12和第二导电柱22，线路层50上设置有凸点60，凸点60连接线路层50。这种半导体器件的封装尺寸小、可靠性高、制备简单以及生产成本低。
可选地，第一导电柱12的高度等于第二芯片20的厚度，如图22所示，这种半导体器件封装尺寸小。
可选地，当第二芯片20为多个时，第二芯片20可以为相同的芯片，也可以为不同的芯片，这种半导体器件集成密度高，能够实现更加复杂的系统功能。在本实施例中，如图23所示，第二芯片20为两个相同的芯片；如图24所示，第二芯片20为两个不相同的芯片。
可选地，在本实施例中，半导体器件还可以包括第三芯片，第三芯片上有第三导电柱，形成三层堆叠结构；也可以在第四芯片上再堆叠，按照这种堆叠方法依次类推，可以形成多层堆叠，在此不再赘述，堆叠层数越多，可以提高集成密度，相应的工艺难度会增加，根据需要合理设置堆叠层数即可。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (11)

1.一种堆叠封装方法，其特征在于，包括如下步骤：
在晶圆内成型的第一芯片上制备第一导电柱；
在所述第一芯片的上方设置一个或者多个第二芯片，所述第二芯片上设置有第二导电柱；
在所述晶圆的表面进行封装，形成封装层；
将所述封装层进行减薄，减薄至所述第一导电柱和所述第二导电柱的端部露出；
在所述封装层上制备线路层，所述线路层连接所述第一导电柱和所述第二导电柱；
在所述线路层上制备凸点。
2.根据权利要求1所述的堆叠封装方法，其特征在于，当所述第二芯片为多个时,所述第二芯片可以为相同的芯片,也可以为不同的芯片。
3.根据权利要求1或者2所述的堆叠封装方法，其特征在于，所述第一导电柱的高度不小于所述第二芯片的厚度。
4.根据权利要求3所述的堆叠封装方法，其特征在于，所述第一导电柱底部的尺寸不小于第一焊盘的尺寸。
5.根据权利要求1-4任一所述的堆叠封装方法，其特征在于，所述第二导电柱底部的尺寸不小于第二焊盘的尺寸。
6.根据权利要求5所述的堆叠封装方法，其特征在于，所述将所述封装层进行减薄，减薄至所述第一导电柱和所述第二导电柱的端部露出的步骤中，所述第一导电柱和第二导电柱低于或者高于所述封装层表面。
7.根据权利要求1-6任一所述的堆叠封装方法，其特征在于，所述在所述线路层上制备凸点的步骤之后，还包括：
将所述晶圆进行切割，形成单颗半导体器件。
8.一种使用权利要求1-7任一方法制备的半导体器件。
9.一种半导体器件结构，其特征在于，包括依次层叠的第一芯片和第二芯片以及用于将所述第一芯片和第二芯片进行键合的键合层，所述第一芯片和第二芯片上方有封装层，所述第一芯片具有第一焊盘，所述第二芯片具有第二焊盘，在所述封装层内部成型有连接所述第一焊盘的第一导电柱和连接所述第二焊盘的第二导电柱，且所述第一导电柱和第二导电柱贯穿所述封装层，所述封装层上有线路层，所述线路层连接所述第一导电柱和第二导电柱，所述线路层上设置有凸点，所述凸点连接所述线路层。
10.根据权利要求9所述的半导体器件结构，其特征在于，所述第一导电柱的高度不小于所述第二芯片的厚度。
11.根据权利要求9或者10所述的半导体器件结构，其特征在于，当所述第二芯片为多个时，所述第二芯片可以为相同的芯片，也可以为不同的芯片。
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