CN104008998A - 多芯片层叠封装方法 - Google Patents
多芯片层叠封装方法 Download PDFInfo
- Publication number
- CN104008998A CN104008998A CN201410253341.XA CN201410253341A CN104008998A CN 104008998 A CN104008998 A CN 104008998A CN 201410253341 A CN201410253341 A CN 201410253341A CN 104008998 A CN104008998 A CN 104008998A
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- CN
- China
- Prior art keywords
- chip
- pad
- wiring layer
- layer
- surface wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410253341.XA CN104008998B (zh) | 2014-06-10 | 2014-06-10 | 多芯片层叠封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410253341.XA CN104008998B (zh) | 2014-06-10 | 2014-06-10 | 多芯片层叠封装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104008998A true CN104008998A (zh) | 2014-08-27 |
CN104008998B CN104008998B (zh) | 2016-08-03 |
Family
ID=51369606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410253341.XA Active CN104008998B (zh) | 2014-06-10 | 2014-06-10 | 多芯片层叠封装方法 |
Country Status (1)
Country | Link |
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CN (1) | CN104008998B (zh) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105845597A (zh) * | 2016-05-13 | 2016-08-10 | 中国航天科技集团公司第九研究院第七七研究所 | 用于硅通孔叠层芯片的测试方法 |
CN107622985A (zh) * | 2017-09-20 | 2018-01-23 | 维沃移动通信有限公司 | 一种PoP封装结构及其封装方法 |
CN107808876A (zh) * | 2016-08-19 | 2018-03-16 | 上海丽恒光微电子科技有限公司 | 芯片封装结构及芯片晶圆级封装方法 |
WO2020093391A1 (zh) * | 2018-11-09 | 2020-05-14 | 华为技术有限公司 | 一种集成有至少两个裸片的芯片 |
CN111362227A (zh) * | 2018-12-25 | 2020-07-03 | 无锡华润矽科微电子有限公司 | Mems传感器封装结构 |
WO2020252497A1 (en) * | 2019-06-10 | 2020-12-17 | Qualcomm Incorporated | Double sided embedded trace substrate |
CN114975333A (zh) * | 2022-07-29 | 2022-08-30 | 广东大普通信技术股份有限公司 | 芯片结构 |
CN117594538A (zh) * | 2024-01-17 | 2024-02-23 | 江阴长电先进封装有限公司 | 芯片堆叠封装结构及其形成方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003110054A (ja) * | 2001-07-19 | 2003-04-11 | Samsung Electronics Co Ltd | ウェーハレベル積層チップパッケージ及びその製造方法 |
CN1708840A (zh) * | 2002-12-20 | 2005-12-14 | 国际商业机器公司 | 三维器件制造方法 |
CN101290889A (zh) * | 2007-04-17 | 2008-10-22 | 新光电气工业株式会社 | 布线板制造方法、半导体器件制造方法和布线板 |
US20100200992A1 (en) * | 2008-09-26 | 2010-08-12 | International Business Machines Corporation | Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced |
CN102270603A (zh) * | 2011-08-11 | 2011-12-07 | 北京大学 | 一种硅通孔互连结构的制作方法 |
-
2014
- 2014-06-10 CN CN201410253341.XA patent/CN104008998B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003110054A (ja) * | 2001-07-19 | 2003-04-11 | Samsung Electronics Co Ltd | ウェーハレベル積層チップパッケージ及びその製造方法 |
CN1708840A (zh) * | 2002-12-20 | 2005-12-14 | 国际商业机器公司 | 三维器件制造方法 |
CN101290889A (zh) * | 2007-04-17 | 2008-10-22 | 新光电气工业株式会社 | 布线板制造方法、半导体器件制造方法和布线板 |
US20100200992A1 (en) * | 2008-09-26 | 2010-08-12 | International Business Machines Corporation | Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced |
CN102270603A (zh) * | 2011-08-11 | 2011-12-07 | 北京大学 | 一种硅通孔互连结构的制作方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105845597A (zh) * | 2016-05-13 | 2016-08-10 | 中国航天科技集团公司第九研究院第七七研究所 | 用于硅通孔叠层芯片的测试方法 |
CN107808876A (zh) * | 2016-08-19 | 2018-03-16 | 上海丽恒光微电子科技有限公司 | 芯片封装结构及芯片晶圆级封装方法 |
CN107622985A (zh) * | 2017-09-20 | 2018-01-23 | 维沃移动通信有限公司 | 一种PoP封装结构及其封装方法 |
WO2020093391A1 (zh) * | 2018-11-09 | 2020-05-14 | 华为技术有限公司 | 一种集成有至少两个裸片的芯片 |
CN111362227A (zh) * | 2018-12-25 | 2020-07-03 | 无锡华润矽科微电子有限公司 | Mems传感器封装结构 |
WO2020252497A1 (en) * | 2019-06-10 | 2020-12-17 | Qualcomm Incorporated | Double sided embedded trace substrate |
US11545435B2 (en) | 2019-06-10 | 2023-01-03 | Qualcomm Incorporated | Double sided embedded trace substrate |
CN114975333A (zh) * | 2022-07-29 | 2022-08-30 | 广东大普通信技术股份有限公司 | 芯片结构 |
CN117594538A (zh) * | 2024-01-17 | 2024-02-23 | 江阴长电先进封装有限公司 | 芯片堆叠封装结构及其形成方法 |
CN117594538B (zh) * | 2024-01-17 | 2024-04-12 | 江阴长电先进封装有限公司 | 芯片堆叠封装结构及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN104008998B (zh) | 2016-08-03 |
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Effective date of registration: 20180614 Address after: 200120 C, 888, west two road, Nanhui new town, Pudong New Area, Shanghai Patentee after: Shanghai stratosphere Intelligent Technology Co.,Ltd. Address before: 250101 two, B block, Qilu Software Park, 1768 Xinjie street, Ji'nan new and high tech Zone, Shandong. Patentee before: SHANDONG SINOCHIP SEMICONDUCTORS Co.,Ltd. |
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Effective date of registration: 20230506 Address after: Room 1125, Block M, 11th Floor, Building 1, No. 158 Shuanglian Road, Qingpu District, Shanghai, 200000 Patentee after: Shanghai Thermosphere Information Technology Co.,Ltd. Address before: 200120 C, 888, west two road, Nanhui new town, Pudong New Area, Shanghai Patentee before: Shanghai stratosphere Intelligent Technology Co.,Ltd. |
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