CN107527800A - 沟槽栅极结构及其制造方法 - Google Patents

沟槽栅极结构及其制造方法 Download PDF

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CN107527800A
CN107527800A CN201610457601.4A CN201610457601A CN107527800A CN 107527800 A CN107527800 A CN 107527800A CN 201610457601 A CN201610457601 A CN 201610457601A CN 107527800 A CN107527800 A CN 107527800A
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polysilicon gate
groove
polysilicon
insulating cell
gate
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CN107527800B (zh
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卞铮
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CSMC Technologies Corp
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Abstract

本发明涉及一种沟槽栅极结构及其制造方法。沟槽栅极结构包括衬底,衬底表面的沟槽,衬底上的绝缘衬垫,所述沟槽内表面的栅氧层,以及所述栅氧层上的多晶硅栅极,所述绝缘衬垫通过自身的斜坡结构与所述沟槽邻接,所述多晶硅栅极从沟槽内沿所述斜坡结构延伸至所述绝缘衬垫上,所述绝缘衬垫包括较衬垫的其他部分下凹的多晶硅栅极拉抬区,从沟槽中伸出的所述多晶硅栅极搭在所述多晶硅栅极拉抬区上。本发明沟槽内的多晶硅栅极与延伸至绝缘衬底上的部分相对独立,因此沟槽深度和接触孔深度不会相互构成限制。多晶硅栅极的光刻步骤与器件的多晶硅光刻在同一步中进行,不需要额外增加光刻版(mask)和光刻层次,因此不会造成这方面成本的提高。

Description

沟槽栅极结构及其制造方法
技术领域
本发明涉及半导体制造技术,特别是涉及一种沟槽栅极结构,还涉及一种沟槽栅极结构的制造方法。
背景技术
传统的沟槽型垂直双扩散金属氧化物半导体场效应管(VDMOS)产品因成本原因,大多采用加大引出沟槽的端部尺寸,在其上打接触孔的方式将沟槽栅极结构引出,如图1所示。该方案的优点是可以利用产品工艺已有的光罩(mask)层次进行,无需增加光罩层次成本。但其缺点是受到沟槽深度、多晶硅厚度、接触孔深度等工艺限制,从而限制了此传统方案的应用。
发明内容
基于此,有必要提供一种设计时相对更灵活的沟槽栅极结构。
一种沟槽栅极结构,包括衬底,衬底表面的沟槽,衬底上的绝缘衬垫,所述沟槽内表面的栅氧层,以及所述栅氧层上的多晶硅栅极,所述绝缘衬垫通过自身的斜坡结构与所述沟槽邻接,所述多晶硅栅极从沟槽内沿所述斜坡结构延伸至所述绝缘衬垫上,所述绝缘衬垫包括较衬垫的其他部分下凹的多晶硅栅极拉抬区,从沟槽中伸出的所述多晶硅栅极是搭在所述多晶硅栅极拉抬区上。
在其中一个实施例中,所述多晶硅栅极拉抬区的所述斜坡结构的宽度与所述沟槽的宽度相等,两个所述宽度的方向均为与所述多晶硅栅极的延伸方向相垂直的方向。
在其中一个实施例中,所述绝缘衬垫为场氧层。
在其中一个实施例中,所述沟槽栅极结构为垂直双扩散金属氧化物半导体场效应管或横向双扩散金属氧化物半导体场效应管的沟槽栅极结构。
还有必要提供一种沟槽栅极结构的制造方法。
一种沟槽栅极结构的制造方法,包括:在衬底表面形成绝缘衬垫,所述绝缘衬垫的一端形成斜坡结构;在所述衬底和绝缘衬垫表面形成硬掩膜;使用光刻胶光刻形成多晶硅栅极窗口;通过所述窗口将露出的硬掩膜刻蚀掉,所述绝缘衬垫因硬掩膜的过刻蚀在所述窗口处形成相对绝缘衬垫的其他部分下凹的多晶硅栅极拉抬区;通过所述窗口刻蚀露出的衬底,形成沟槽;所述绝缘衬垫通过自身的斜坡结构与所述沟槽邻接;进行栅氧氧化,在所述沟槽的内表面形成栅氧层;向所述沟槽内淀积多晶硅,形成多晶硅栅极;所述多晶硅栅极从沟槽内伸至所述多晶硅栅极拉抬区上作为与接触孔接触的区域;将所述硬掩膜剥离。
在其中一个实施例中,所述将所述硬掩膜剥离的步骤之后,还包括步骤:进行多晶硅氧化;进行阱注入和推阱;进行有源区光刻及注入;在所述衬底上形成介质层;形成接触孔,并填充金属形成金属塞;所述金属塞打进所述多晶硅栅极拉抬区上的多晶硅栅极中;在所述介质层上形成与所述金属塞连接的金属连线。
在其中一个实施例中,所述在衬底表面形成绝缘衬垫的步骤是生长场氧层后进行有源区光刻及湿法腐蚀。
在其中一个实施例中,所述形成沟槽的步骤之后、所述进行栅氧氧化的步骤之前,还包括步骤:进行沟槽牺牲氧化,形成牺牲氧化层;剥除所述牺牲氧化层。
在其中一个实施例中,所述向所述沟槽内淀积多晶硅的步骤之后,是通过多晶硅回刻形成所述多晶硅栅极。
在其中一个实施例中,所述多晶硅栅极窗口包括用于形成所述多晶硅栅极与所述金属塞接触的部位的金属塞接触窗口,用于形成所述多晶硅栅极的主体的主体窗口,以及连接所述金属塞接触窗口和主体窗口的连接窗口,所述连接窗口为长方形。
上述沟槽栅极结构的制造方法,将多晶硅栅极位于绝缘衬底上的部分作为与接触孔接触的位置(即作为沟槽栅极引出结构),因此该接触孔下方的绝缘衬底可以作为接触孔刻蚀的阻挡层,不存在必须把工艺窗口做得很小以避免接触孔将多晶硅打穿造成漏电的问题。沟槽内的多晶硅栅极与延伸至绝缘衬底上的多晶硅栅极相对独立,因此沟槽深度和接触孔深度不会相互构成限制,沟槽内的多晶硅厚度与搭在场氧上的多晶硅厚度也不会相互构成限制,使得沟槽栅极的设计更加灵活,便于在线控制。另一方面,多晶硅栅极的光刻步骤与器件的多晶硅光刻在同一步中进行,不需要额外增加光刻版(mask)和光刻层次,因此不会造成这方面成本的提高。
附图说明
通过附图中所示的本发明的优选实施例的更具体说明,本发明的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分,且并未刻意按实际尺寸等比例缩放绘制附图,重点在于示出本发明的主旨。
图1是一种传统的沟槽栅极结构的示意图;
图2是一实施例中沟槽栅极结构的制造方法的流程图;
图3a~图3o为采用图2所示的沟槽栅极结构的制造方法在制造过程中器件的示意图;
图4为步骤S180之后器件的制造流程图;
图5为一实施例中沟槽栅极结构的立体图。
具体实施方式
为了便于理解本发明,下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是,本发明可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是,当元件被称为“固定于”另一个元件,它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件,它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
图2是一实施例中沟槽栅极结构的制造方法的流程图,包括以下步骤:
S110,在衬底表面形成绝缘衬垫。
参见图3b,绝缘衬垫20邻接沟槽的一端为斜坡结构21,以将多晶硅栅极从沟槽内抬升至绝缘衬垫20上。在本实施例中,绝缘衬垫20为场氧层。参见图3a,通过在衬底10上生长场氧层后采用光刻胶11进行有源区光刻及湿法腐蚀形成绝缘衬垫20。
S120,在衬底和绝缘衬垫表面形成硬掩膜。
淀积形成硬掩膜30。在本实施例中,硬掩膜30为氮化硅,在其他实施例中也可以采用本领域习知的其他硬掩膜。
S130,使用光刻胶光刻形成多晶硅栅极窗口。
图3c是步骤S130完成后器件的俯视图,图3d是沿图3c中AA线的剖视图。光刻胶13在光刻后形成多晶硅栅极窗口,多晶硅栅极窗口下方的硬掩膜30露出。图3c中与AA线垂直的虚线表示光刻胶13下方的硬掩膜30的轮廓线。
在本实施例中,多晶硅栅极窗口包括用于形成多晶硅栅极与金属塞接触的部位的金属塞接触窗口31,用于多晶硅栅极的主体的主体窗口35,以及连接金属塞接触窗口31和主体窗口35的连接窗口33。在本实施例中,连接窗口33为长方形且垂直于主体窗口35。主体窗口35可以为网状或其他形状,以实现DMOS元胞区多晶硅栅极的互联。可以理解的,因附图仅示出了器件的一部分结构,所以图3c中仅示出了主体窗口35的部分区域。
S140,将露出的硬掩膜刻蚀掉,绝缘衬垫因过刻蚀形成下凹的多晶硅栅极拉抬区。
刻蚀并去胶,参见图3e,绝缘衬垫20在硬掩膜刻蚀时同样被刻蚀掉一部分,故多晶硅栅极窗口下方的绝缘衬垫20形成下凹的多晶硅栅极拉抬区22,后续形成的多晶硅栅极从沟槽内沿多晶硅栅极拉抬区22伸至绝缘衬垫20上。
S150,刻蚀露出的衬底,形成沟槽。
多晶硅栅极窗口下方的衬底被刻蚀出沟槽12。由于绝缘衬垫20对刻蚀的阻挡作用,沟槽12与绝缘衬垫20的斜坡结构21邻接。
S160,进行栅氧氧化,在沟槽的内表面形成栅氧层。
参见图3f,沟槽12内表面的硅被氧化形成栅氧层41。
S170,向沟槽内淀积多晶硅,形成多晶硅栅极。
参见图3g、图3h、图3i,在本实施例中,是淀积后通过多晶硅回刻,将多余的多晶硅去除,形成多晶硅栅极40。图3h是步骤S170完成后器件的俯视图,图3i是沿图3h中AA线的剖视图。多晶硅栅极40从沟槽内沿斜坡结构21伸至多晶硅栅极拉抬区22上,该多晶硅栅极拉抬区22上的部分(即栅极引出结构)作为打接触孔的区域。
S180,将硬掩膜剥离。
将硬掩膜30剥离。图3j是步骤S180完成后器件的俯视图,图3k是沿图3j中AA线的剖视图。硬掩膜30被剥除后露出下方的绝缘衬垫20。
上述沟槽栅极结构的制造方法,将多晶硅栅极40位于绝缘衬底20上的部分作为与接触孔接触的位置(即作为沟槽栅极引出结构),因此该接触孔下方的绝缘衬底20可以作为接触孔刻蚀的阻挡层,不存在工艺窗口的问题,沟槽内的多晶硅栅极40与延伸至绝缘衬底20上的部分相对独立,因此沟槽深度和接触孔深度(以及相对应的多晶硅厚度)不会相互构成限制,使得沟槽栅极的设计更加灵活,便于在线控制。
另一方面,多晶硅栅极40的光刻步骤(即步骤S130)与器件的多晶硅光刻在同一步中进行,不需要额外增加光刻版(mask)和光刻层次,因此不会造成这方面成本的提高。
步骤S180之后的有源区工艺、介质层工艺、接触孔工艺、金属互连工艺等可以采用现有技术。以下提供一个如图4所示的具体实施例:
S210,进行多晶硅氧化。
在多晶硅的表面形成氧化层。
S220,进行阱注入和推阱。
绝缘衬底20等阻挡层已将不需要进行阱注入的地方阻挡,因此可以不需要光刻直接注入。
S230,进行有源区光刻及注入。
光刻后形成的光刻胶15如图3l所示。
S240,在衬底上形成介质层。
步骤S240完成后器件的剖视图如图3m所示。介质层50为层间介质(ILD),材质可以是二氧化硅、磷硅玻璃(PSG)/硼磷硅玻璃(BPSG)、氮氧化硅、氮化硅等,或者包含这些材质的多层结构。
S250,形成接触孔,并填充金属形成金属塞。
用光刻胶光刻后刻蚀形成接触孔,然后向接触孔内填充金属。金属塞60打进多晶硅栅极拉抬区22上的多晶硅栅极40中形成电性连接。步骤S250完成后器件的剖视图如图3n所示。在本实施例中,金属塞60为钨塞。在其他实施例中也可以采用其他本领域习知的用于填充接触孔的金属。
S260,在介质层上形成与金属塞连接的金属连线。
在介质层上淀积金属后再于金属上使用光刻胶光刻和刻蚀,然后进行金属的合金化处理。步骤S260完成后器件的剖视图如图3o所示。在本实施例中,金属连线70的材质为铝,在其他实施例中,也可以采用其他导电性良好的金属。
在其中一个实施例中,步骤S150和S160之间还包括进行沟槽牺牲氧化,在沟槽内表面形成牺牲氧化层的步骤;以及将牺牲氧化层全部剥除的步骤。牺牲氧化的目的是修复步骤S150沟槽干法刻蚀时形成的缺陷,以及清除沟槽刻蚀后的表面沾污等。从而改善步骤S160栅氧前沟槽的表面状况,以期在栅氧时获得更好的氧化质量。
上述沟槽栅极结构的制造方法尤其适用于DMOS器件(包括VDMOS和LDMOS)。可以理解的,该制造方法同样适用于其他具有沟槽栅极结构的半导体器件。
本发明相应提供一种沟槽栅极结构,参见图3o和图5,图5中的点划线111表示沿此处剖开以剖面示出沟槽栅极的内部结构。沟槽栅极结构包括衬底10,衬底10表面的沟槽,衬底10上的绝缘衬垫20,沟槽内表面的栅氧层41,以及栅氧层41上的多晶硅栅极40。绝缘衬垫20通过自身的斜坡结构21与沟槽邻接,多晶硅栅极40从沟槽内沿斜坡结构21延伸至绝缘衬垫20上,绝缘衬垫20包括较衬垫的其他部分下凹的多晶硅栅极拉抬区22,多晶硅栅极40从沟槽中伸出的部分是搭在多晶硅栅极拉抬区22上。
在其中一个实施例中,多晶硅栅极拉抬区22的斜坡结构21的宽度与沟槽的宽度相等。宽度的方向是指与多晶硅栅极40的延伸方向相垂直的方向。
在其中一个实施例中,绝缘衬垫20为场氧层。在其他实施例中,绝缘衬底20也可以采用其他本领域常用的绝缘材质。通过绝缘衬垫20的场氧形成接触孔与衬底10的隔离,相对于图1中传统技术通过沟槽表面的薄栅氧层进行隔离,隔离效果更加可靠。
上述沟槽栅极结构尤其适用于DMOS器件(包括VDMOS和LDMOS)。可以理解的,该沟槽栅极结构同样适用于其他具有沟槽栅极结构的半导体器件。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种沟槽栅极结构的制造方法,包括:
在衬底表面形成绝缘衬垫,所述绝缘衬垫的一端形成斜坡结构;
在所述衬底和绝缘衬垫表面形成硬掩膜;
使用光刻胶光刻形成多晶硅栅极窗口;
通过所述窗口将露出的硬掩膜刻蚀掉,所述绝缘衬垫因硬掩膜的过刻蚀在所述窗口处形成相对绝缘衬垫的其他部分下凹的多晶硅栅极拉抬区;
通过所述窗口刻蚀露出的衬底,形成沟槽;所述绝缘衬垫通过斜坡结构与所述沟槽邻接;
进行栅氧氧化,在所述沟槽的内表面形成栅氧层;
向所述沟槽内淀积多晶硅,形成多晶硅栅极;所述多晶硅栅极从沟槽内伸至所述多晶硅栅极拉抬区上作为与接触孔接触的区域;
将所述硬掩膜剥离。
2.根据权利要求1所述的方法,其特征在于,所述将所述硬掩膜剥离的步骤之后,还包括步骤:
进行多晶硅氧化;
进行阱注入和推阱;
进行有源区光刻及注入;
在所述衬底上形成介质层;
形成接触孔,并填充金属形成金属塞;所述金属塞打进所述多晶硅栅极拉抬区上的多晶硅栅极中;
在所述介质层上形成与所述金属塞连接的金属连线。
3.根据权利要求1所述的方法,其特征在于,所述在衬底表面形成绝缘衬垫的步骤是生长场氧层后进行有源区光刻及湿法腐蚀。
4.根据权利要求1所述的方法,其特征在于,所述形成沟槽的步骤之后、所述进行栅氧氧化的步骤之前,还包括步骤:
进行沟槽牺牲氧化,形成牺牲氧化层;
剥除所述牺牲氧化层。
5.根据权利要求1所述的方法,其特征在于,所述向所述沟槽内淀积多晶硅的步骤之后,是通过多晶硅回刻形成所述多晶硅栅极。
6.根据权利要求1所述的方法,其特征在于,所述多晶硅栅极窗口包括用于形成所述多晶硅栅极与所述金属塞接触的部位的金属塞接触窗口,用于形成所述多晶硅栅极的主体的主体窗口,以及连接所述金属塞接触窗口和主体窗口的连接窗口,所述连接窗口为长方形。
7.一种沟槽栅极结构,包括衬底,衬底表面的沟槽,衬底上的绝缘衬垫,所述沟槽内表面的栅氧层,以及所述栅氧层上的多晶硅栅极,其特征在于,所述绝缘衬垫通过自身的斜坡结构与所述沟槽邻接,所述多晶硅栅极从沟槽内沿所述斜坡结构延伸至所述绝缘衬垫上,所述绝缘衬垫包括较绝缘衬垫的其他部分下凹的多晶硅栅极拉抬区,从沟槽中伸出的所述多晶硅栅极搭在所述多晶硅栅极拉抬区上。
8.根据权利要求7所述的沟槽栅极结构,其特征在于,所述多晶硅栅极拉抬区的所述斜坡结构的宽度与所述沟槽的宽度相等,两个所述宽度的方向均为与所述多晶硅栅极的延伸方向相垂直的方向。
9.根据权利要求7所述的沟槽栅极结构,其特征在于,所述绝缘衬垫为场氧层。
10.根据权利要求7所述的沟槽栅极结构,其特征在于,所述沟槽栅极结构为垂直双扩散金属氧化物半导体场效应管或横向双扩散金属氧化物半导体场效应管的沟槽栅极结构。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113013086A (zh) * 2020-06-03 2021-06-22 上海积塔半导体有限公司 深沟道隔离结构及其制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111916496B (zh) * 2020-06-18 2022-02-11 南瑞联研半导体有限责任公司 一种igbt栅极总线结构

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1399349A (zh) * 2002-09-09 2003-02-26 北京大学 垂直沟道场效应晶体管及制备方法
JP2004247713A (ja) * 2003-02-12 2004-09-02 Samsung Electronics Co Ltd 不揮発性sonosメモリ素子及びその製造方法
US20070176237A1 (en) * 2002-05-13 2007-08-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US20090065838A1 (en) * 2007-09-12 2009-03-12 Takeshi Nagao Semiconductor memory device and method of manufacturing the same
JP2009071009A (ja) * 2007-09-13 2009-04-02 Hitachi Ltd 半導体装置及びその製造方法
CN101752423A (zh) * 2010-01-08 2010-06-23 无锡新洁能功率半导体有限公司 沟槽型大功率mos器件及其制造方法
CN102184862A (zh) * 2011-04-08 2011-09-14 上海先进半导体制造股份有限公司 沟槽功率器件的栅极沟槽的刻蚀方法
CN102779750A (zh) * 2012-04-23 2012-11-14 上海先进半导体制造股份有限公司 沟槽绝缘栅双极型晶体管的制造方法
CN103578967A (zh) * 2012-07-19 2014-02-12 上海华虹Nec电子有限公司 改善沟槽型igbt 栅极击穿能力的制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
GB2381122B (en) * 2001-10-16 2006-04-05 Zetex Plc Termination structure for a semiconductor device
US6861701B2 (en) * 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
DE10324754B4 (de) * 2003-05-30 2018-11-08 Infineon Technologies Ag Halbleiterbauelement
US7319256B1 (en) * 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
KR20090025757A (ko) * 2007-09-07 2009-03-11 주식회사 동부하이텍 Dmos 트랜지스터 및 그 제조 방법
US8866255B2 (en) * 2008-03-12 2014-10-21 Infineon Technologies Austria Ag Semiconductor device with staggered oxide-filled trenches at edge region
US7915672B2 (en) * 2008-11-14 2011-03-29 Semiconductor Components Industries, L.L.C. Semiconductor device having trench shield electrode structure
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
JP6008377B2 (ja) * 2010-03-03 2016-10-19 ルネサスエレクトロニクス株式会社 Pチャネル型パワーmosfet
JP5136674B2 (ja) * 2010-07-12 2013-02-06 株式会社デンソー 半導体装置およびその製造方法
CN105576025A (zh) * 2014-10-15 2016-05-11 无锡华润华晶微电子有限公司 一种浅沟槽半超结vdmos器件及其制造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070176237A1 (en) * 2002-05-13 2007-08-02 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
CN1399349A (zh) * 2002-09-09 2003-02-26 北京大学 垂直沟道场效应晶体管及制备方法
JP2004247713A (ja) * 2003-02-12 2004-09-02 Samsung Electronics Co Ltd 不揮発性sonosメモリ素子及びその製造方法
US20090065838A1 (en) * 2007-09-12 2009-03-12 Takeshi Nagao Semiconductor memory device and method of manufacturing the same
JP2009071009A (ja) * 2007-09-13 2009-04-02 Hitachi Ltd 半導体装置及びその製造方法
CN101752423A (zh) * 2010-01-08 2010-06-23 无锡新洁能功率半导体有限公司 沟槽型大功率mos器件及其制造方法
CN102184862A (zh) * 2011-04-08 2011-09-14 上海先进半导体制造股份有限公司 沟槽功率器件的栅极沟槽的刻蚀方法
CN102779750A (zh) * 2012-04-23 2012-11-14 上海先进半导体制造股份有限公司 沟槽绝缘栅双极型晶体管的制造方法
CN103578967A (zh) * 2012-07-19 2014-02-12 上海华虹Nec电子有限公司 改善沟槽型igbt 栅极击穿能力的制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113013086A (zh) * 2020-06-03 2021-06-22 上海积塔半导体有限公司 深沟道隔离结构及其制作方法
CN113013086B (zh) * 2020-06-03 2024-02-02 上海积塔半导体有限公司 深沟道隔离结构及其制作方法

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