CN113013086B - 深沟道隔离结构及其制作方法 - Google Patents
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- 238000002955 isolation Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000001020 plasma etching Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 4
- -1 Nitride Nitride Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Element Separation (AREA)
Abstract
本发明公开了一种深沟道隔离结构及其制作方法,制作方法包括:提供半导体衬底,其上依次形成有与所述半导体衬底类型相反的外延层、浅沟道隔离以及氮化物;在浅沟道隔离上进行深沟道隔离的光罩工艺以及反应离子刻蚀;线性氧化,并采用TEOS淀积;TEOS刻蚀,以清除顶部和底部的氧化物;多晶硅淀积,进行CMP工艺以及去除氮化物;淀积氧化物和氮化物,进行LOCOS光罩工艺以及反应离子刻蚀;LOCOS氧化;去除氮化物;ILD淀积,Contact通过多晶硅与所述半导体衬底连接。本发明通过TEOS刻蚀步骤清除了顶部和底部的氧化物,为多晶硅填充提供了更大空间,从而使得多晶硅与半导体衬底直接接触,省略了接触阱的制作过程。
Description
技术领域
本发明涉及半导体领域,特别涉及一种深沟道隔离(Deep Trench Isolation,DTI)结构及其制作方法。
背景技术
传统的深沟道隔离结构如图1所示,需要与深P阱(Deep P-Well)进行结合以实现P型基板(P-substrate)的接触,具体地,Contact通过Deep P-Well与P-substrate进行连接。相应地,在上述深沟道隔离结构的制作过程中需要制作P型接触阱,还需要进行Deep P-Well的光罩工艺,制作流程复杂。
发明内容
本发明要解决的技术问题是为了克服现有技术中需要制作P型接触阱导致制作流程复杂的缺陷,提供一种深沟道隔离结构及其制作方法。
本发明是通过下述技术方案来解决上述技术问题:
本发明的第一方面提供一种深沟道隔离结构的制作方法,包括以下步骤:
提供半导体衬底,其上依次形成有与所述半导体衬底的类型相反的外延层、浅沟道隔离(shallow trench isolation,STI)以及氮化物;
在浅沟道隔离上进行深沟道隔离的光罩工艺以及反应离子刻蚀;
线性氧化,并采用TEOS(四乙氧基硅烷)淀积;
TEOS刻蚀,以清除顶部和底部的氧化物;
多晶硅淀积,进行CMP(Chemical Mechanical Polishing化学机制抛光)工艺,以及去除氮化物;
淀积氧化物和氮化物,进行LOCOS(Local Oxidation of Silicon局部硅氧化隔离)光罩工艺以及反应离子刻蚀;
LOCOS氧化;
去除氮化物;
ILD(Inter Layer Dielectric,层间介电)淀积,Contact通过多晶硅与所述半导体衬底连接。
较佳地,所述半导体衬底为P型,所述外延层为N型。
较佳地,所述半导体衬底为硅衬底。
本发明的第二方面还提供一种深沟道隔离结构,其利用上述第一方面提供的制作方法制成。
本发明的积极进步效果在于:通过TEOS刻蚀步骤清除了顶部和底部的氧化物,为后续的多晶硅填充提供了更大的空间,从而使得多晶硅与半导体衬底直接接触,省略了通常的接触阱的制作过程。
附图说明
图1为传统的深沟道隔离结构的示意图。
图2为本发明实施例1提供的深沟道隔离结构的制作方法流程图。
图3中(1)-(8)为本发明实施例1提供的深沟道隔离结构的制作过程示意图。
图4为本发明实施例2提供的深沟道隔离结构的示意图。
具体实施方式
下面通过实施例的方式进一步说明本发明,但并不因此将本发明限制在所述的实施例范围之中。
实施例1
本实施例提供一种深沟道隔离结构的制作方法,如图2所示,包括:
步骤S100、提供半导体衬底,其上依次形成有与所述半导体衬底的类型相反的外延层、浅沟道隔离STI以及氮化物Nitride。
在一种可选的实施方式中,半导体衬底为P型硅衬底,也叫P型基板P-substrate,外延层Epi为N型,即N-Epi。
步骤S101、如图3(1)所示,在浅沟道隔离STI上进行深沟道隔离DTI的光罩Mask工艺以及反应离子刻蚀(Reactive Ion Etch,RIE)。
步骤S102、如图3(2)所示,线性氧化,并采用TEOS淀积。
步骤S103、如图3(3)所示,TEOS刻蚀(Etch back),以清除顶部(箭头31所指的位置)和底部(箭头32所指的位置)的氧化物。
步骤S104、如图3(4)所示,多晶硅Poly淀积,进行CMP工艺,以及去除氮化物Nitride。
步骤S105、如图3(5)所示,淀积氧化物和氮化物Nitride,进行LOCOS光罩工艺以及反应离子刻蚀。
步骤S106、如图3(6)所示,LOCOS氧化,使得在顶部角落处如箭头33所指的位置引起的氧化更多。
步骤S107、如图3(7)所示,去除氮化物Nitride。
步骤S108、ILD淀积,Contact通过多晶硅Poly与所述半导体衬底连接。如图3(8)所示,多晶硅Poly与P型基板P-substrate直接接触。
本实施例制作深沟道隔离结构的方法简单,可以应用于180nmBCD(Bipolar CMOSDMOS)工艺平台中,具体地,通过步骤S103,即TEOS刻蚀清除了顶部和底部的氧化物,为后续的多晶硅Poly填充提供了更大的空间,从而使得多晶硅Poly与半导体衬底直接接触,省略了通常的接触阱的制作过程。
实施例2
本实施例提供一种深沟道隔离结构,如图4所示,利用实施例1提供的制作方法制成。
虽然以上描述了本发明的具体实施方式,但是本领域的技术人员应当理解,这仅是举例说明,本发明的保护范围是由所附权利要求书限定的。本领域的技术人员在不背离本发明的原理和实质的前提下,可以对这些实施方式做出多种变更或修改,但这些变更和修改均落入本发明的保护范围。
Claims (4)
1.一种深沟道隔离结构的制作方法,其特征在于,包括以下步骤:
提供半导体衬底,其上依次形成有与所述半导体衬底的类型相反的外延层、浅沟道隔离以及氮化物;
在浅沟道隔离上进行深沟道隔离的光罩工艺以及反应离子刻蚀;
对包括所述半导体衬底、所述外延层、所述浅沟道隔离以及所述氮化物的半导体结构进行线性氧化,并采用TEOS淀积;
对所述半导体结构进行TEOS刻蚀,以清除所述半导体结构顶部和所述半导体结构底部的氧化物;
在所述半导体衬底上进行多晶硅淀积,进行CMP工艺,以及去除所述氮化物;
在所述半导体结构的上方淀积氧化物和氮化物,进行LOCOS光罩工艺以及反应离子刻蚀;
LOCOS氧化;
去除淀积的氮化物;
在所述半导体结构的上方进行ILD淀积,Contact通过多晶硅与所述半导体衬底连接。
2.如权利要求1所述的制作方法,其特征在于,所述半导体衬底为P型,所述外延层为N型。
3.如权利要求1所述的制作方法,其特征在于,所述半导体衬底为硅衬底。
4.一种深沟道隔离结构,其特征在于,利用权利要求1-3中任一项所述制作方法制成。
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US6406987B1 (en) * | 1998-09-08 | 2002-06-18 | Taiwan Semiconductor Manufacturing Company | Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions |
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