US20120261727A1 - Semiconductor device and method for manufacturing local interconnect structure thereof - Google Patents
Semiconductor device and method for manufacturing local interconnect structure thereof Download PDFInfo
- Publication number
- US20120261727A1 US20120261727A1 US13/380,061 US201113380061A US2012261727A1 US 20120261727 A1 US20120261727 A1 US 20120261727A1 US 201113380061 A US201113380061 A US 201113380061A US 2012261727 A1 US2012261727 A1 US 2012261727A1
- Authority
- US
- United States
- Prior art keywords
- sidewall spacers
- drain
- source
- gate
- sacrificial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 185
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 67
- 239000000463 material Substances 0.000 claims description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 10
- 239000007769 metal material Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 238000005530 etching Methods 0.000 description 15
- 239000013078 crystal Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- -1 for example Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000036632 reaction speed Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Definitions
- the present invention relates to the field of semiconductor manufacturing, and specifically, relates to a semiconductor device and a method for manufacturing a local interconnect structure thereof.
- FIG. 1 illustrates contact through-holes formed between a first layer of metal wiring and source/drain regions or a gate region at a lower level in the prior art.
- the contact through-holes 101 , 103 at the source/drain regions and the contact through-holes 105 , 107 at the gate regions of the semiconductor device are not in the same depth, which consequently makes it difficult to etch contact through-holes at different regions in a local interconnect structure and to deposit conductive materials.
- the contact through-holes at the source/drain regions and the gate regions are not in the same depth, it is hard to control the time for stopping etching of the contact through-holes in the local interconnect structure. If the etching is stopped when the bottom of the contact through-hole at the gate region comes into contact with the gate, then the bottoms of the contact through-holes at the source/drain regions usually do not have a sufficient depth to be in contact with the source/drain regions. As a result, the bottoms of the contact through-holes at the source/drain regions will be separated from the source/drain regions by local interconnect dielectric, and thus may not be electrically connected with the source/drain regions.
- gate through-holes gate regions
- source/drain through-holes source/drain through-holes
- the problem that the present invention solves is to provide a semiconductor device and a method for fabricating a local interconnect structure thereof, so as to get rid of over-etching or insufficient etching occurring at formation of contact through-holes at different regions of a semiconductor device.
- the present invention provides a method for manufacturing a local interconnect structure for a semiconductor device, comprising: providing a semiconductor substrate with a gate, wherein the gate is sealed by a cap layer and sidewall spacers; forming sacrificial sidewall spacers outside the sidewall spacers; forming outer sidewall spacers at outer sides of the sacrificial sidewall spacers, wherein the material of the sacrificial sidewall spacers is different from the materials of the sidewall spacers and the outer sidewall spacers; removing the sacrificial sidewall spacers, forming source/drain through-holes between the sidewall spacers and the outer sidewall spacers which are located on the same side, and then forming sacrificial source/drain in the source/drain through-holes; and depositing an interlayer dielectric layer which is made of a material different from that of the sacrificial source/drain; performing planarization and removing the
- planarization is performed to expose the sacrificial source/drain, and then the sacrificial source/drain is removed.
- planarization is performed to expose the cap layer, the interlayer dielectric layer is etched to expose the sacrificial source/drain, and then the sacrificial source/drain is removed.
- the method further comprises removing the gate and a gate dielectric layer therebelow to form a new gate and a new gate dielectric layer.
- the method further comprises removing the gate and the gate dielectric layer therebelow to form a new gate and a new gate dielectric layer.
- the new gate is formed with a metal material.
- the method further comprises removing the sidewall spacers or the outer sidewall spacers, and then forming new sidewall spacers or new outer sidewall spacers.
- the new sidewall spacers or the new outer sidewall spacers are made of a low-k material or a Si 3 N 4 stressed thin film.
- the cap layer and the sidewall spacers are made of Si 3 N 4
- the sacrificial sidewall spacers at outer sides of the sidewall spacers are made of SiO 2
- the outer sidewall spacers at outer sides of the sacrificial sidewall spacers are made of Si 3 N 4 .
- the outer sidewall spacers are located over the source/drain of the semiconductor device or extend over a shallow trench isolation between neighboring semiconductor devices.
- the sacrificial source/drain are grown by means of a Molecular Beam Epitaxy method.
- the sacrificial source/drain is Si, SiGe or Si:C.
- the present invention further provides a semiconductor device having a local interconnect structure for semiconductor device manufactured according to aforesaid method, comprising: a semiconductor substrate with a gate and sidewall spacers formed on two sides of the gate; outer sidewall spacers which are formed at outer sides of the sidewall spacers at a certain spacing distance, and source/drain through-holes formed between the sidewall spacers and the outer sidewall spacers which are located on the same side; a conductive material filled into the source/drain through-holes; and an interlayer dielectric layer filled into recesses between the outer sidewall spacers of neighboring semiconductor devices.
- the sidewall spacers are made of Si 3 N 4
- the outer sidewall spacers are made of Si 3 N 4 .
- the outer sidewall spacers extend over a shallow trench isolation between neighboring semiconductor devices.
- the heads of the gate, the sidewall spacers, the outer sidewall spacers and the conductive material are at the same level.
- the present invention exhibits following advantages: sacrificial sidewall spacers are formed between the sidewall spacers and outer sidewall spacers on the semiconductor substrate, and after the sacrificial sidewall spacers are removed, the contact through-holes of the source/drain regions are formed immediately between the sidewall spacer and outer sidewall spacer on the same side of the gate. After the conductive material is filled into the source/drain through-holes to form vias, the height of the vias shall be same as the height of the gate.
- the contact through-holes which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region, shall be in the same depth; therefore, over-etching or insufficient etching is prevented from occurring to the contact through-holes during formation of the contact through-holes at different regions in the semiconductor device, and the filling effects on the contact through-holes are also improved at the meantime.
- the present invention may integrate the Gate Last Technique at different stages, and newly form gates of different metal materials, and also may further optimize the threshold voltage (Vth) and the saturated drain current (Idsat) between the source and the drain of the semiconductor device.
- Vth threshold voltage
- Idsat saturated drain current
- the sidewall spacers and outer sidewall spacers on two sides of the gate may be removed after formation of a local interconnect structure, then new sidewall spacers or outer sidewall spacers may be formed again, and the material for the new sidewall spacers or the outer sidewall spacers may be a low-k material or a Si 3 N 4 stressed thin film.
- a low-k material is able to reduce the dielectric constants of a local interconnect dielectric/an interlayer dielectric layer, to reduce gate parasitic capacitance and thus to improve performance of a device; meanwhile, the Si 3 N 4 stressed thin film exhibits effects of pulling and pressing the channel material under the gate, so as to improve carrier mobility at the channel region, thereby enhancing the reaction speed of the semiconductor device.
- the outer sidewall spacers on the two sides of the gate in the present invention may be located over the source/drain of the semiconductor device, and also may extend till partly or entirely over the shallow trench isolation between the neighboring semiconductor devices; therefore, it becomes possible to adjust flexibly the widths or positions of source/drain through-holes according to the needs of the widths of source/drain through-holes in practice, so as to improve utilization of chip area and to reduce manufacturing cost as well.
- the present invention is able to manufacture contact through-holes, which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, in a same depth, and to flexibly arrange the widths or positions of the contact through-holes so as to adjust the depth to width ratio of the contact through-holes into a reasonable range, at which a conductive material shall be easily filled; thus it becomes convenient to use a metal material like Cu as the conductive material to fill the contact through-holes, which thus is favorable for improving electrical mobility effects of metal interconnect wiring and also improving both yield and reliability of the product.
- FIG. 1 illustrates contact through-holes formed between a first layer of metal wiring and source/drain regions or a gate region at a lower level in the prior art
- FIG. 2 is a flowchart of a method for manufacturing a local interconnect structure for a semiconductor device according to an embodiment of the present invention
- FIG. 3 is a flowchart of a method for manufacturing a local interconnect structure for a semiconductor device according to another embodiment of the present invention.
- FIGS. 4-14 are cross-sectional views of intermediate structures of a local interconnect structure of a semiconductor device manufactured according to an embodiment of the present invention.
- FIG. 15 is the top view of a local interconnect structure for a semiconductor device according to an embodiment of the present invention.
- FIGS. 16-21 are cross-sectional views of intermediate structures of a local interconnect structure of a semiconductor device according to another embodiment of the present invention.
- FIG. 2 is a flow chart of a method for manufacturing a local interconnect structure for semiconductor device of an embodiment of the present invention.
- the method comprises: performing step S 201 to provide a semiconductor substrate with a gate, wherein the gate is surrounded by a cap layer and sidewall spacers; performing step S 202 to form sacrificial sidewall spacers outside the sidewall spacers, wherein the material for the sacrificial sidewall spacers is different from the material for the cap layer and the sidewall spacers; performing step S 203 to form outer sidewall spacers outside the sacrificial sidewall spacers, wherein the material for the outer sidewall spacers is different from the material for the sacrificial sidewall spacers; performing step S 204 to remove the sacrificial sidewall spacers and to form source/drain through-holes between the sidewall spacer and the outer sidewall spacer on the same side; performing step S 205 to form sacrificial source/drain
- FIG. 3 is a flowchart of a method for fabricating a local interconnect structure for semiconductor device of another embodiment of the present invention.
- the method comprises: performing step S 301 to provide a semiconductor substrate with a gate, wherein the gate is surrounded by a cap layer and sidewall spacers; performing step S 302 to form sacrificial sidewall spacers outside the sidewall spacers, wherein the material for the sacrificial sidewall spacers is different from the material for the cap layer and the sidewall spacers; performing step S 303 to form outer sidewall spacers outside the sacrificial sidewall spacers, wherein the material for the outer sidewall spacers is different from the material for the sacrificial sidewall spacers; performing step S 304 to remove the sacrificial sidewall spacers and to form source/drain through-holes between the sidewall spacer and the outer sidewall spacer on the same side; performing step S 305 to form sacrificial source/
- FIG. 4 to FIG. 14 illustrate the cross-sectional structural diagrams of a local interconnect structure of semiconductor device manufactured according to an embodiment of the present invention.
- a semiconductor substrate 201 on which a gate dielectric layer 202 is positioned, is provided; a patterned gate 203 is positioned on the gate dielectric layer 202 , and the gate 203 is surrounded by a cap layer 205 on its head and sidewall spacers 207 on its two sides; the neighboring semiconductor devices are isolated by a shallow trench isolation 209 .
- the sidewall spacers 207 and the cap layer 205 may be used as a mask to implement ion implantation at the source/drain, so as to form source/drain regions (not shown) in the semiconductor substrate on two sides of the sidewall spacers 207 .
- angle tilt ion implantation may be performed before formation of sidewall spacers 207 to form source/drain extension regions or a Halo implant region.
- the source/drain regions also may be formed through other methods.
- the gate 203 may be polycrystalline silicon, Ti, Co, Ni, Al, W, alloy or a metal silicide; the cap layer 205 and the sidewall spacers 207 may be made of Si 3 N 4 , SiO 2 or SiON, etc.; the length of the gate 203 may be 10 ⁇ 50 nm, and the width of the sidewall spacers 207 may be 10 ⁇ 30 nm.
- sacrificial sidewall spacers 211 are formed outside the sidewall spacers 207 , wherein the material for the sacrificial sidewall spacers 211 is different from the material for the cap layer 205 and the sidewall spacers 207 .
- the sacrificial sidewall spacers 211 may be made of Si 3 N 4 , SiO 2 or SiON, and the width of the sacrificial sidewall spacers 211 may be greater than 10 nm.
- the semiconductor substrate under the sacrificial sidewall spacers corresponds to at least a portion of the source/drain regions of the device, and the width of the sacrificial sidewall spacers is same as the width of source/drain through-holes to be formed. Accordingly, it becomes easy to adjust the width of the source/drain through-holes of the device in the embodiment of the present invention.
- the embodiment of the present invention overcomes such an issue.
- outer sidewall spacers 213 are formed outside the sacrificial sidewall spacers 211 ; the material for the outer sidewall spacers 213 is different from the material for the sacrificial sidewall spacers 211 ; the spacing distance between the sidewall spacer 207 and the outer sidewall spacer 213 on the same side of the gate 203 is same as the width of source/drain through-holes to be formed in the local interconnect structure.
- the outer sidewall spacers 213 may be made of Si 3 N 4 , SiO 2 or SiON, and the width of the outer sidewall spacers 213 may be greater than 10 nm; additionally, the outer sidewall spacers 213 may be located over the source/drain of the semiconductor device, or may extend till partly or entirely over the shallow trench isolation between the neighboring semiconductor devices.
- the outer sidewall spacers 213 also may be formed partly or completely on the shallow trench isolation 209 between the neighboring semiconductor devices, as shown in FIG. 6 .
- the sidewall spacers 207 and the outer sidewall spacers 213 are removed, and source/drain through-holes 214 are formed between the sidewall spacer 207 and the outer sidewall spacer 213 on the same side of the gate 203 .
- the sacrificial sidewall spacers 211 may be removed by means of wet etching, wherein the solution for wet etching may be HF.
- sacrificial source/drain 215 are formed within the source/drain through-holes 214 .
- the sacrificial source/drain 215 may be formed by means of Molecular Beam Epitaxy (MBE) method; the sacrificial source/drain 215 may be Si, SiGe or Si:C.
- MBE Molecular Beam Epitaxy
- the source/drain may be formed after removal of the sacrificial sidewall spacers 211 .
- ion implantation may be performed to the semiconductor substrate to form source/drain regions; alternatively, recesses are formed by way of further etching downwards the semiconductor substrate within the source/drain through-holes 214 , and then the source/drain regions are grown epitaxially within the recesses.
- the method for forming the source/drain regions may be selected according to the needs in practice.
- an interlayer dielectric layer 217 is deposited on the entire crystal surface, on which the semiconductor device is positioned; the interlayer dielectric layer 217 fills the recesses between the outer sidewall spacers of the neighboring semiconductor devices; and the material for the interlayer dielectric layer 217 is different from the material for the sacrificial source/drain 215 .
- the interlayer dielectric layer 217 may be a low-k material, for example, SiO 2 , SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG or BPSG, etc.
- the entire crystal surface is planarized till the gate 203 and the sacrificial source/drain 215 are exposed.
- the Gate Last Technique may be integrated after aforesaid step; namely, the gate 203 and the gate dielectric layer therebelow are removed after the gate is exposed, then a new gate and a gate dielectric layer are formed again; the new gate may be made of a metal material, while the gate dielectric layer may be made of a high-k material.
- the sacrificial source/drain 215 are removed to expose the source/drain regions on the semiconductor substrate 201 ; source/drain through-holes 214 are formed again between the sidewall spacer 217 and the outer sidewall spacer 213 on the same side of the gate 203 .
- the sacrificial source/drain 215 may be removed by means of dry etching or wet etching.
- source/drain may be formed after removal of the sacrificial source/drain 215 .
- ion implantation may be performed to the semiconductor substrate to form the source/drain; alternatively, recesses are formed by way of further etching downwards the semiconductor substrate in the source/drain through-holes 214 , then source/drain regions are grown epitaxially within the recesses.
- the method for forming the source/drain regions may be selected according to the needs in practice.
- source/drain contacts 219 of the local interconnect structure are formed at the source/drain regions at the bottoms of the source/drain through-holes 214 .
- the source/drain contacts 219 may be NiSi.
- a conductive material 216 is deposited on the entire crystal surface, on which the semiconductor device is positioned; the conductive material 216 is filled into the source/drain through-holes 214 to form vias of the local interconnect structure.
- the conductive material 216 may be Cu, W, Al or TiAl, etc.
- the entire crystal surface is planarized till the gate 203 and the vias 211 are completely exposed so as to form the local interconnect structure for semiconductor device of the present invention.
- the Gate Last Technique may be integrated after said step; namely, the gate 203 and the gate dielectric layer therebelow are removed, then a new gate and a gate dielectric layer are formed again; the new gate may be made of a metal material, while the gate dielectric layer may be made of a high-k material.
- the new sidewall spacers or outer sidewall spacers may be made of a low-k material or a Si 3 N 4 stressed thin film.
- the sacrificial source/drain 215 occupy first the space where the source/drain contacts are desirably to be formed; after an interlayer dielectric layer is deposited, the unoccupied space on the surface of the entire semiconductor structure is filled completely by the dielectric; now, the sacrificial source/drain 215 are removed such that source/drain through-holes corresponding to the source/drain regions shall be formed on the flat surface of the semiconductor device structure. As such, a short circuit shall not arise when the contacts are formed within the through-holes.
- FIG. 15 illustrates a top view of a completely formed local interconnect structure for semiconductor device; the dashed blocks therein denote source/drain regions in the semiconductor device.
- FIG. 16 to FIG. 21 illustrate the cross-sectional structural views of a local interconnect structure for semiconductor device manufactured according to another embodiment of the present invention.
- an interlayer dielectric layer 217 (not shown in FIG. 9 ) is deposited on the entire crystal surface of the semiconductor device, the entire crystal surface is planarized, and the planarization shall be stopped immediately when the cap layer 205 on the head of the gate 203 is exposed.
- the interlayer dielectric layer 217 on the entire crystal surface is etched till the sacrificial source/drain 215 are exposed.
- the interlayer dielectric layer 217 may be removed by means of dry etching or wet etching till the sacrificial source/drain 215 are exposed.
- the sacrificial source/drain 215 are removed to expose the source/drain regions on the semiconductor substrate 201 ; then new source/drain through-holes 214 are formed again between the sidewall spacer 207 and the outer sidewall spacer 213 on the same side of the gate 203 .
- the sacrificial source/drain 215 may be removed by means of dry etching or wet etching.
- source/drain contacts 219 of the local interconnect structure are formed at the source/drain regions at the bottoms of the source/drain through-holes 214 .
- the source/drain contacts 219 may be NiSi.
- a conductive material 216 is deposited on the entire crystal surface, on which the semiconductor device is positioned; the conductive material 216 is filled into the source/drain through-holes 214 to form vias of the local interconnect structure.
- the conductive material 216 may be Cu, W, Al, TiAl, etc.
- the entire crystal surface is planarized till the gate 203 and the vias 221 are completely exposed, so as to form the local interconnect structure for semiconductor device of the present invention.
- the Gate Last Technique may be integrated after aforesaid step; namely, the gate 203 and the gate dielectric layer therebelow are removed, then a new gate and a gate dielectric layer are formed again; and the new gate may be made of a metal material, while the gate dielectric layer may be made of a high-k material.
- the top view of the completely formed local interconnect structure for semiconductor device also is similar to the one illustrated in FIG. 15 , wherein the dashed blocks therein denote source/drain regions in the semiconductor device.
- FIG. 14 to FIG. 21 illustrate a local interconnect structure for semiconductor device manufactured according to the embodiment of the present invention.
- the structure comprises: a semiconductor substrate 201 with a gate 203 and sidewall spacers 207 formed on two sides of the gate 203 ; outer sidewall spacers 213 formed outside the sidewall spacers at certain spacing distance; source/drain through-holes formed between the sidewall spacer 207 and the outer sidewall spacer 213 on the same side; a conductive material 221 is filled into the source/drain through-holes; an interlayer dielectric layer 217 is filled into recesses between the outer sidewall spacers of the neighboring semiconductor devices.
- the gate dielectric layer under the gate 203 also is shown in the drawings.
- the sidewall spacers 207 may be Si 3 N 4
- the outer sidewall spacers 221 are Si 3 N 4 .
- the outer sidewall spacers 221 may extend over the shallow trench isolation 209 between the neighboring semiconductor devices.
- the heads of the gate 203 , the sidewall spacers 207 , the outer sidewall spacers 213 and the conductive material 221 are at the same level.
- the present invention proposes to form removable sacrificial sidewall spacers between the sidewall spacers and the outer sidewall spacers on two sides of the patterned gate on the semiconductor substrate, and to form the contact through-holes at the source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers.
- the source/drain through-holes are filled with a conductive material to form vias, the height of the vias shall be same as the height of the gate.
- the contact through-holes which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth, which therefore prevents over-etching or insufficient etching of contact through-holes occurring during formation of contact through-holes in different regions of the semiconductor device, and also improves the filling effects on the contact through-holes at the meantime.
- the present invention may integrate the Gate Last Technique at different stages to form again gates of different metal materials, and may further optimize the threshold voltage (Vth) and the saturated drain current (Idsat) between the source and the drain of the semiconductor device.
- Vth threshold voltage
- Idsat saturated drain current
- the sidewall spacers and outer sidewall spacers on two sides of the gate may be removed after formation of the local interconnect structure, and then new sidewall spacers or outer sidewall spacers may be formed again, and the material for the new sidewall spacers or the outer sidewall spacers may be a low-k material or a Si 3 N 4 stressed thin film.
- the use of a low-k material is able to reduce the dielectric constants of the local interconnect dielectric/the interlayer dielectric layer, to reduce gate parasitic capacitance and to improve device performance; besides, the Si 3 N 4 stressed thin film exhibits effects of pulling and pressing the channel material under the gate, so as to improve carrier mobility at the channel region thereby enhancing the reaction speed of a semiconductor device.
- the outer sidewall spacers on the two sides of the gate in the present invention may be located over the source/drain of the semiconductor device, and also may extend till partly or entirely over the shallow trench isolation between the neighboring semiconductor devices; therefore, it becomes possible to adjust flexibly the widths or the positions of source/drain through-holes according to the needs of the widths of source/drain through-holes in practice, so as to improve utilization of chip area and to reduce manufacturing cost as well.
- the present invention is able to manufacture contact through-holes, which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, in the same depth; besides, the widths or positions of the contact through-holes may be arranged flexibly so as to adjust the depth to width ratio of the contact through-holes into a reasonable range, at which the conductive material shall be easily filled; therefore, it becomes convenient to use a metal material like Cu as the conductive material to fill the contact through-holes, which thus is favorable for improving electrical mobility effects of the metal interconnect wiring and also improves both yield and reliability of the product.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- The present invention relates to the field of semiconductor manufacturing, and specifically, relates to a semiconductor device and a method for manufacturing a local interconnect structure thereof.
- In the back end interconnect process of manufacturing a semiconductor device, it is necessary to establish electrical connection between a first layer of metal wiring and an active device structure at a lower level having both source/drain regions and a gate region. Accordingly, a local interconnect structure of the semiconductor device must be formed in advance before formation of the first layer of metal wiring. The local interconnect structure comprises contact through-holes for connecting the first layer of metal wiring with the source/drain regions or the gate region at a lower level. However, the contact through-holes at the source/drain regions and the gate region of the semiconductor device usually do not have the same length. For example,
FIG. 1 illustrates contact through-holes formed between a first layer of metal wiring and source/drain regions or a gate region at a lower level in the prior art. As shown inFIG. 1 , the contact through-holes holes - Specifically, since the contact through-holes at the source/drain regions and the gate regions are not in the same depth, it is hard to control the time for stopping etching of the contact through-holes in the local interconnect structure. If the etching is stopped when the bottom of the contact through-hole at the gate region comes into contact with the gate, then the bottoms of the contact through-holes at the source/drain regions usually do not have a sufficient depth to be in contact with the source/drain regions. As a result, the bottoms of the contact through-holes at the source/drain regions will be separated from the source/drain regions by local interconnect dielectric, and thus may not be electrically connected with the source/drain regions. However, if the etching is stopped when the bottoms of the contact through-holes at the source/drain regions come into contact with the source/drain regions, then the bottom of the contact through-hole at the gate region shall extend into the gate, which would bring about over-etching of the gate and destroy integrity of the gate. Furthermore, it is likely to cause excessive gate leakage current in the gate dielectric layer below the gate, and thus cause unfavorable effects on controlling of switch for the semiconductor device.
- Therefore, there is an urgent need for a method capable of forming contact through-holes at different regions in a local interconnect structure in back end local interconnect process for manufacturing a semiconductor device, and preventing over-etching of contact through-holes at gate regions (hereinafter referred to as gate through-holes) or under-etching of contact through-holes at source/drain regions (hereinafter referred to as source/drain through-holes).
- The problem that the present invention solves is to provide a semiconductor device and a method for fabricating a local interconnect structure thereof, so as to get rid of over-etching or insufficient etching occurring at formation of contact through-holes at different regions of a semiconductor device.
- In order to solve aforesaid problems, the present invention provides a method for manufacturing a local interconnect structure for a semiconductor device, comprising: providing a semiconductor substrate with a gate, wherein the gate is sealed by a cap layer and sidewall spacers; forming sacrificial sidewall spacers outside the sidewall spacers; forming outer sidewall spacers at outer sides of the sacrificial sidewall spacers, wherein the material of the sacrificial sidewall spacers is different from the materials of the sidewall spacers and the outer sidewall spacers; removing the sacrificial sidewall spacers, forming source/drain through-holes between the sidewall spacers and the outer sidewall spacers which are located on the same side, and then forming sacrificial source/drain in the source/drain through-holes; and depositing an interlayer dielectric layer which is made of a material different from that of the sacrificial source/drain; performing planarization and removing the sacrificial source/drain; forming source/drain contacts at bottom of the source/drain through-holes; depositing a conductive material to fill the source/drain through-holes so as to form contact vias; and performing planarization to expose the gate and the contact vias.
- Optionally, at the step of performing planarization and removing the sacrificial source/drain: planarization is performed to expose the sacrificial source/drain, and then the sacrificial source/drain is removed.
- Optionally, at the step of performing planarization and removing the sacrificial source/drain: planarization is performed to expose the cap layer, the interlayer dielectric layer is etched to expose the sacrificial source/drain, and then the sacrificial source/drain is removed.
- Optionally, after performing planarization to expose the gate and the sacrificial source/drain, the method further comprises removing the gate and a gate dielectric layer therebelow to form a new gate and a new gate dielectric layer.
- Optionally, after performing planarization to expose the gate and the vias, the method further comprises removing the gate and the gate dielectric layer therebelow to form a new gate and a new gate dielectric layer.
- Optionally, the new gate is formed with a metal material.
- Optionally, after performing planarization to expose the gate and the vias, the method further comprises removing the sidewall spacers or the outer sidewall spacers, and then forming new sidewall spacers or new outer sidewall spacers.
- Optionally, the new sidewall spacers or the new outer sidewall spacers are made of a low-k material or a Si3N4 stressed thin film.
- Optionally, the cap layer and the sidewall spacers are made of Si3N4, the sacrificial sidewall spacers at outer sides of the sidewall spacers are made of SiO2, and the outer sidewall spacers at outer sides of the sacrificial sidewall spacers are made of Si3N4.
- Optionally, the outer sidewall spacers are located over the source/drain of the semiconductor device or extend over a shallow trench isolation between neighboring semiconductor devices.
- Optionally, the sacrificial source/drain are grown by means of a Molecular Beam Epitaxy method.
- Optionally, the sacrificial source/drain is Si, SiGe or Si:C.
- The present invention further provides a semiconductor device having a local interconnect structure for semiconductor device manufactured according to aforesaid method, comprising: a semiconductor substrate with a gate and sidewall spacers formed on two sides of the gate; outer sidewall spacers which are formed at outer sides of the sidewall spacers at a certain spacing distance, and source/drain through-holes formed between the sidewall spacers and the outer sidewall spacers which are located on the same side; a conductive material filled into the source/drain through-holes; and an interlayer dielectric layer filled into recesses between the outer sidewall spacers of neighboring semiconductor devices.
- Optionally, the sidewall spacers are made of Si3N4, and the outer sidewall spacers are made of Si3N4.
- Optionally, the outer sidewall spacers extend over a shallow trench isolation between neighboring semiconductor devices.
- Optionally, the heads of the gate, the sidewall spacers, the outer sidewall spacers and the conductive material are at the same level.
- As compared to the prior art, the present invention exhibits following advantages: sacrificial sidewall spacers are formed between the sidewall spacers and outer sidewall spacers on the semiconductor substrate, and after the sacrificial sidewall spacers are removed, the contact through-holes of the source/drain regions are formed immediately between the sidewall spacer and outer sidewall spacer on the same side of the gate. After the conductive material is filled into the source/drain through-holes to form vias, the height of the vias shall be same as the height of the gate. As such, in a local interconnect structure, the contact through-holes, which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region, shall be in the same depth; therefore, over-etching or insufficient etching is prevented from occurring to the contact through-holes during formation of the contact through-holes at different regions in the semiconductor device, and the filling effects on the contact through-holes are also improved at the meantime.
- The present invention may integrate the Gate Last Technique at different stages, and newly form gates of different metal materials, and also may further optimize the threshold voltage (Vth) and the saturated drain current (Idsat) between the source and the drain of the semiconductor device.
- It is also applicable in the present invention that the sidewall spacers and outer sidewall spacers on two sides of the gate may be removed after formation of a local interconnect structure, then new sidewall spacers or outer sidewall spacers may be formed again, and the material for the new sidewall spacers or the outer sidewall spacers may be a low-k material or a Si3N4 stressed thin film. The use of a low-k material is able to reduce the dielectric constants of a local interconnect dielectric/an interlayer dielectric layer, to reduce gate parasitic capacitance and thus to improve performance of a device; meanwhile, the Si3N4 stressed thin film exhibits effects of pulling and pressing the channel material under the gate, so as to improve carrier mobility at the channel region, thereby enhancing the reaction speed of the semiconductor device.
- The outer sidewall spacers on the two sides of the gate in the present invention may be located over the source/drain of the semiconductor device, and also may extend till partly or entirely over the shallow trench isolation between the neighboring semiconductor devices; therefore, it becomes possible to adjust flexibly the widths or positions of source/drain through-holes according to the needs of the widths of source/drain through-holes in practice, so as to improve utilization of chip area and to reduce manufacturing cost as well.
- According to aforesaid technical solution, the present invention is able to manufacture contact through-holes, which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, in a same depth, and to flexibly arrange the widths or positions of the contact through-holes so as to adjust the depth to width ratio of the contact through-holes into a reasonable range, at which a conductive material shall be easily filled; thus it becomes convenient to use a metal material like Cu as the conductive material to fill the contact through-holes, which thus is favorable for improving electrical mobility effects of metal interconnect wiring and also improving both yield and reliability of the product.
-
FIG. 1 illustrates contact through-holes formed between a first layer of metal wiring and source/drain regions or a gate region at a lower level in the prior art; -
FIG. 2 is a flowchart of a method for manufacturing a local interconnect structure for a semiconductor device according to an embodiment of the present invention; -
FIG. 3 is a flowchart of a method for manufacturing a local interconnect structure for a semiconductor device according to another embodiment of the present invention; -
FIGS. 4-14 are cross-sectional views of intermediate structures of a local interconnect structure of a semiconductor device manufactured according to an embodiment of the present invention; -
FIG. 15 is the top view of a local interconnect structure for a semiconductor device according to an embodiment of the present invention; and -
FIGS. 16-21 are cross-sectional views of intermediate structures of a local interconnect structure of a semiconductor device according to another embodiment of the present invention. - The present invention is further described with the specific exemplary embodiments and the accompanying drawings, but it will be understood that they should not be interpreted as limits to the present invention.
-
FIG. 2 is a flow chart of a method for manufacturing a local interconnect structure for semiconductor device of an embodiment of the present invention. As shown inFIG. 2 , the method comprises: performing step S201 to provide a semiconductor substrate with a gate, wherein the gate is surrounded by a cap layer and sidewall spacers; performing step S202 to form sacrificial sidewall spacers outside the sidewall spacers, wherein the material for the sacrificial sidewall spacers is different from the material for the cap layer and the sidewall spacers; performing step S203 to form outer sidewall spacers outside the sacrificial sidewall spacers, wherein the material for the outer sidewall spacers is different from the material for the sacrificial sidewall spacers; performing step S204 to remove the sacrificial sidewall spacers and to form source/drain through-holes between the sidewall spacer and the outer sidewall spacer on the same side; performing step S205 to form sacrificial source/drain within the source/drain through-holes; performing step S206 to deposit an interlayer dielectric layer, whose material is different from the material for the sacrificial source/drain; performing step S207 to implement planarization operation to expose the sacrificial source/drain; performing step S208 to remove the sacrificial source/drain; performing step S209 to form source/drain contacts at the bottoms of the source/drain through-holes; performing step S210 to deposit a conductive material and to fill the source/drain through-holes to form vias; and performing step S211 to implement planarization operation till the gate and the vias are completely exposed. -
FIG. 3 is a flowchart of a method for fabricating a local interconnect structure for semiconductor device of another embodiment of the present invention. As shown inFIG. 3 , the method comprises: performing step S301 to provide a semiconductor substrate with a gate, wherein the gate is surrounded by a cap layer and sidewall spacers; performing step S302 to form sacrificial sidewall spacers outside the sidewall spacers, wherein the material for the sacrificial sidewall spacers is different from the material for the cap layer and the sidewall spacers; performing step S303 to form outer sidewall spacers outside the sacrificial sidewall spacers, wherein the material for the outer sidewall spacers is different from the material for the sacrificial sidewall spacers; performing step S304 to remove the sacrificial sidewall spacers and to form source/drain through-holes between the sidewall spacer and the outer sidewall spacer on the same side; performing step S305 to form sacrificial source/drain within the source/drain through-holes; performing step S306 to deposit an interlayer dielectric layer, whose material is different from the material for the sacrificial source/drain; performing step S307 to implement planarization operation to expose the cap layer on top of the gate; performing step S308 to etch the interlayer dielectric layer till the sacrificial source/drain are exposed; performing step S309 to remove the sacrificial source/drain; performing step S310 to form source/drain contacts at the bottoms of the source/drain through-holes; performing step S311 to deposit a conductive material filling into the source/drain through-holes to form vias; and performing step S312 to implement planarization operation till the gate and the vias are completely exposed. -
FIG. 4 toFIG. 14 illustrate the cross-sectional structural diagrams of a local interconnect structure of semiconductor device manufactured according to an embodiment of the present invention. As shown inFIG. 4 , asemiconductor substrate 201, on which a gatedielectric layer 202 is positioned, is provided; a patternedgate 203 is positioned on the gatedielectric layer 202, and thegate 203 is surrounded by acap layer 205 on its head andsidewall spacers 207 on its two sides; the neighboring semiconductor devices are isolated by ashallow trench isolation 209. - Optionally, the
sidewall spacers 207 and thecap layer 205 may be used as a mask to implement ion implantation at the source/drain, so as to form source/drain regions (not shown) in the semiconductor substrate on two sides of thesidewall spacers 207. For other embodiments of the present invention, angle tilt ion implantation may be performed before formation ofsidewall spacers 207 to form source/drain extension regions or a Halo implant region. The source/drain regions also may be formed through other methods. - In the present embodiment, the
gate 203 may be polycrystalline silicon, Ti, Co, Ni, Al, W, alloy or a metal silicide; thecap layer 205 and thesidewall spacers 207 may be made of Si3N4, SiO2 or SiON, etc.; the length of thegate 203 may be 10˜50 nm, and the width of thesidewall spacers 207 may be 10˜30 nm. - As shown in
FIG. 5 ,sacrificial sidewall spacers 211 are formed outside thesidewall spacers 207, wherein the material for thesacrificial sidewall spacers 211 is different from the material for thecap layer 205 and thesidewall spacers 207. - In the present embodiment, the
sacrificial sidewall spacers 211 may be made of Si3N4, SiO2 or SiON, and the width of thesacrificial sidewall spacers 211 may be greater than 10 nm. The semiconductor substrate under the sacrificial sidewall spacers corresponds to at least a portion of the source/drain regions of the device, and the width of the sacrificial sidewall spacers is same as the width of source/drain through-holes to be formed. Accordingly, it becomes easy to adjust the width of the source/drain through-holes of the device in the embodiment of the present invention. However, because the device size in the prior art is scaling down, thus precision of lithography and etching becomes increasingly demanding, whereas the embodiment of the present invention overcomes such an issue. - Next,
outer sidewall spacers 213 are formed outside thesacrificial sidewall spacers 211; the material for theouter sidewall spacers 213 is different from the material for thesacrificial sidewall spacers 211; the spacing distance between thesidewall spacer 207 and theouter sidewall spacer 213 on the same side of thegate 203 is same as the width of source/drain through-holes to be formed in the local interconnect structure. - In the present embodiment, the
outer sidewall spacers 213 may be made of Si3N4, SiO2 or SiON, and the width of theouter sidewall spacers 213 may be greater than 10 nm; additionally, theouter sidewall spacers 213 may be located over the source/drain of the semiconductor device, or may extend till partly or entirely over the shallow trench isolation between the neighboring semiconductor devices. - In the various embodiments of the present invention, with regard to the practical demands of width or position of the contact through-hole at the gate region, the
outer sidewall spacers 213 also may be formed partly or completely on theshallow trench isolation 209 between the neighboring semiconductor devices, as shown inFIG. 6 . - As shown in
FIG. 7 , in view that the material for thesacrificial sidewall spacers 211 is different from the material for thecap layer 205, thesidewall spacers 207 and theouter sidewall spacers 213, thus thesacrificial sidewall spacers 211 are removed, and source/drain through-holes 214 are formed between thesidewall spacer 207 and theouter sidewall spacer 213 on the same side of thegate 203. - In the present embodiment, the
sacrificial sidewall spacers 211 may be removed by means of wet etching, wherein the solution for wet etching may be HF. - As shown in
FIG. 8 , sacrificial source/drain 215 are formed within the source/drain through-holes 214. - In the present embodiment, the sacrificial source/
drain 215 may be formed by means of Molecular Beam Epitaxy (MBE) method; the sacrificial source/drain 215 may be Si, SiGe or Si:C. - As for other embodiments of the present invention, if no source/drain has been formed at foregoing steps, then the source/drain may be formed after removal of the
sacrificial sidewall spacers 211. For example, ion implantation may be performed to the semiconductor substrate to form source/drain regions; alternatively, recesses are formed by way of further etching downwards the semiconductor substrate within the source/drain through-holes 214, and then the source/drain regions are grown epitaxially within the recesses. The method for forming the source/drain regions may be selected according to the needs in practice. - As shown in
FIG. 9 , aninterlayer dielectric layer 217 is deposited on the entire crystal surface, on which the semiconductor device is positioned; theinterlayer dielectric layer 217 fills the recesses between the outer sidewall spacers of the neighboring semiconductor devices; and the material for theinterlayer dielectric layer 217 is different from the material for the sacrificial source/drain 215. - In the present embodiment, the
interlayer dielectric layer 217 may be a low-k material, for example, SiO2, SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG or BPSG, etc. - As shown in
FIG. 10 , the entire crystal surface is planarized till thegate 203 and the sacrificial source/drain 215 are exposed. - In various embodiments of the present invention, the Gate Last Technique may be integrated after aforesaid step; namely, the
gate 203 and the gate dielectric layer therebelow are removed after the gate is exposed, then a new gate and a gate dielectric layer are formed again; the new gate may be made of a metal material, while the gate dielectric layer may be made of a high-k material. - As shown in
FIG. 11 , the sacrificial source/drain 215 are removed to expose the source/drain regions on thesemiconductor substrate 201; source/drain through-holes 214 are formed again between thesidewall spacer 217 and theouter sidewall spacer 213 on the same side of thegate 203. - In the present embodiment, the sacrificial source/
drain 215 may be removed by means of dry etching or wet etching. - As for other embodiments of the present invention, if no source/drain is formed at foregoing steps, then source/drain may be formed after removal of the sacrificial source/
drain 215. For example, ion implantation may be performed to the semiconductor substrate to form the source/drain; alternatively, recesses are formed by way of further etching downwards the semiconductor substrate in the source/drain through-holes 214, then source/drain regions are grown epitaxially within the recesses. The method for forming the source/drain regions may be selected according to the needs in practice. - As shown in
FIG. 12 , source/drain contacts 219 of the local interconnect structure are formed at the source/drain regions at the bottoms of the source/drain through-holes 214. - In the present embodiment, the source/
drain contacts 219 may be NiSi. - Then, as shown in
FIG. 13 , aconductive material 216 is deposited on the entire crystal surface, on which the semiconductor device is positioned; theconductive material 216 is filled into the source/drain through-holes 214 to form vias of the local interconnect structure. - In the present embodiment, the
conductive material 216 may be Cu, W, Al or TiAl, etc. - Finally, as shown in
FIG. 14 , the entire crystal surface is planarized till thegate 203 and thevias 211 are completely exposed so as to form the local interconnect structure for semiconductor device of the present invention. - In various embodiments of the present invention, the Gate Last Technique may be integrated after said step; namely, the
gate 203 and the gate dielectric layer therebelow are removed, then a new gate and a gate dielectric layer are formed again; the new gate may be made of a metal material, while the gate dielectric layer may be made of a high-k material. - It is also applicable in other embodiments of the present invention to remove the
sidewall spacers 207 orouter sidewall spacers 213 on the two sides of thegate 203, and then to form new sidewall spacers or outer sidewall spacers; the new sidewall spacers or outer sidewall spacers may be made of a low-k material or a Si3N4 stressed thin film. - For the embodiment of the present invention, if the conductive contacts are formed immediately after removal of the sacrificial sidewall spacers, the surface of the entire device would be covered with the metal, which nonetheless is hard to remove completely. However, according to the method of the embodiment of the present invention, the sacrificial source/
drain 215 occupy first the space where the source/drain contacts are desirably to be formed; after an interlayer dielectric layer is deposited, the unoccupied space on the surface of the entire semiconductor structure is filled completely by the dielectric; now, the sacrificial source/drain 215 are removed such that source/drain through-holes corresponding to the source/drain regions shall be formed on the flat surface of the semiconductor device structure. As such, a short circuit shall not arise when the contacts are formed within the through-holes. - As shown,
FIG. 15 illustrates a top view of a completely formed local interconnect structure for semiconductor device; the dashed blocks therein denote source/drain regions in the semiconductor device. -
FIG. 16 toFIG. 21 illustrate the cross-sectional structural views of a local interconnect structure for semiconductor device manufactured according to another embodiment of the present invention. As shown inFIG. 16 , after an interlayer dielectric layer 217 (not shown inFIG. 9 ) is deposited on the entire crystal surface of the semiconductor device, the entire crystal surface is planarized, and the planarization shall be stopped immediately when thecap layer 205 on the head of thegate 203 is exposed. - As shown in
FIG. 17 , theinterlayer dielectric layer 217 on the entire crystal surface is etched till the sacrificial source/drain 215 are exposed. - In the present embodiment, the
interlayer dielectric layer 217 may be removed by means of dry etching or wet etching till the sacrificial source/drain 215 are exposed. - As shown in
FIG. 18 , the sacrificial source/drain 215 are removed to expose the source/drain regions on thesemiconductor substrate 201; then new source/drain through-holes 214 are formed again between thesidewall spacer 207 and theouter sidewall spacer 213 on the same side of thegate 203. - In the present embodiment, the sacrificial source/
drain 215 may be removed by means of dry etching or wet etching. - As shown in
FIG. 19 , source/drain contacts 219 of the local interconnect structure are formed at the source/drain regions at the bottoms of the source/drain through-holes 214. - In the present embodiment, the source/
drain contacts 219 may be NiSi. - Then, as shown in
FIG. 20 , aconductive material 216 is deposited on the entire crystal surface, on which the semiconductor device is positioned; theconductive material 216 is filled into the source/drain through-holes 214 to form vias of the local interconnect structure. - In the present embodiment, the
conductive material 216 may be Cu, W, Al, TiAl, etc. - Finally, as shown in
FIG. 21 , the entire crystal surface is planarized till thegate 203 and thevias 221 are completely exposed, so as to form the local interconnect structure for semiconductor device of the present invention. - In different embodiments of the present invention, the Gate Last Technique may be integrated after aforesaid step; namely, the
gate 203 and the gate dielectric layer therebelow are removed, then a new gate and a gate dielectric layer are formed again; and the new gate may be made of a metal material, while the gate dielectric layer may be made of a high-k material. - It is also applicable in other embodiments of the present invention to remove the
sidewall spacers 207 orouter sidewall spacers 213 on two sides of thegate 203, and then to form new sidewall spacers or outer sidewall spacers; and the new sidewall spacers or outer sidewall spacers may be made of a low-k material or a Si3N4 stressed thin film. - In the present embodiment, the top view of the completely formed local interconnect structure for semiconductor device also is similar to the one illustrated in
FIG. 15 , wherein the dashed blocks therein denote source/drain regions in the semiconductor device. - As shown,
FIG. 14 toFIG. 21 illustrate a local interconnect structure for semiconductor device manufactured according to the embodiment of the present invention. The structure comprises: asemiconductor substrate 201 with agate 203 andsidewall spacers 207 formed on two sides of thegate 203;outer sidewall spacers 213 formed outside the sidewall spacers at certain spacing distance; source/drain through-holes formed between thesidewall spacer 207 and theouter sidewall spacer 213 on the same side; aconductive material 221 is filled into the source/drain through-holes; aninterlayer dielectric layer 217 is filled into recesses between the outer sidewall spacers of the neighboring semiconductor devices. The gate dielectric layer under thegate 203 also is shown in the drawings. - Optionally, the
sidewall spacers 207 may be Si3N4, and theouter sidewall spacers 221 are Si3N4. - Optionally, the
outer sidewall spacers 221 may extend over theshallow trench isolation 209 between the neighboring semiconductor devices. - Preferably, in the embodiments of the present invention, the heads of the
gate 203, thesidewall spacers 207, theouter sidewall spacers 213 and theconductive material 221 are at the same level. - The present invention proposes to form removable sacrificial sidewall spacers between the sidewall spacers and the outer sidewall spacers on two sides of the patterned gate on the semiconductor substrate, and to form the contact through-holes at the source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form vias, the height of the vias shall be same as the height of the gate. As such, the contact through-holes, which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth, which therefore prevents over-etching or insufficient etching of contact through-holes occurring during formation of contact through-holes in different regions of the semiconductor device, and also improves the filling effects on the contact through-holes at the meantime.
- The present invention may integrate the Gate Last Technique at different stages to form again gates of different metal materials, and may further optimize the threshold voltage (Vth) and the saturated drain current (Idsat) between the source and the drain of the semiconductor device.
- It is also applicable in the present invention that the sidewall spacers and outer sidewall spacers on two sides of the gate may be removed after formation of the local interconnect structure, and then new sidewall spacers or outer sidewall spacers may be formed again, and the material for the new sidewall spacers or the outer sidewall spacers may be a low-k material or a Si3N4 stressed thin film. The use of a low-k material is able to reduce the dielectric constants of the local interconnect dielectric/the interlayer dielectric layer, to reduce gate parasitic capacitance and to improve device performance; besides, the Si3N4 stressed thin film exhibits effects of pulling and pressing the channel material under the gate, so as to improve carrier mobility at the channel region thereby enhancing the reaction speed of a semiconductor device.
- The outer sidewall spacers on the two sides of the gate in the present invention may be located over the source/drain of the semiconductor device, and also may extend till partly or entirely over the shallow trench isolation between the neighboring semiconductor devices; therefore, it becomes possible to adjust flexibly the widths or the positions of source/drain through-holes according to the needs of the widths of source/drain through-holes in practice, so as to improve utilization of chip area and to reduce manufacturing cost as well.
- According to aforesaid technical solution, the present invention is able to manufacture contact through-holes, which establishes electrical connection between the subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, in the same depth; besides, the widths or positions of the contact through-holes may be arranged flexibly so as to adjust the depth to width ratio of the contact through-holes into a reasonable range, at which the conductive material shall be easily filled; therefore, it becomes convenient to use a metal material like Cu as the conductive material to fill the contact through-holes, which thus is favorable for improving electrical mobility effects of the metal interconnect wiring and also improves both yield and reliability of the product.
- The present invention though is described with preferred embodiments, yet they should not be understood as limits to the present invention. A person of ordinary skill in the art should appreciate that any possible modification and change could be made without departing from the spirit and the scope of the invention. Accordingly, the scope of the present invention should be understood as the scope defined by the appended claims of the present invention.
Claims (16)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010259626.6 | 2010-08-20 | ||
CN201010259626.6A CN102376630B (en) | 2010-08-20 | 2010-08-20 | Semiconductor device and method for manufacturing local interconnect structure thereof |
CN201010259626 | 2010-08-20 | ||
PCT/CN2011/071346 WO2012022144A1 (en) | 2010-08-20 | 2011-02-27 | Semiconductor device and manufacturing method of its local interconnect structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20120261727A1 true US20120261727A1 (en) | 2012-10-18 |
US8987136B2 US8987136B2 (en) | 2015-03-24 |
Family
ID=45604729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/380,061 Active 2032-10-01 US8987136B2 (en) | 2010-08-20 | 2011-02-27 | Semiconductor device and method for manufacturing local interconnect structure thereof |
Country Status (3)
Country | Link |
---|---|
US (1) | US8987136B2 (en) |
CN (1) | CN102376630B (en) |
WO (1) | WO2012022144A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150270176A1 (en) * | 2014-03-19 | 2015-09-24 | Globalfoundries Inc. | Methods of forming reduced resistance local interconnect structures and the resulting devices |
US10290544B2 (en) | 2017-10-10 | 2019-05-14 | Globalfoundries Inc. | Methods of forming conductive contact structures to semiconductor devices and the resulting structures |
US20190279910A1 (en) * | 2018-03-07 | 2019-09-12 | Globalfoundries Inc. | Contact structures |
JP2020064912A (en) * | 2018-10-15 | 2020-04-23 | パナソニック株式会社 | Manufacturing method of imaging apparatus |
US10748814B2 (en) * | 2017-11-24 | 2020-08-18 | Semiconductor Manufacturing International (Shanghai) Corporation | Fabrication method of semiconductor device by removing sacrificial layer on gate structures |
US20200286782A1 (en) * | 2013-10-30 | 2020-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Semiconductor Integrated Circuit Fabrication |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104752329B (en) * | 2013-12-30 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
US9378963B2 (en) * | 2014-01-21 | 2016-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned contact and method of forming the same |
US9412656B2 (en) * | 2014-02-14 | 2016-08-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reverse tone self-aligned contact |
CN106952866B (en) * | 2016-01-06 | 2020-03-24 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing local interconnection structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087706A (en) * | 1998-04-07 | 2000-07-11 | Advanced Micro Devices, Inc. | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
KR100699813B1 (en) * | 2000-09-27 | 2007-03-27 | 삼성전자주식회사 | Method for manufacturing semiconductor memory device |
-
2010
- 2010-08-20 CN CN201010259626.6A patent/CN102376630B/en active Active
-
2011
- 2011-02-27 WO PCT/CN2011/071346 patent/WO2012022144A1/en active Application Filing
- 2011-02-27 US US13/380,061 patent/US8987136B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087706A (en) * | 1998-04-07 | 2000-07-11 | Advanced Micro Devices, Inc. | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200286782A1 (en) * | 2013-10-30 | 2020-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Semiconductor Integrated Circuit Fabrication |
US11735477B2 (en) * | 2013-10-30 | 2023-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US20150270176A1 (en) * | 2014-03-19 | 2015-09-24 | Globalfoundries Inc. | Methods of forming reduced resistance local interconnect structures and the resulting devices |
US9553028B2 (en) * | 2014-03-19 | 2017-01-24 | Globalfoundries Inc. | Methods of forming reduced resistance local interconnect structures and the resulting devices |
US10290544B2 (en) | 2017-10-10 | 2019-05-14 | Globalfoundries Inc. | Methods of forming conductive contact structures to semiconductor devices and the resulting structures |
US10748814B2 (en) * | 2017-11-24 | 2020-08-18 | Semiconductor Manufacturing International (Shanghai) Corporation | Fabrication method of semiconductor device by removing sacrificial layer on gate structures |
US20190279910A1 (en) * | 2018-03-07 | 2019-09-12 | Globalfoundries Inc. | Contact structures |
CN110246804A (en) * | 2018-03-07 | 2019-09-17 | 格芯公司 | Contact structures |
US10593599B2 (en) * | 2018-03-07 | 2020-03-17 | Globalfoundries Inc. | Contact structures |
US11257718B2 (en) | 2018-03-07 | 2022-02-22 | Globalfoundries U.S. Inc. | Contact structures |
JP2020064912A (en) * | 2018-10-15 | 2020-04-23 | パナソニック株式会社 | Manufacturing method of imaging apparatus |
Also Published As
Publication number | Publication date |
---|---|
WO2012022144A1 (en) | 2012-02-23 |
CN102376630A (en) | 2012-03-14 |
US8987136B2 (en) | 2015-03-24 |
CN102376630B (en) | 2013-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8987136B2 (en) | Semiconductor device and method for manufacturing local interconnect structure thereof | |
US9589845B1 (en) | Fin cut enabling single diffusion breaks | |
TWI523237B (en) | Finfet having source-drain sidewall spacers with reduced heights | |
TWI399856B (en) | Bulk finfet device | |
US9171757B2 (en) | Dual shallow trench isolation liner for preventing electrical shorts | |
US8836031B2 (en) | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices | |
US8053897B2 (en) | Production of a carrier wafer contact in trench insulated integrated SOI circuits having high-voltage components | |
TW201926708A (en) | Semiconductor device | |
JP2006352125A (en) | Method of manufacturing mos field effect transistor having multiple channels, and mos field effect transistor having multiple channels manufactured by the same | |
KR20150094498A (en) | Method for manufacturing semiconductor device and semiconductor device | |
US10832967B2 (en) | Tapered fin-type field-effect transistors | |
US10373875B1 (en) | Contacts formed with self-aligned cuts | |
US20200152504A1 (en) | Airgap spacers formed in conjunction with a late gate cut | |
US20190096880A1 (en) | Semiconductor device and method for manufacturing the same | |
US9330971B2 (en) | Method for fabricating integrated circuits including contacts for metal resistors | |
CN103579004A (en) | Finfet and manufacturing method thereof | |
US9059043B1 (en) | Fin field effect transistor with self-aligned source/drain regions | |
CN103779224A (en) | Manufacturing method of mosfet | |
US10734381B2 (en) | Fin-FET devices | |
US10340362B2 (en) | Spacers for tight gate pitches in field effect transistors | |
US20170005092A1 (en) | Low end parasitic capacitance finfet | |
US9337259B2 (en) | Structure and method to improve ETSOI MOSFETS with back gate | |
CN108987276B (en) | Enlarged sacrificial gate cap for forming self-aligned contacts | |
CN112951765B (en) | Semiconductor structure and forming method thereof | |
US10832966B2 (en) | Methods and structures for a gate cut |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZHONG, HUICAI;LIANG, QINGQING;REEL/FRAME:027433/0461 Effective date: 20111114 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2552); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY Year of fee payment: 8 |