CN107482002A - 具有层叠封装结构的半导体组件及包括该组件的电子设备 - Google Patents

具有层叠封装结构的半导体组件及包括该组件的电子设备 Download PDF

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Publication number
CN107482002A
CN107482002A CN201710428788.XA CN201710428788A CN107482002A CN 107482002 A CN107482002 A CN 107482002A CN 201710428788 A CN201710428788 A CN 201710428788A CN 107482002 A CN107482002 A CN 107482002A
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China
Prior art keywords
infrabasal plate
semiconductor
semiconductor package
package part
conductive
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CN201710428788.XA
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English (en)
Inventor
裵基哲
朴澈雨
李光燮
李相均
张世映
曺治铉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN107482002A publication Critical patent/CN107482002A/zh
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Abstract

提供具有层叠封装结构的半导体组件及包括该组件的电子设备。一种具有层叠封装(POP)结构的半导体组件包括：第一半导体封装件，其具有第一下基板、面对所述第一下基板的第一上基板、以及安装在所述第一下基板的区域上的第一半导体芯片。所述POP结构还包括：第二半导体封装件，其具有堆叠在所述第一半导体封装件上并且与所述第一半导体封装件间隔开的第二下基板、以及安装在所述第二下基板的区域内的第二半导体芯片。至少一个无源元件布置在所述第一半导体封装件和所述第二半导体封装件中的至少一个内，并且电连接到所述第二半导体芯片。

Description

具有层叠封装结构的半导体组件及包括该组件的电子设备
优先权声明
本申请要求于2016年6月8日在韩国知识产权局提交的、申请号为10-2016-0070671的韩国专利申请的优先权，该韩国专利申请的全部公开内容通过引用合并于此。
技术领域
本公开涉及基于层叠封装结构的无源元件的布置。
背景技术
相应于电子设备的高度集成，安装在电子设备上的半导体封装件的集成程度也在增加。因此，已经提出了用于在有限空间内实现更高集成度的封装结构。例如，代替平面安装结构，其中多个半导体封装件垂直堆叠的层叠封装(POP)结构，能够实现高集成度并且允许对电子设备的空间进行更有效的设计。
具有POP结构的半导体芯片可以高速处理大容量数据。在这种情况下，从半导体芯片输出的(或者传送到半导体芯片)的信号可能与半导体封装件中的寄生电感成分耦合，从而引起噪声，导致系统产生逻辑缺陷。
发明内容
本公开的各方面至少要解决上述问题和/或缺陷，并且提供诸如下述的一个或更多个优点。因此，本公开的一方面提供了一种具有POP结构的半导体组件以及一种电子设备，所述半导体组件可以使无源元件与半导体芯片之间的布线路径上存在的电感成分最小化，这是通过布置所述无源元件使得所述无源元件靠近所述半导体芯片实现的，其中所述无源元件包含在所述POP结构中并且被设计用来减小所述半导体封装件中的电感成分。
根据各种实施例的具有POP结构的半导体组件可以包括第一半导体封装件、第二半导体封装件以及至少一个无源元件(例如，去耦电容器)。所述第一半导体封装件可以包括第一下基板、面对所述第一下基板的第一上基板、以及安装在所述第一下基板的区域上的第一半导体芯片。所述第二半导体封装件可以包括堆叠在所述第一半导体封装件上并且与所述第一半导体封装件间隔开的第二下基板、以及安装在所述第二下基板的区域内的第二半导体芯片。至少一个无源元件可以布置在所述第一半导体封装件和所述第二半导体封装件中的至少一个内，并且电连接到所述第二半导体芯片。
从以下结合附图披露了本公开的各种实施例的详细描述中，本公开的其它方面、优点和显著特征对于本领域技术人员将变得显而易见。
附图说明
从以下结合附图的描述中，本公开的特定实施例的前述及其它方面、特征以及优点将更加显而易见，在附图中：
图1A是示出根据本公开的第一实施例的形式的视图，其中去耦电容器布置在具有POP结构的第一半导体封装件中；
图1B是示出根据本公开的第二实施例的形式的视图，其中去耦电容器布置在具有POP结构的第一半导体封装件中；
图2A是示出根据本公开的第一实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中；
图2B是示出根据本公开的第二实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中；
图2C是示出根据本公开的第三实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中；
图2D是示出根据本公开的第四实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中；
图2E是示出根据本公开的第五实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中；
图2F是示出根据本公开的第六实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中；以及
图3是示出了电子设备的配置的视图，在所述电子设备上安装了具有POP结构的半导体组件。
应当注意，贯穿所述附图相似的附图标记用于描述相同或相似的元件、特征和结构。
具体实施方式
下文中，将参考附图描述本公开的各个实施例。因此，本领域普通技术人员将认识到，在不脱离本公开的范围和精神的情况下，可以以各种方式对本文中描述的各个实施例进行修改、等效、和/或替换。关于附图的描述，通过相似的附图标记来标记相似的部件。
在本文公开的内容中，本文中使用的表述“具有”、“可以具有”、“包括”和“包含”、或者“可以包括”和“可以包含”是指存在对应的特征(例如，诸如数值、功能、操作或部件的元素)，但是并不排除存在另外的特征。
在本文公开的内容中，本文中使用的表述“A或B”、“A或/和B中的至少一个”、或者“A或/和B中的一个或多个”等等，可以包括相关列出项中的一个或更多个项的任何和所有组合。例如，术语“A或B”、“A和B中的至少一个”、或者“A或B中的至少一个”可以指如下三种情况中的所有情况：情况(1)，在这种情况下包括至少一个A；情况(2)，在这种情况下包括至少一个B；或者情况(3)，在这种情况下既包括至少一个A也包括至少一个B。
本文中使用的诸如“第一”、“第二”等等的术语，可以指本公开的各个实施例的各个元件，而不限制所述元件。例如，这些术语仅用于区分一个元件与另一个元件，并不限制这些元件的顺序和/或优先级。例如，第一半导体封装件和第二半导体封装件可以代表不同的半导体器件，而与顺序或重要性无关。例如，在不脱离本公开的范围的情况下，第一元件可以被称为第二元件，类似地，第二元件可以被称为第一元件。
应当理解，当一个元件(例如，第一元件)被称为“(可操作地或电气地)与另一个元件(例如，第二元件)耦合或者耦合到另一个元件(例如，第二元件)”或者“连接到另一个元件(例如，第二元件)”时，所述一个元件可以直接与所述另一个元件耦合/耦合到所述另一个元件或者连接到所述另一个元件，或者可以存在介入元件(例如，第三元件)。对照而言，当一个元件(例如，第一元件)被称为“直接与另一个元件(例如，第二元件)耦合或者直接耦合到另一个元件(例如，第二元件)”或者“直接连接到另一个元件(例如，第二元件)”时，应当理解，不存在介入元件(例如，第三元件)。
根据情况，本文中使用的表述“配置成……”例如可以用作如下表述：“适合于……”、“具有……的能力”、“设计成……”、“适于……”、“被用来……”或者“能够……”。术语“配置成……”并不意味着在硬件上“特别设计成……”。相反，表述“装置，配置成……”可以表达这样的意思：所述装置“能够”与另一装置或其它部件一起工作。
本说明书中使用的术语用于描述本公开的特定实施例，并不意图限制本公开的范围。单数形式的术语可能包含复数形式，除非另外说明。除非在本文中另外定义，本文中使用的所有术语，包括技术术语和科学术语在内，具有与本领域技术人员通常理解的含义相同的含义。还应当理解，在本公开的各个实施例中，在字典中定义的并且常用的术语，也应当像在有关的相关领域中的习惯一样解释，而不是理想地或者过分形式化地认知，除非在本文中明确这样定义。在一些情况下，即使术语是在说明书中定义的术语，这样的术语也不能被解释为排除本公开的实施例。
根据本公开的各个实施例的具有层叠封装(POP)结构的半导体组件，可以应用于需要高集成度、大容量以及高速数据处理的电子设备。此外，所述半导体组件可以应用于这样的电子设备：在所述电子设备中，多个元件在有限空间内集成(即，元件的密度高)，这种集成导致设计上有限制。
根据本公开的各个实施例的电子设备可以包括如下电子设备中的至少一种：智能电话、平板电脑(PC)、移动电话、视频电话、电子书阅读器、桌上PC、笔记本PC、上网本计算机、工作站、个人数字助手(PDA)、便携式多媒体播放器(PMP)、MP3播放器、移动医疗设备、照相机和可穿戴设备。
下文中，将参考附图描述根据本公开的各个实施例的具有POP结构的半导体组件。
图1A是示出根据本公开的第一实施例的形式的视图，其中去耦电容器布置在具有POP结构的第一半导体封装件中。
参考图1A，具有POP结构的半导体组件1000a可以包括第一半导体封装件100、第二半导体封装件200、以及至少一个无源元件301(例如，去耦电容器)。
具有POP结构的半导体组件1000a可以具有这样的形式：其中，第二半导体封装件200堆叠在第一半导体封装件100上。然后，可以通过电极层(例如，导电凸块40)或者绝缘层，将第一半导体封装件100与第二半导体封装件200彼此间隔开特定的间隔。所述至少一个去耦电容器301可以与POP结构中的半导体芯片相邻地布置，从而抑制在所述POP结构的布线路径上产生的电阻或电感成分。
第一半导体封装件100可以包括第一下基板110、第一上基板120、以及第一半导体芯片130。
第一下基板110和第一上基板120均可以包括具有至少一个导电图案的印刷电路板。第一下基板110和第一上基板120均可以具有单层或多层结构，在多层结构中多个其中均包含导电图案的绝缘层堆叠。在多层结构的情况下，包含在所述层中的导电图案可以彼此相互电连接。此外，第一下基板110和第一上基板120可以具有对应的形状。例如，第一下基板110和第一上基板120可以具有相同或相似的纵向和横向宽度(即，具有相同或相似的面积和形状)，从而在它们被堆叠时没有任何突出部分地排列。
下基板110可以堆叠在主板10(例如，印刷电路板)上，同时它们之间具有特定的间隔。就这一点而言，第一导电凸块20布置在第一下基板110与主板10之间的间隔空间中，并且至少一个一部分暴露的第一下表面焊盘111可以形成在第一下基板110的下表面上。第一下表面焊盘111可以电连接到第一下基板110中包含的导电图案。第一下表面焊盘111可以连接(或者电连接)到第一导电凸块20的一端，第一导电凸块20的另一端可以连接(或者电连接)到在主板10中形成的焊盘11。因此，第一下基板110可以被第一导电凸块20支撑在主板10上，并且可以电连接到主板10。至少一个用于连接(电连接)到第二导电凸块30的第一上表面焊盘112，可以形成在第一下基板110的上表面上，所述第一上表面焊盘112的一部分是暴露的。第一上表面焊盘112也可以电连接到第一下基板110中包含的导电图案。
第一导电凸块20、以及下文中将要描述的第二导电凸块30和第三导电凸块40，例如，可以包括至少一种金属或者下述中的至少一种：金属合金、导电金属氧化物、导电聚合物以及导电复合材料。此外，第一到第三导电凸块20、30、40不限于图1A中形状和数量，并且例如可以根据布线路径以及半导体封装件的尺寸进行各种修改。
第一半导体芯片130可以布置在第一下基板110上(例如，第一下基板110的上侧的中心部分处)。例如，第一半导体芯片130可以通过导电凸块50电连接到第一下基板110。例如，第一半导体芯片130可以包括用于智能电话、平板PC或者导航设备的片上系统(SOC，System on Chip)型应用处理器(AP)。
第一上基板120可以堆叠在第一下基板110上，同时它们之间有特定间隔。至少一个第二下表面焊盘121可以形成在第一上基板120的下表面上，并且第二导电凸块30可以置于第一上基板120与第一下基板110之间的间隔空间中。第二下表面焊盘121可以电连接到第一上基板120中包含的导电图案。由于第二导电凸块30的另一端连接(或电连接)到第一上基板120的第二下表面焊盘121以及第一下基板110的第一上表面焊盘112，第一上基板120可以被第一下基板110支撑并且可以电连接到第一下基板110。至少一个用于连接(电连接)到第三导电凸块40的第二上表面焊盘122，可以形成在第一上基板120的上表面上，所述第二上表面焊盘122的一部分是暴露的。
第一半导体封装件100还可以包括第一模塑成型层140。第一模塑成型层140可以形成在第一下基板110与第一上基板120之间的间隔空间内。可以通过在第一下基板110与第一上基板120之间填充模塑成型材料形成第一模塑成型层140，使得模塑成型层140包围第二导电凸块30和第一半导体芯片130(即，使得第二导电凸块30和第一半导体芯片130嵌入在模塑成型层140中)。第一模塑成型层140例如可以由环氧树脂模塑料形成，并且可以遮挡和保护第二导电凸块30和第一半导体芯片130免受外部环境(例如，热、湿气、碰撞等等)影响。
第二半导体封装件200可以包括第二下基板210和第二半导体芯片220。此外，第二半导体封装件200还可以包括在第二下基板210上包围第二半导体芯片220的第二模塑成型层240。
第二下基板210可以具有单层或多层结构，在多层结构中多个绝缘层堆叠。构成第二下基板210的层(单层或者多层)中的每一层都可以包括至少一个导电图案，并且所述层的导电图案可以彼此相互电连接。此外，第二下基板210可以具有与上述第一半导体封装件100(或者第一下基板110和第一上基板120)相同或相似的面积和形状。
第二下基板210可以堆叠在第一上基板120上，同时它们之间有特定间隔。至少一个第三下表面焊盘211可以形成在第二下基板210的下表面上，并且第三导电凸块40可以置于第二下基板210与第一上基板120之间。第三下表面焊盘211可以电连接到第二下基板210中包含的导电图案。由于第三下表面焊盘211连接(或电连接)到第三导电凸块40的一端，并且第三导电凸块40的另一端连接(或电连接)到第一上基板120的第二上表面焊盘122，因此第二下基板210与第一上基板120可以彼此电连接。
第二半导体芯片220可以布置在第二下基板210上(例如，第二下基板210的上侧的中心部分处)。第二半导体芯片220例如可以包括易失性存储器芯片，例如动态随机存取存储器(DRAM)或者静态随机存取存储器(SRAM)。此外，第二半导体芯片220可以包括诸如快闪存储器的非易失性存储器芯片。此外，第二半导体芯片220可以包括用于移动设备的双倍数据速率同步动态随机存取存储器(DDR SDRAM)芯片。第二半导体芯片220可以通过倒装芯片焊接方法安装到第二下基板210的上侧上。此外，例如，可以通过使用接合部件(例如UV膜、热固性粘合剂、激光固化粘合剂、超声固化粘合剂、非导电膜(NCF)、各向异性导电膜(ACF)或者非导电膏(NCP))，将第二半导体芯片220安装在第二下基板210上。
可以在第二半导体芯片220的上表面上形成其一部分为暴露的焊盘(未示出)。就这一点而言，由于所述焊盘可以与导电线230的一端接合并且导电线230的另一端可以接合到第二下基板210，因此第二半导体芯片220和第二下基板210可以彼此电连接。可以堆叠多个第二半导体芯片220，并且所堆叠的芯片可以通过穿硅通路方法彼此电连接。
如上所述，第二半导体封装件200还可以包括导电线230和包围第二半导体芯片220的第二模塑成型层240。第二模塑成型层240可以遮挡和保护导电线230和第二半导体芯片220使其免受外界影响。模塑成型层240的宽度可以对应于第二下基板210的面积。
至少一个去耦电容器301可以包括在其相对的侧表面上的电极以及所述电极之间的电介质膜(未示出)。去耦电容器301可以具有多层结构，在该多层结构中堆叠了金属绝缘体金属(MIM)结构。去耦电容器301可以用于帮助向第二半导体芯片220供电。如果第二半导体芯片220中的每单位时间处理速率增加(即，第二半导体芯片220需要大电流)，电流值会瞬间增加，导致电压降现象，于是去耦电容器301会有用。例如，第二半导体芯片220高速处理大容量数据，电子设备的电源单元(未示出)会向第二半导体芯片220提供电力。在这个过程中，去耦电容器301可以通过向第二半导体芯片220提供充电电力来帮助向第二半导体芯片220供电。然后，由于去耦电容器301与第二半导体芯片220布置地彼此非常靠近，去耦电容器301与第二半导体芯片220之间的布线路径导致的电阻和电感成分可以最小化。基于这个事实，去耦电容器301可以向第二半导体芯片220提供最佳供电。
在其中去耦电容器301布置在第一半导体封装件100中的第一实施例中，去耦电容器301可以安装在第一上基板120的上侧上。去耦电容器301可以电连接到至少一个包含在第一上基板120中的导电图案。因此，去耦电容器301可以电连接到与主板10电连接的外部电源单元(未示出)、主板10、以及包括如下部分的导电路径(相对于去耦电容器301的下导电路径)：第一导电凸块20、第一下基板110的导电图案与焊盘111和112、第二导电凸块30、以及第一上基板120的导电图案与焊盘121和122。此外，去耦电容器301可以电连接到包括如下部分的导电路径(相对于去耦电容器301的上导电路径)：第一上基板120的导电图案与焊盘121和122、第三导电凸块40、第二下基板210的导电图案和焊盘211、以及导电线230。即，第二半导体芯片220可以基于相对于上述去耦电容器301的下导电路径和上导电路径接收电力。
去耦电容器301的一个实施例可以安装在第一上基板的上部区域的位置处，在所述位置所述下导电路径和上导电路径可以通过最短的布线距离形成。例如，去耦电容器301可以安装成最大限度地邻近第三导电凸块40，使得所述下导电路径和上导电路径的布线线路可以缩短。
图1B示出了另一个例子，其中去耦电容器置于第一半导体封装件中。图1B中的与图1A中的元件相同或相对应的元件，可以用相同的附图标记标示，或者可以省略。然而，所给出的图1B中的与图1A中的附图标记(例如，301)不同的附图标记(例如，302)是为了方便描述，注意这些元件并不限制成不同的元件。
图1B是示出根据本公开的第二实施例的形式的视图，其中去耦电容器布置在具有POP结构的第一半导体封装件中。
在其中去耦电容器302布置在第一半导体封装件100b中的第二实施例中，去耦电容器302可以嵌入在第一上基板120b中。例如，去耦电容器302可以嵌入在第一上基板120b的内部区域中的位置，所述位置与第二导电凸块30或者第三导电凸块40相邻。去耦电容器302可以电连接到第一上基板120b中包含的导电图案。去耦电容器302可以电连接到与参考图1A描述的导电路径(即，相对于去耦电容器(图1A的301)的所述下导电路径和所述上导电路径)相同或者相对应的导电路径。这样，如果去耦电容器302嵌入在第一上基板120b中，则可以从POP结构排除由于去耦电容器302的布置导致的空间，从而可以以各种方式简单地设计POP结构。
图2A至图2F示出了其中去耦电容器布置在第二半导体封装件中的各种实施例。图2A至图2F中的与图1A中的元件相同或相对应的元件，可以用相同的附图标记标示，或者可以省略。然而，所给出的图2A至图2F中的与图1A中的附图标记(例如，301)不同的附图标记(例如，300a至300f)是为了方便描述，注意这些元件并不限制成不同的元件。
图2A是示出根据本公开的第一实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中。
参考图2A，去耦电容器300a可以与第二半导体芯片220相邻地安装在包含在第二半导体封装件200a中的第二下基板210a的下侧。去耦电容器300a可以电连接到至少一个包含在第二下基板210a中的导电图案。因此，去耦电容器300a可以电连接到与主板10电连接的外部电源单元(未示出)、主板10、以及包括如下部分的导电路径(相对于去耦电容器300a的下导电路径)：第一导电凸块20、第一下基板110的导电图案与焊盘111和112、第二导电凸块30、第一上基板120的导电图案与焊盘121和122、第三导电凸块40、以及第二下基板210a的导电图案和焊盘211。此外，去耦电容器300a可以电连接到包括如下部分的导电路径(相对于去耦电容器300a的上导电路径)：第二下基板210a的导电图案和焊盘211、以及导电线230。因此，第二半导体芯片220可以基于相对于上述去耦电容器300a的下导电路径和上导电路径接收电力。去耦电容器300a的一个实施例可以安装在第二下基板210的下部区域的位置处，在所述位置上述导电路径可以通过最短的布线距离形成。例如，去耦电容器300a可以最大限度地邻近第三导电凸块40安装，延伸到主板10的相对于去耦电容器300a的下导电路径的布线线路、以及延伸到导电线230的相对于去耦电容器300a的上导电路径的布线线路，可以缩短。
图2B是示出根据本公开的第二实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中。
在其中去耦电容器300b布置在第二半导体封装件200b的第二实施例中，去耦电容器300b可以安装在第二下基板210b的下侧中心处。去耦电容器300b可以电连接到至少一个包含在第二下基板210b中的导电图案。因此，第二半导体芯片220可以通过与参考图2A描述的导电路径(即，相对于去耦电容器(图2A的300a)的所述下导电路径和所述上导电路径)相同或者相对应的导电路径接收电力。这样，如果去耦电容器300b安装在第二下基板210b的下部中心区域中，则可以容易地设计第二下基板210b的下部空间。例如，根据情况，可以改变第三导电凸块40的布置，或者可以布置另外的元件。
图2C是示出根据本公开的第三实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中。
在其中去耦电容器300c布置在第二半导体封装件200c中的第三实施例中，去耦电容器300c的至少一部分可以插入并且安装在第二下基板210c中。就这一点而言，可以在第二下基板210c的下表面上形成至少一个具有特定深度的插入凹部212c。插入凹部212c可以具有与去耦电容器300c的形状和面积相对应的形状和面积，以便与去耦电容器300c稳固地啮合。此外，可以在插入凹部212c中布置用于固定插入的去耦电容器300c的固定件或接合件(未示出)。去耦电容器300c可以插入并且安装在插入凹部212c中，从而电连接到第二下基板210c中包含的导电图案。因此，第二半导体芯片220可以通过与参考图2A描述的导电路径(即，相对于去耦电容器(图2A的300a)的所述下导电路径和所述上导电路径)相同或者相对应的导电路径接收电力。这样，如果去耦电容器300c的至少一部分插入并安装在第二下基板210c中，则即使在去耦电容器300c的电容或尺寸增加的情况下，也能够避免去耦电容器300c与第一上基板120的物理交叠。
图2D是示出根据本公开的第四实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中。
在其中去耦电容器300d布置在第二半导体封装件200d中的第四实施例中，去耦电容器300d可以安装在第二下基板210d的上侧上。例如，去耦电容器300d可以嵌入在模塑成型层240d中并且安装在第二下基板210d的上侧上。去耦电容器300d可以电连接到至少一个包含在第二下基板210d中的导电图案。去耦电容器300d可以直接连接到导电线230d的一端，并且导电线230d的另一端连接到第二半导体芯片220。去耦电容器300d与导电线230d的所述一端可以通过键合(bonding)彼此连接。这样，如果去耦电容器300d安装在第二下基板210d的上侧上并且直接连接到导电线230d，去耦电容器300d到第二半导体芯片220的布线路径可以变短，由此电流供给效率或者电感减小效率可以提高。
图2E是示出根据本公开的第五实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中。
在其中去耦电容器300e布置在第二半导体封装件200e中的第五实施例中，去耦电容器300e可以安装在第二下基板210e的上侧上的模塑成型层240e外部。例如，去耦电容器300e可以安装在模塑成型层240e的外部区域的位置处，所述位置靠近第三导电凸块40。去耦电容器300e可以电连接到至少一个包含在第二下基板210e中的导电图案。因此，第二半导体芯片220可以通过与参考图2A描述的导电路径(即，相对于去耦电容器(图2A的300a)的所述下导电路径和所述上导电路径)相同或者相对应的导电路径接收电力。这样，当模塑成型层240e的横向面积或体积减小时，大电容去耦电容器300e可以安装在第二下基板210e上，这是因为不包括模塑成型层240e的第二下基板210e的上部空间得到了保证。
图2F是示出根据本公开的第六实施例的形式的视图，其中去耦电容器布置在具有POP结构的第二半导体封装件中。
在其中去耦电容器300f布置在第二半导体封装件200f中的第六实施例中，去耦电容器300f可以嵌入在第二下基板210f中。例如，去耦电容器300f可以嵌入在第二下基板210f的内部区域的位置处，所述位置邻近导电线230(即，在导电线230与第二下基板210f彼此键合的点的下侧)。去耦电容器300f可以电连接到至少一个包含在第二下基板210f中的导电图案。当第二下基板210f具有多层结构时，去耦电容器300f可以电连接到第二下基板210f的这些层的全部导电图案，或者可以选择性地连接到所述导电图案。因此，第二半导体芯片220可以通过与参考图2A描述的导电路径(即，相对于去耦电容器(图2A的300a)的所述下导电路径和所述上导电路径)相同或者相对应的导电路径接收电力。这样，如果去耦电容器300f嵌入在第二下基板210f中，则可以从POP结构排除由于去耦电容器300f的布置导致的空间，从而可以以各种方式简单地设计所述POP结构。
图3是示意性地示出了电子设备的配置的视图，在所述电子设备安装了根据本公开的实施例的具有POP结构的半导体组件。
图3中的与图1A中的元件相同或相对应的元件，可以用相同的附图标记标示，或者可以省略。尽管图3示出了布置根据第一实施例的具有POP结构的半导体组件，其中如上文中参考图1A所述无源元件布置在第一半导体封装件中，但是根据参考图1B至图2F所描述的各种实施例的具有POP结构的半导体组件也可以安装到所述电子设备中。
参考图3，电子设备2000可以包括外壳70、具有POP结构的半导体组件1000a、主板10和电源单元60。
外壳70可以通过结合第一壳体71与第二壳体72来形成。主板10(例如，印刷电路板)以及电连接到主板10的电源单元60(例如，电池)可以布置在外壳70内(即，在第二壳体72内部)。电源单元60可以通过主板10向具有POP结构的半导体组件1000a供电。
具有POP结构的半导体组件1000a可以包括第一半导体封装件100、第二半导体封装件200、以及至少一个无源元件301(例如，图1A的去耦电容器301)。第一半导体封装件100可以包括第一下基板110、布置在第一下基板110上的第一半导体芯片(未示出)(例如，图1A的第一半导体芯片130)、以及面对第一下基板110的第一上基板120。第二半导体封装件200可以包括第二下基板210、以及布置在第二下基板210上的第二半导体芯片(未示出)(例如，图1A的第二半导体芯片220)。
具有POP结构的半导体组件1000a可以安装在主板10的上侧，同时它们之间有特定间隔。例如，具有POP结构的半导体组件1000a可以用层叠封装方法安装在主板10的上侧上，其中第一半导体封装件100堆叠在主板10的上侧上，并且第二半导体封装件200堆叠在半导体封装件100的上侧上。然后，可以在主板10与第一半导体封装件100之间、以及第一半导体封装件100与第二半导体封装件200之间布置导电凸块(未示出)(例如，图1A的第一导电凸块20和第三导电凸块40)，从而使它们彼此电连接并且彼此物理支撑。此外，甚至可以在第一半导体封装件100的第一下基板110与第一上基板120之间布置导电凸块(未示出)(例如，图1A的第二导电凸块30)。
去耦电容器301可以布置在第一半导体封装件100和第二半导体封装件200中的至少一个内，并且可以电连接到包含在第二半导体封装件200内的所述第二半导体芯片(未示出)。如上文中所提及的，除了第一上基板120的上侧之外，去耦电容器301还可以布置在如下位置中的至少一处从而电连接到所述第二半导体芯片(未示出)：第一上基板120的内部、第二下基板210的下侧、第二下基板210的上侧、以及第二下基板210的内部。以这种方式布置的去耦电容器301可以帮助向所述第二半导体芯片(未示出)供电。例如，如果所述第二半导体芯片(未示出)处理大量数据或者高速处理数据，则去耦电容器301可以通过向所述第二半导体芯片(未示出)提供充电的电力来帮助电源单元60供电。
根据各种实施例的具有POP结构的半导体组件可以包括第一半导体封装件、第二半导体封装件以及至少一个无源元件。
根据各种实施例，所述第一半导体封装件可以包括第一下基板、面对所述第一下基板的第一上基板、以及安装在所述第一下基板的区域上的第一半导体芯片。
根据各种实施例，所述第二半导体封装件可以包括堆叠在所述第一半导体封装件上并且与所述第一半导体封装件间隔开的第二下基板、以及安装在所述第二下基板的区域内的第二半导体芯片。
根据各种实施例，至少一个无源元件可以布置在所述第一半导体封装件和所述第二半导体封装件中的至少一个内，并且电连接到所述第二半导体芯片。
根据各种实施例，所述第一半导体芯片可以包括应用处理器(AP)芯片，并且所述第二半导体芯片可以包括存储器芯片。
根据各种实施例，所述第一下基板、所述第一上基板、以及所述第二下基板可以具有对应的面积或形状。
根据各种实施例，所述第一下基板、所述第一上基板或者所述第二下基板中的至少一个可以包括具有多层结构的印刷电路板，所述多层结构中的每一层包括至少一个导电图案。
根据各种实施例，所述半导体组件可以包括主板。
根据各种实施例，所述第一下基板可以堆叠在所述主板上并且与所述主板间隔开。
根据各种实施例，所述半导体组件还可以包括下述元件中的至少一个：至少一个电连接所述第一下基板与所述主板的第一导电凸块、至少一个电连接所述第一下基板与所述第一上基板的第二导电凸块、或者至少一个电连接所述第一上基板与所述第二下基板的第三导电凸块。
根据各种实施例，所述无源元件可以安装在所述第二下基板的下侧或者所述第二下基板的上侧中的至少一者上。
根据各种实施例，所述无源元件可以电连接到以如下部分为路线的导电路径：所述主板、所述第一导电凸块、所述第一下基板的导电图案和焊盘、所述第二导电凸块、所述第一上基板的导电图案和焊盘、所述第三导电凸块、以及所述第二下基板的导电图案和焊盘。
根据各种实施例，所述无源元件可以电连接到以如下部分为路线的导电路径：至少一条电连接所述第二下基板与所述第二半导体芯片的导电线、以及所述第二下基板的导电图案和焊盘。
根据各种实施例，所述无源元件可以与所述第三导电凸块相邻地安装。
根据各种实施例，所述第二半导体封装件还可以包括：至少一个形成在所述第二下基板的下侧并且具有特定深度的插入凹部。
根据各种实施例，所述无源元件的至少一部分插入并安装在所述插入凹部中。
根据各种实施例，所述第二半导体封装件还可以包括：至少一条电连接所述第二下基板与所述第二半导体芯片的导电线。
根据各种实施例，所述无源元件可以在所述第二下基板上直接连接到所述导电线。
根据各种实施例，所述无源元件可以安装在所述第一上基板的上侧上。
根据各种实施例，所述无源元件可以电连接到以如下部分为路线的导电路径：所述主板、所述第一导电凸块、所述第一下基板的导电图案和焊盘、所述第二导电凸块、以及所述第一上基板的导电图案和焊盘。
根据各种实施例，所述无源元件可以电连接到以如下部分为路线的导电路径：所述第一上基板的导电图案和焊盘、所述第三导电凸块、所述第二下基板的导电图案和焊盘、以及至少一条电连接所述第二下基板与所述第二半导体芯片的导电线。
根据各种实施例的电子设备可以包括具有层叠封装(POP)结构的半导体组件以及电源单元。所述半导体组件包括：第一半导体封装件，其包括第一下基板、面对所述第一下基板的第一上基板、以及安装在所述第一下基板的区域上的第一半导体芯片；第二半导体封装件，其包括堆叠在所述第一半导体封装件上并且与所述第一半导体封装件间隔开的第二下基板、以及安装在所述第二下基板的区域内的第二半导体芯片；以及至少一个无源元件，其布置在所述第一半导体封装件和所述第二半导体封装件中的至少一个内，并且电连接到所述第二半导体芯片。所述电源单元配置成与所述第一半导体芯片的控制相对应地向所述半导体组件供电。
根据各种实施例，所述无源元件可以布置在以下位置中的至少一处：所述第一上基板的上侧、所述第一上基板的内部、所述第二下基板的下侧、所述第二下基板的上侧、或者所述第二下基板的内部。
根据各种实施例，所述具有POP结构的半导体组件还可以包括主板，所述第一半导体封装件坐落在所述主板上。
根据各种实施例，所述电源单元可以布置在所述主板的一侧上。
根据各种实施例，通过在具有POP结构的半导体组件中布置无源元件，使得所述无源元件靠近半导体芯片，所述半导体芯片与所述无源元件之间的布线路径可以缩短并简化，从而可以最小化在所述布线路径上产生的电感成分。
另外，本公开可以提供直接或间接认识到的各种效果。
此外，提供本说明书中公开的实施例是为了描述技术内容或者说为了技术内容的理解，本公开的技术范围不限于此。因此，本公开的范围应当理解为包括基于本公开的技术精神的所有改变或者各种实施例。

Claims (15)

1.一种具有层叠封装(POP)结构的半导体组件，所述半导体组件包括：
第一半导体封装件，其包括第一下基板、面对所述第一下基板的第一上基板、以及安装在所述第一下基板的区域上的第一半导体芯片；
第二半导体封装件，其包括堆叠在所述第一半导体封装件上并且与所述第一半导体封装件间隔开的第二下基板、以及安装在所述第二下基板的区域内的第二半导体芯片；以及
至少一个无源元件，其布置在所述第一半导体封装件和所述第二半导体封装件中的至少一个内，并且电连接到所述第二半导体芯片。
2.根据权利要求1所述的半导体组件，其中所述第一下基板、所述第一上基板或者所述第二下基板中的至少一个包括具有多层结构的印刷电路板，所述多层结构中的每一层包括至少一个导电图案。
3.根据权利要求2所述的半导体组件，还包括：
主板，
其中所述第一下基板堆叠在所述主板上并且与所述主板间隔开。
4.根据权利要求3所述的半导体组件，还包括以下元件中的至少一个：
至少一个电连接所述第一下基板与所述主板的第一导电凸块；
至少一个电连接所述第一下基板与所述第一上基板的第二导电凸块；或者
至少一个电连接所述第一上基板与所述第二下基板的第三导电凸块。
5.根据权利要求4所述的半导体组件，其中所述至少一个无源元件安装在所述第二下基板的下侧或者所述第二下基板的上侧中的至少一者上。
6.根据权利要求5所述的半导体组件，其中所述至少一个无源元件电连接到以如下部分为路线的导电路径：所述主板、所述第一导电凸块、所述第一下基板的导电图案和焊盘、所述第二导电凸块、所述第一上基板的导电图案和焊盘、所述第三导电凸块、以及所述第二下基板的导电图案和焊盘。
7.根据权利要求6所述的半导体组件，其中所述至少一个无源元件电连接到以如下部分为路线的导电路径：至少一条电连接所述第二下基板与所述第二半导体芯片的导电线、以及所述第二下基板的导电图案和焊盘。
8.根据权利要求6所述的半导体组件，其中所述至少一个无源元件与所述第三导电凸块相邻地安装。
9.根据权利要求5所述的半导体组件，其中所述第二半导体封装件还包括：至少一个形成在所述第二下基板的下侧并且具有特定深度的插入凹部，并且
其中所述至少一个无源元件的至少一部分插入并安装在所述插入凹部中。
10.根据权利要求6所述的半导体组件，其中所述第二半导体封装件还包括：至少一条电连接所述第二下基板与所述第二半导体芯片的导电线，
其中所述至少一个无源元件在所述第二下基板上直接连接到所述至少一条导电线。
11.根据权利要求4所述的半导体组件，其中所述至少一个无源元件安装在所述第一上基板的上侧。
12.根据权利要求11所述的半导体组件，其中所述至少一个无源元件电连接到以如下部分为路线的导电路径：所述主板、所述第一导电凸块、所述第一下基板的导电图案和焊盘、所述第二导电凸块、以及所述第一上基板的导电图案和焊盘。
13.根据权利要求12所述的半导体组件，其中所述至少一个无源元件电连接到以如下部分为路线的导电路径：所述第一上基板的导电图案和焊盘、所述第三导电凸块、所述第二下基板的导电图案和焊盘、以及至少一条电连接所述第二下基板与所述第二半导体芯片的导电线。
14.一种电子设备，包括：
具有层叠封装(POP)结构的半导体组件，该半导体组件包括：第一半导体封装件，其包括第一下基板、面对所述第一下基板的第一上基板、以及安装在所述第一下基板的区域上的第一半导体芯片；第二半导体封装件，其包括堆叠在所述第一半导体封装件上并且与所述第一半导体封装件间隔开的第二下基板、以及安装在所述第二下基板的区域内的第二半导体芯片；以及至少一个无源元件，其布置在所述第一半导体封装件和所述第二半导体封装件中的至少一个内，并且电连接到所述第二半导体芯片,以及
电源单元，其配置成与所述第一半导体芯片的控制相对应地向所述半导体组件供电。
15.根据权利要求14所述的电子设备，其中所述至少一个无源元件布置在以下位置中的至少一处：所述第一上基板的上侧、所述第一上基板的内部、所述第二下基板的下侧、所述第二下基板的上侧、或者所述第二下基板的内部。
CN201710428788.XA 2016-06-08 2017-06-08 具有层叠封装结构的半导体组件及包括该组件的电子设备 Pending CN107482002A (zh)

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US11037890B2 (en) 2021-06-15
US20170358544A1 (en) 2017-12-14

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