CN107154428A - 互补纳米线半导体器件及其制备方法 - Google Patents

互补纳米线半导体器件及其制备方法 Download PDF

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CN107154428A
CN107154428A CN201610120564.8A CN201610120564A CN107154428A CN 107154428 A CN107154428 A CN 107154428A CN 201610120564 A CN201610120564 A CN 201610120564A CN 107154428 A CN107154428 A CN 107154428A
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gengon
extension cord
active regions
semiconductor devices
nanowire semiconductor
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CN201610120564.8A
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CN107154428B (zh
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肖德元
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Zing Semiconductor Corp
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Zing Semiconductor Corp
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Priority to CN201610120564.8A priority Critical patent/CN107154428B/zh
Priority to TW105118646A priority patent/TWI673780B/zh
Priority to US15/268,164 priority patent/US9779999B2/en
Priority to US15/587,484 priority patent/US9972543B2/en
Publication of CN107154428A publication Critical patent/CN107154428A/zh
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Abstract

本发明提供一种互补纳米线半导体器件及其制备方法，包括：提供一衬底，衬底上形成有NMOS有源区域、PMOS有源区域及浅沟槽隔离区域；在NMOS有源区域和PMOS有源区域上选择性外延生长锗晶体材料，以形成第一多边体外延线；选择性蚀刻衬底，使该第一多边体外延线悬空于衬底上方；在NMOS有源区域上方的第一多边体外延线的周围区域选择性外延生长III-V族半导体晶体材料，以形成第二多边体外延线；沉积介电材料于第一多边体外延线及第二多边体外延线，介电材料覆盖第一多边体外延线及第二多边体外延线；及沉积导电材料于介电材料，以形成包围第一多边体外延线及第二多边体外延线的栅极电极，其中第一多边体外延线作为第一纳米线，第二多边体外延线作为第二纳米线。

Description

互补纳米线半导体器件及其制备方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种互补纳米线半导体器件及其制备方法。
背景技术
随着可携式电子产品不断的推陈出新，其工艺技术也不断的在进步，而产品尺寸的微小化为目前最受关注的技术，如金氧半场效应晶体管(MOSFET)不断的被微小化，然而晶体管的微小化衍生出许多物理上的限制以及问题，例如热载流子注入、漏电流、绝缘、短沟道效应(Short-Channel Effects，SCEs)及沟道长度控制等，使得晶体管之栅极对于沟道内的控制能力逐渐降低。
因此，为了解决晶体管因微小化所产生的问题，多重栅极(Multi-Gate)晶体管被提出以改善栅极对于沟道的控制能力。常见的多重栅极晶体管为在硅衬底上制造三栅极(tri-gate)晶体管或环绕式栅极(gate-all-around)晶体管，然而，该类三维结构器件沟道的迁移率仍须改善。
现有技术中，例如美国公开专利US20100164101，硅锗外延线包围在鳍部的顶端，因此所形成的硅锗外延线为具有硅核的外延线。虽然通过后续的氧化热退火处理能够使锗向中心聚集以形成锗纳米线，但是由于内核的硅含量较高，也就是纳米线的锗含量较低，从而影响所形成的半导体器件的性能。
发明内容
本发明的目的在于，提供一种互补纳米线半导体器件及其制备方法。
为解决上述技术问题，本发明一种互补纳米线半导体器件及其制备方法，包括：提供一衬底，该衬底上形成有NMOS有源区域、PMOS有源区域及浅沟槽隔离(STI)区域；在该NMOS有源区域和该PMOS有源区域上选择性外延生长锗晶体材料，以形成第一多边体外延线；选择性蚀刻该衬底，使该第一多边体外延线悬空于该衬底上方；在该NMOS有源区域上方的该第一多边体外延线的周围区域选择性外延生长III-V族半导体晶体材料，以形成第二多边体外延线；在该第一多边体外延线及该第二多边体外延线上沉积介电材料，该介电材料覆盖该第一多边体外延线及该第二多边体外延线；及在该介电材料上沉积导电材料，以形成包围该第一多边体外延线及该第二多边体外延线的栅极电极，其中该第一多边体外延线作为第一纳米线，该第二多边体外延线作为第二纳米线。
根据一实施例，该第一多边体外延线的形状为棱形。
根据一实施例，形成该第一多边体外延线的步骤包括：该第一多边体外延线的长度介于2纳米至50纳米之间。
根据一实施例，形成该第一多边体外延线的步骤包括：该第一多边体外延线的直径介于2纳米至5纳米之间。
根据一实施例，在该NMOS有源区域和该PMOS有源区域上选择性外延生长该锗晶体材料的步骤包括：采用化学气相沉积、分子束外延或原子层沉积的方式生长该锗晶体材料。
根据一实施例，形成该第一多边体外延线的步骤包括：该第一多边体外延线为锗纳米线。
根据一实施例，按质量(或重量)百分比计算，该锗纳米线中锗含量介于65％至100％之间。
根据一实施例，在该NMOS有源区域上方的该第一多边体外延线的周围区域选择性外延生长III-V族半导体晶体材料的步骤包括：该III-V族半导体晶体材料为砷化铟镓(InGaAs)。
相应的，本发明还提供一种互补纳米线半导体器件，该互补纳米线半导体器件包括：衬底，该衬底包括NMOS有源区域、PMOS有源区域及浅沟槽隔离(STI)区域；锗晶体材料，形成于该NMOS有源区域和该PMOS有源区域上，作为第一多边体外延线；III-V族半导体晶体材料，该III-V族半导体晶体材料包覆该NMOS有源区域上的该第一多边体外延线，作为第二多边体外延线；介电材料，该介电材料覆盖该第一多边体外延线与该第二多边体外延线；及导电材料，该导电材料覆盖该介电材料，以形成包围该第一多边体外延线及该第二多边体外延线的栅极电极，其中该第一多边体外延线作为第一纳米线，该第二多边体外延线作为第二纳米线。
根据一实施例，该第一多边体外延线的形状为棱形。
根据一实施例，该第一多边体外延线的长度介于2纳米至50纳米之间。
根据一实施例，该第一多边体外延线的直径介于2纳米至5纳米之间。
根据一实施例，该第一多边体外延线为锗纳米线。
根据一实施例，按质量百分比计算，该锗纳米线中锗含量介于65％至100％之间。
根据一实施例，该III-V族半导体晶体材料为砷化铟镓(InGaAs)。
本发明提供的互补纳米线半导体器件及其制备方法，于PMOS有源区域具有环绕式栅极环绕锗纳米线，于NMOS有源区域具有环绕式栅极环绕III-V族纳米线，且锗纳米线中锗含量较高，可以实现具有极佳静电控制的高迁移率沟道。
附图说明
图1为本发明一实施例中制备互补纳米线半导体器件的方法流程图；
图2为本发明一实施例中衬底的剖面结构示意图；
图3为本发明一实施例中于NMOS有源区域与PMOS有源区域上生长第一多边体外延线的剖面结构示意图；
图4至5为本发明一实施例中选择性蚀刻衬底的剖面结构示意图；
图6至7为本发明一实施例中在NMOS有源区域上生长第二多边体外延线的剖面结构示意图。
图8为本发明一实施例中沉积介电材料于第一、二多边体外延线的剖面结构示意图。
图9为本发明一实施例中沉积导电材料于介电材料上的剖面结构示意图。
具体实施方式
下面将结合示意图对本发明的互补纳米线半导体器件及其制备方法进行更详细的描述，其中表示了本发明的较佳实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
本发明的核心思想在于，提供一种互补纳米线半导体器件及其制备方法，于PMOS有源区域具有环绕式栅极环绕锗纳米线，于NMOS有源区域具有环绕式栅极环绕III-V族纳米线，且锗纳米线中锗含量较高，可以实现具有极佳静电控制的高迁移率沟道。
下文结合附图对本发明的互补纳米线半导体器件及其制备方法，图1为互补纳米线半导体器件的制备流程图，图2～图9为各步骤中的结构示意图，其制备过程包括如下步骤：
执行步骤S1，参考图2所示，提供一衬底100，衬底100上形成有PMOS有源区域110、NMOS有源区域120及浅沟槽隔离(STI)区域130。根据一实施例，衬底100为单晶硅衬底，PMOS有源区域110与NMOS有源区域120呈鳍状，浅沟槽隔离(STI)区域130将PMOS有源区域110与NMOS有源区域120隔离。
执行步骤S2，参考图3所示，在PMOS有源区域110和NMOS有源区域120上选择性外延生长锗晶体材料，以形成第一多边体外延线310。根据一实施例，采用化学气相沉积(CVD)、金属有机物化学气相沉积(MOCVD)、分子束外延(MBE)或原子层沉积(ALD)等方式生长该锗晶体材料。根据一实施例，第一多边体外延线310位于PMOS有源区域110和NMOS有源区域120的鳍状顶端，作为第一纳米线。第一多边体外延线310的形状可为棱形，例如六角形等。根据一实施例，第一多边体外延线310的长度介于2纳米至50纳米之间。
执行步骤S3，参考图4至5所示，选择性蚀刻衬底100，使第一多边体外延线310悬空于衬底100上方。根据一实施例，透过第一蚀刻程序选择性蚀刻STI区域130至一预定深度D(如图4所示)，再透过第二道蚀刻程序选择性蚀刻PMOS有源区域110和NMOS有源区域120的鳍状顶端，使第一多边体外延线310悬空于衬底100上方。根据一实施例第二蚀刻程序为湿式蚀刻，采用的溶液包括氢氧化四甲铵(tetramethylazanium hydroxide，TMAH)溶液。根据一实施例，第一多边体外延线310呈现一悬臂结构。
执行步骤S4，参考图6至7所示，在NMOS有源区域120上方的第一多边体外延线310的周围区域选择性外延生长III-V族半导体晶体材料200，以形成第二多边体外延线320，第二多边体外延线作为第二纳米线。根据一实施例，III-V族半导体晶体材料200为砷化铟(InAs)或砷化铟镓(InGaAs)。根据一实施例，采用CVD、MOCVD、MBE或ALD等方式生长III-V族半导体晶体材料200。根据一实施例，执行步骤S4还包括可先在PMOS有源区域110上方处形成硬屏蔽(Hard Mask，HM)将PMOS有源区域110遮挡住(如图6所示)，避免III-V族半导体晶体材料200形成于PMOS有源区域110上的第一多边体外延线310。在第二多边体外延线320形成之后，利用蚀刻去除PMOS有源区域110处的硬屏蔽(如图7所示)。
执行步骤S5，参考图8所示，在第一多边体外延线310及第二多边体外延线320上沉积介电材料500，介电材料500覆盖第一多边体外延线310及第二多边体外延线320。根据一实施例，介电材料500为高介电常数(High-K)的介电材料，例如TiO2、HfO2、ZrO2等等。根据一实施例，采用ALD、CVD或MOCVD等方式沉积介电材料500。
执行步骤S6，参考图9所示，在介电材料500上沉积导电材料600，以形成包围第一多边体外延线310及第二多边体外延线320的栅极电极。根据一实施例，采用ALD、MOCVD或MBE等方式沉积导电材料600。根据一实施例，采用光刻与蚀刻技术以图案化定义栅极电极。
再次参考图9，藉由上述方法步骤，本发明提供一种互补纳米线半导体器件10，包括衬底100，衬底100包括PMOS有源区域110、NMOS有源区域120及浅沟槽隔离(STI)区域130；锗晶体材料，形成于PMOS有源区域110和PMOS有源区域120上，作为第一多边体外延线310；III-V族半导体晶体材料200，包覆NMOS有源区域上的第一多边体外延线310，作为第二多边体外延线320；介电材料500，覆盖第一多边体外延线310与第二多边体外延线320；及导电材料600，覆盖介电材料500，以形成包围第一多边体外延线310及第二多边体外延线320的栅极电极，其中第一多边体外延线310作为第一纳米线，第二多边体外延线320作为第二纳米线。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明申请专利范围及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (16)

1.一种互补纳米线半导体器件的制备方法，其特征在于，包括：
提供一衬底，该衬底上形成有NMOS有源区域、PMOS有源区域及浅沟槽隔离区域；
在该NMOS有源区域和该PMOS有源区域上选择性外延生长锗晶体材料，以形成第一多边体外延线；
选择性蚀刻该衬底，使该第一多边体外延线悬空于该衬底上方；
在该NMOS有源区域上方的该第一多边体外延线的周围区域选择性外延生长III-V族半导体晶体材料，以形成第二多边体外延线；
在该第一多边体外延线及该第二多边体外延线上沉积介电材料，该介电材料覆盖该第一多边体外延线及该第二多边体外延线；及
在该介电材料上沉积导电材料，以形成包围该第一多边体外延线及该第二多边体外延线的栅极电极，其中该第一多边体外延线作为第一纳米线，该第二多边体外延线作为第二纳米线。
2.如权利要求1所述的互补纳米线半导体器件的制备方法，其特征在于，该第一多边体外延线的形状为棱形。
3.如权利要求1所述的互补纳米线半导体器件的制备方法，其特征在于，形成该第一多边体外延线的步骤包括：该第一多边体外延线的长度介于2纳米至50纳米之间。
4.如权利要求1所述的互补纳米线半导体器件的制备方法，其特征在于，形成该第一多边体外延线的步骤包括：该第一多边体外延线的直径介于2纳米至5纳米之间。
5.如权利要求1所述的互补纳米线半导体器件的制备方法，其特征在于，在该NMOS有源区域和该PMOS有源区域上选择性外延生长该锗晶体材料的步骤包括：采用化学气相沉积、分子束外延或原子层沉积的方式生长该锗晶体材料。
6.如权利要求1所述的互补纳米线半导体器件的制备方法，其特征在于，形成该第一多边体外延线的步骤包括：该第一多边体外延线为锗纳米线。
7.如权利要求6所述的互补纳米线半导体器件的制备方法，其特征在于，按质量或重量百分比计算，该锗纳米线中锗含量介于65％至100％之间。
8.如权利要求1所述的互补纳米线半导体器件的制备方法，其特征在于，在该NMOS有源区域上方的该第一多边体外延线的周围区域选择性外延生长III-V族半导体晶体材料的步骤包括：该III-V族半导体晶体材料为砷化铟镓。
9.一种互补纳米线半导体器件，其特征在于，该互补纳米线半导体器件采用如权利要求1～8项中任一项所述的制备方法制备而成，该互补纳米线半导体器件包括：
衬底，该衬底包括NMOS有源区域、PMOS有源区域及浅沟槽隔离区域；
锗晶体材料，形成于该NMOS有源区域和该PMOS有源区域上，作为第一多边体外延线；
III-V族半导体晶体材料，该III-V族半导体晶体材料包覆该NMOS有源区域上的该第一多边体外延线，作为第二多边体外延线；
介电材料，该介电材料覆盖该第一多边体外延线与该第二多边体外延线；及
导电材料，该导电材料覆盖该介电材料，以形成包围该第一多边体外延线及该第二多边体外延线的栅极电极，其中该第一多边体外延线作为第一纳米线，该第二多边体外延线作为第二纳米线。
10.如权利要求9所述的互补纳米线半导体器件，其特征在于，该第一多边体外延线的形状为棱形。
11.如权利要求9所述的互补纳米线半导体器件，其特征在于，该第一多边体外延线的长度介于2纳米至50纳米之间。
12.如权利要求9所述的互补纳米线半导体器件，其特征在于，该第一多边体外延线的长度介于2纳米至50纳米之间。
13.如权利要求9所述的互补纳米线半导体器件，其特征在于，该第一多边体外延线的直径介于2纳米至5纳米之间。
14.如权利要求9所述的互补纳米线半导体器件，其特征在于，该第一多边体外延线为锗纳米线。
15.如权利要求14所述的互补纳米线半导体器件，其特征在于，按质量百分比计算，该锗纳米线中锗含量介于65％至100％之间。
16.如权利要求9所述的互补纳米线半导体器件，其特征在于，该III-V族半导体晶体材料为砷化铟镓。
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