CN102184923B - 硅纳米线晶体管器件可编程阵列的制备方法 - Google Patents

硅纳米线晶体管器件可编程阵列的制备方法 Download PDF

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CN102184923B
CN102184923B CN201110089699A CN201110089699A CN102184923B CN 102184923 B CN102184923 B CN 102184923B CN 201110089699 A CN201110089699 A CN 201110089699A CN 201110089699 A CN201110089699 A CN 201110089699A CN 102184923 B CN102184923 B CN 102184923B
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CN102184923A (zh
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黄如
邹积彬
王润声
樊捷闻
刘长泽
王阳元
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Peking University
Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明提供一种基于硅纳米线场效应晶体管的六边形可编程阵列及其制备方法，该阵列包括纳米线器件、纳米线器件连接区和栅连接区，所述纳米线器件呈圆柱形结构，包括硅纳米线沟道、栅介质层和栅区，栅介质层包裹硅纳米线沟道，栅区包裹栅介质层，纳米线器件以六边形排列构成一单元，纳米线器件连接区为3个纳米线器件之间的连接节点，纳米线器件连接区固定在一个硅支架上。本发明可实现复杂互联控制逻辑，适合应用于高速高集成度的数字/模拟电路，和数模混合电路。

Description

硅纳米线晶体管器件可编程阵列的制备方法
技术领域
本发明属于CMOS超大规模集成电路(ULSI)制造技术领域，特别涉及一种硅纳米线场效应晶体管(Silicon Nanowire Metal-Oxide-Silicon Field Effect Transistor，SNW MOSFET)六边形可编程阵列(Hexagonal Programmable Array)及其制备方法。
背景技术
半导体器件是制造电子产品的重要元件。半导体器件的更新换代推进了半导体技术的发展和半导体工业的进步，特别是对中央处理器CPU和存储器的性能提升。从上世纪末开始，芯片制造工艺发展十分迅速，先后从微米级别，一直发展到今天小于32nm的技术。
随着器件特征尺寸进入45纳米或更小，传统平面管器件的栅控能力逐渐减小，器件特性衰退，饱受短沟道效应的影响。在传统器件设计中栅氧厚度至多为几纳米甚至小于一纳米，如此薄的栅氧厚度会带来严重的栅泄漏电流，从而恶化器件的性能，可靠性以及大幅度增加器件的功耗；同时，如果通过工艺技术减小结深，不仅会给工艺实现方面带来巨大的挑战，另一方面，由于在器件制备的整个过程中，将不可避免的经历许多热过程，为制造浅结带来很多的困难。
为了解决上述一系列问题，器件设计者提出了多栅器件结构例如双栅，三栅和围栅器件来提高器件的栅控能力。在众多器件结构中，围栅结构具有最强的栅控能力，因为整个沟道被栅包围，当沟道长度缩小到纳米尺度时，围栅结构中的纳米线结构成为最有潜力的器件结构，因为这种围栅结构有利于器件迁移率和可靠性的提高，因此纳米线器件成为在场效应晶体管特征尺寸缩小到纳米尺度条件下的最为理想的器件结构。
同时，摩尔定律指出：集成电路上可容纳的晶体管数目，每隔18个月增加一倍，集成电路的性能也将提升一倍。随着半导体器件的特征尺寸不断减小，制约摩尔定律的主要因素从器件工作区的大小进而转向诸如源漏面积、引线等其他方面。在传统纳米线制造工艺中，源区(source)漏区(drain)会占有相当大的面积，它们等效为器件栅控有效沟道工作区(channel)的两倍大小。这无疑成为制约集成电路集成度进一步提高的一个非常重要因素。因此如何节约此部分面积，优化硅纳米线器件版图设计，已经成为当前高密度集成电路设计的重要课题。
发明内容
本发明的目的是弥补现有技术的空白，针对传统工艺，提供一种基于纳米线晶体管制造的优化方案，形成六边形可编程阵列，大幅度提高纳米线器件集成度，方便编程使用，实现超大规模，超高集成度的数字/模拟和数模混合电路。
本发明的技术方案如下：
一种基于硅纳米线场效应晶体管的六边形可编程阵列(如图1所示)，包括纳米线器件、纳米线器件连接区和栅连接区，纳米线器件以六边形排列构成一编程单元，相邻编程单元之间共用一个公共的纳米线器件，每个编程单元的中间部分为镂空区，所述纳米线器件(见图2)为硅纳米线场效应晶体管六边形可编程阵列的核心部分，呈圆柱形结构。纳米线器件包括硅纳米线沟道、栅介质层、栅区。栅介质层包裹硅纳米线沟道，栅区包裹栅介质层。硅纳米线沟道、栅介质层、栅区的长度取值一致，范围是5纳米～1微米。
所述硅纳米线沟道半径取值范围是3纳米～100纳米。硅纳米线沟道的掺杂浓度小于1015cm-3，不掺杂或等效为不掺杂。
所述栅介质层厚度取值范围是0.5纳米～10纳米。
所述栅区厚度取值范围是10纳米～500纳米。
纳米线器件与纳米线器件连接区相连接，每个硅纳米线连接区连接3个纳米线器件，为高密度、多纳米线器件互联提供了基础。由于纳米线器件连接区位于纳米线器件两侧。纳米线器件连接区可同时作为此纳米线器件的源或漏，具体源漏的定义使用者自己定义。同时纳米线器件连接区下面存在一个硅支架，支撑整个纳米线器件网络。纳米线器件连接区尺寸依纳米线沟道尺寸/工艺条件取值，其尺寸比例如图1，2所示。对于CMOS工艺，同时具有N型和P型纳米线器件的电路结构来讲，纳米线器件连接区掺杂浓度小于1015cm-3，不掺杂或等效为不掺杂。对于单独的NMOS工艺或PMOS工艺，全部器件为同种类型，可对纳米线器件连接区进行高浓度掺杂，掺杂浓度为1018～1020cm-3。
栅连接区为纳米线器件的栅区提供连接，使多根纳米线器件可以形成共栅结构。
本发明硅纳米线场效应晶体管六边形可编程阵列是基于原有纳米线制作技术。在CMOS工艺下，具体包括以下步骤：
(1)选取初始浓度很低的硅片(掺杂浓度小于1015cm-3)，利用硬掩模定义硅片镂空区；
(2)去掉(1)中硬掩模，进行氧化减薄纳米线硅条，形成悬浮的硅纳米线网络；交错的掩模版形成的纳米线器件连接区较纳米线沟道粗，在氧化减薄这个工艺步骤中，纳米线可以实现悬空，而纳米线器件连接区并没有悬空，它下面存在硅支架同支撑整个网络。
(3)湿法腐蚀掉形成的二氧化硅，进行热氧化形成一层致密二氧化硅栅介质；
(4)利用另两片硬掩模分别对N型栅和P型栅连接进行定义；这里用户自定义，可编程控制；
(5)淀积材料，制作栅连接区；
(6)利用另一块掩模版定义一些隔断图形，用作隔断一些不需要连接的部分；利用刻蚀技术使这些连接部分断开；可编程控制；(此步骤可选，如无需隔断则略去此步骤)
(7)最后进入常规CMOS后道工序。
在NMOS或PMOS工艺下，需作出以下修改：
步骤(4)中用一块栅掩模版即可。
步骤(5)中制作栅连接区后，要额外增加一块掩模版，对六边形可编程阵列区域进行高浓度掺杂，掺杂浓度为1018～1020cm-3。之后快速热退火(RTA)，将杂志驱入纳米线器件连接区和其他作为互联线用的纳米线沟道。
这里需注意，对于CMOS工艺和N/PMOS工艺来讲，前者中作为互联的纳米线沟道需要制作栅控制，达到等效于“传输门”的目的，而后者中的互联作用沟道不需要栅控制，仅注入高浓度杂志即可。因此CMOS工艺和N/PMOS工艺的(4)步骤可能有不同。
与现有技术相比，本发明的作用是：
硅纳米线场效应晶体管六边形可编程阵列适合应用于高速高集成度的数字/模拟电路，和数模混合电路。由于其略去了传统纳米线器件的大块源漏接触，十分节省面积。与传统平面管可编程门阵列FPGA比较，在达到抑制短沟效应的同时，也节省了相当大的面积，可以达到超高集成度。同时，六边形纳米线互联网络结构每个互联节点(纳米线器件连接区)连接三个器件沟道，每个单元最远的两个节点间存在3个器件，因此可实现复杂控制互联控制逻辑，这是传统形式的阵列所不能提供的。
附图说明
图1是本发明中介绍的硅纳米线场效应晶体管六边形可编程阵列的俯视面示意图。图中：
1-纳米线器件的抽象棍棒式示意图，2-硅片镂空区，3-纳米线器件连接区，4-栅连接区(图中为两种栅，可为两种材料构成，实现NMOS和PMOS)，5-硅片，6-隔断。
图2是左侧为单个纳米线器件示意图，图中：因为较多，以下我的改动不加修订标记了。
7-纳米线器件连接区，8-硅片镂空区，9-纳米线器件的栅区。
图2是右侧为单个纳米线器件剖面示意图，图中：
10-硅纳米线沟道，11-栅介质层，12-栅区。
图3为第一次硬掩模，掩模版为圆形或方形。(图中以圆形为例，如为方形，利用曝光的临界效应，也可以将图形曝圆)。图3中：
13-圆形掩模版，14-硅片。
图4为曝光后刻蚀出圆形图形，并且氧化减薄纳米线硅条，使之悬空，同时使之剖面形成如图2右侧图中的圆形。图4中：
15-硅片镂空区，16-纳米线沟道，17-硅片。
图5为在高温热氧化形成栅介质层后，淀积形成栅连接区。覆盖在纳米线沟道上的部分为栅区。在这之后可以定义隔断，隔断某些不想要的连接。
18-栅连接区，19-隔断。以下改动用修订。图6为利用两个基本六边形单元制作4管CMOS与非门的示意图：
20-N型纳米线器件，21-P型纳米线器件，22-常开管用做互联，23-被隔断的纳米线，24-N型纳米线器件的栅，25-P型纳米线器件的栅，26-常开管的栅(等效为传输们)，27-输入信号A，28-输入信号B，29-常开管输入(VDD或GND，视常开管类型而定)。
图7为CMOS与非门电路图，对应图6中各种器件和信号：
30-N型纳米线器件，31-P型纳米线器件，32-输入信号A，33-输入信号B，34-节点0GND，35-节点1，36-节点2输出，37-节点3VDD。
具体实施方式
下面结合附图和具体实施方式对本发明作进一步详细描述：
图1为本发明中介绍的硅纳米线场效应晶体管六边形可编程阵列的俯视面示意图。其结构与一般的常规纳米线场效应晶体管区别在于：
首先纳米线器件结构有所变化，传统的纳米线器件大体包括：纳米线沟道，栅区，源区和漏区。为了打通孔制作互联引线，传统纳米线器件的源区和漏区占用非常大的面积，本专利所介绍的六边形阵列中的纳米线器件，完全抛弃传统源漏，用面积很小且可作为互联节点的纳米线器件连接区替代，这样极大地减小了纳米线器件沟道与沟道之间冗余面积。对于相同功能的电路结构，其核心面积节省至少8/9。另外，交错的圆形掩模版也为形成这种纳米线网络提供了可能：交错的掩模版形成的纳米线器件连接区较纳米线沟道粗，在氧化减薄这个工艺步骤中，纳米线沟道可以实现悬空，而可控制工艺条件：适当氧化温度，如950度、时间，如10秒等，使纳米线器件连接区并没有悬空，它下面存在硅支架支撑整个网络。
其次，硅纳米线场效应晶体管六边形可编程阵列的工艺简单，只需定义一次硅片镂空区，就可以实现众多纳米线。等效为一个光刻图形实现三根纳米线器件，高效地利用光刻技术。这在使用电子束光刻(E-Beam Lithography)时尤为明显。
同时，六边形纳米线互联网络结构每个互联节点(纳米线器件连接区)连接三个器件沟道，每个单元最远的两个节点间存在3个器件，因此可实现复杂控制互联控制逻辑，这是传统形式的阵列所不能提供的。上述各种区别有利于提高纳米线场效应晶体管的性能和工作效率。所以，硅纳米线场效应晶体管六边形可编程阵列适合应用于高速高集成度的数字/模拟电路，和数模混合电路。
下面以CMOS工艺下的硅纳米线场效应晶体管六边形可编程阵列制作与非门为例说明主要制作流程：
(1)选取掺杂浓度小于1015cm-3的硅片，利用交错式硬掩模定义硅片镂空区。如图3所示。此步骤中，交错式图形面积要小于预计的硅片镂空区面积，可以为圆形或方形或六边形，利用曝光时的临近效应达到曝光出稍大圆形的目的。典型的交错式图形基本单元面积范围是：10纳米×10纳米～2.5微米×2.5微米。
(2)去掉(1)中硬掩模，进行氧化减薄纳米线硅条，形成悬浮的硅纳米线网络；交错的掩模版形成的纳米线器件连接区较纳米线沟道粗，在氧化减薄这个工艺步骤中，纳米线可以实现悬空，而纳米线器件连接区并没有悬空，它下面存在硅支架同支撑整个网。
(3)湿法腐蚀掉形成的二氧化硅，进行热氧化形成一层致密二氧化硅栅介质。如图7所示。(此时硅上都有一层二氧化硅，未在图中标出)。
(4)利用另两片硬掩模分别对N型栅和P型栅连接进行定义，定义栅的同时，也定义了栅所覆盖器件的类型。然后淀积生成纳米线器件栅连接区。此步骤中N型栅和P型栅需采用不同材料，如想要形成NMOS，则N型栅采用磷P/砷As注入，如想要形成PMOS，P型栅采用硼B注入。
(5)利用另一块掩模版定义一些隔断图形，隔断一些不需要连接的部分；利用刻蚀技术使这些连接部分断开。
后面的工艺流程和常规硅纳米线MOS晶体管完全一样。先后进行：平坦化，淀积隔离层，光刻外围输入输出引线孔，淀积金属，光刻引线，钝化等等。
图6所示包括两个六边形编程单元的实施例，该编程阵列实际用到9根纳米线器件，其中2根N型纳米线器件，两根P型纳米线器件，其余5根纳米线器件用作互连。参考图7，29-N型纳米线器件和30-P型纳米线器件分别由33-N型纳米线器件的栅和34-P型纳米线器件的栅所控制，利用不同材料栅与硅的功函数差控制阈值电压，达到形成不同类型纳米线器件的目的。
以上通过详细实例描述了本发明所提供的硅纳米线场效应晶体管六边形可编程阵列，上面描述的应用场景和实施例，并非用于限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，可以做各种的更动和润饰，因此本发明的保护范围视权利要求范围界定。

Claims (3)

1.一种硅纳米线晶体管器件可编程阵列的制备方法，该硅纳米线晶体管器件可编程阵列包括纳米线器件、纳米线器件连接区和栅连接区，所述纳米线器件呈圆柱形结构，包括硅纳米线沟道、栅介质层和栅区，栅介质层包裹硅纳米线沟道，栅区包裹栅介质层，其中，硅纳米线沟道、栅介质层和栅区的长度取值一致，范围是5纳米～1微米，纳米线器件以六边形排列构成一编程单元，相邻编程单元之间共用一个公共的纳米线器件，每个编程单元的中间部分为镂空区，纳米线器件连接区为3个纳米线器件之间的连接节点，该纳米线器件连接区与纳米线器件的沟道连接，同时作为纳米线器件的源或漏，纳米线器件连接区固定在一个硅支架上，栅连接区为纳米线器件的栅区提供连接，使多根纳米线器件形成共栅结构，制备工艺具体包括以下步骤：
1)选取掺杂浓度小于1015cm-3的硅片，利用交错式硬掩模定义硅片镂空区；
2)去掉1)中硬掩模，进行氧化减薄纳米线硅条，形成悬浮的硅纳米线网络；交错式硬掩模形成的纳米线器件连接区较纳米线器件沟道区粗，在氧化减薄这个工艺步骤中，纳米线实现悬空，而纳米线器件连接区并没有悬空，它下面存在硅支架支撑整个网络；
3)湿法腐蚀掉形成的二氧化硅，进行热氧化形成一层致密二氧化硅栅介质；
4)利用另两片硬掩模分别对N型栅和P型栅连接进行定义；
5)淀积材料，制作栅连接区；
6)最后进入常规CM0S后道工序。
2.如权利要求1所述的方法，其特征在于，利用另一块掩模版定义隔断图形，利用刻蚀技术断开不需要连接的纳米线器件。
3.如权利要求1所述的方法，其特征在于，步骤5)中制作栅连接区后，额外增加一块掩模版，对六边形可编程阵列区域进行高浓度掺杂，掺杂浓度为1018～1020cm-3，之后快速热退火，将杂质驱入纳米线器件连接区和其他作为互联线用的区域。
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