TWI684215B - 用於磊晶半導體成長之雙曲度空腔 - Google Patents

用於磊晶半導體成長之雙曲度空腔 Download PDF

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TWI684215B
TWI684215B TW107117053A TW107117053A TWI684215B TW I684215 B TWI684215 B TW I684215B TW 107117053 A TW107117053 A TW 107117053A TW 107117053 A TW107117053 A TW 107117053A TW I684215 B TWI684215 B TW I684215B
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阿利納 夫拉瓦
羅先慶
石勇軍
彭建偉
江虎 晏
屹 亓
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明提出數種形成場效電晶體之方法及用於場效電晶體之結構。形成在半導體鰭片中與通道區重疊的閘極結構。用第一蝕刻製程蝕刻該半導體鰭片以形成伸入該半導體鰭片而鄰接該通道區的第一空腔。用第二蝕刻製程蝕刻該半導體鰭片以形成容積小於該第一空腔且毗鄰該第一空腔的第二空腔。

Description

用於磊晶半導體成長之雙曲度空腔
本發明係有關於半導體裝置製造和數種積體電路，且更特別的是，有關於用於場效電晶體之結構及形成場效電晶體之方法。
用於場效電晶體的裝置結構通常包括本體區，界定在本體區中的源極及汲極，與經組配成可施加控制電壓的閘極結構，控制電壓係用以開關形成於本體區中之通道裡的載子流。當施加大於指定臨界電壓的控制電壓時，載子流便出現於源極與汲極之間的通道中以產生裝置輸出電流。
磊晶半導體膜可用來修改場效電晶體的效能。例如，磊晶半導體膜藉由在通道中誘發應力可用來增加載子移動率(carrier mobility)。在p-通道場效電晶體中，藉由施加壓縮應力至通道可增強電洞移動率。壓縮應力的施加可藉由在通道的相對兩側形成磊晶半導體材料，例如矽鍺。同樣，在n-通道場效電晶體中，藉由施加拉伸應力至通道可增強電子移動率。拉伸應力的施加可藉由在通道 的相對兩側形成磊晶半導體材料，例如摻碳矽。這些應力源(stressor)也可作為場效電晶體的源極區及汲極區之一部分運作，且可充當源極區及汲極區之其他部分的摻雜物供應者。
應力源中含有的磊晶半導體材料容積可與裝置效能及良率直接有關聯。賦予通道的應力隨著容積增加而增加，這可優化移動率。容積增加也可減少源極及汲極電阻，且在某些情況也可提供一致的接觸著陸區(contact landing area)。
因此，亟須用於場效電晶體的改良結構與形成場效電晶體的方法。
在本發明之一具體實施例中，提供一種用於形成場效電晶體之方法。形成在半導體鰭片中與通道區重疊的閘極結構。用第一蝕刻製程蝕刻該半導體鰭片以形成伸入該半導體鰭片而鄰接該通道區的第一空腔。用第二蝕刻製程蝕刻該半導體鰭片以形成容積小於該第一空腔且毗鄰該第一空腔的第二空腔。
在本發明之一具體實施例中，提供一種用於形成場效電晶體之結構。該結構包括半導體鰭片，其具有通道區、第一空腔、與容積小於該第一空腔且毗鄰該第一空腔的第二空腔。該結構進一步包括與該通道區重疊而鄰接該第一空腔的閘極結構，與源極/汲極區，其具有在該第一空腔中的第一區段與在該第二空腔中的第二區段。
10‧‧‧半導體鰭片、鰭片
11‧‧‧通道區
12‧‧‧頂面
13‧‧‧溝槽隔離物
14‧‧‧閘極結構
15‧‧‧閘極電極
17‧‧‧閘極介電質
18、19‧‧‧側壁間隔件
20‧‧‧帽蓋
21‧‧‧空腔
22‧‧‧空腔
24‧‧‧側壁
25‧‧‧平面
26‧‧‧空腔、附加空腔
28‧‧‧側壁
30‧‧‧嵌入式源極/汲極區
32‧‧‧區段
34‧‧‧區段
36‧‧‧多閘極鰭片型場效電晶體、FinFET
38‧‧‧淺溝槽隔離區
w0‧‧‧寬度尺寸
併入本專利說明書且構成其一部分的附圖圖示本發明的各種具體實施例，其與以上的【發明內容】及以下的【實施方式】一起用來解釋本發明的具體實施例。
第1圖的橫截面圖根據本發明的具體實施例圖示場效電晶體在加工方法之初始製造階段的結構。
第1A圖圖示第1圖結構從與半導體鰭片長度平行的觀點繪出位在閘極結構之間的橫截面圖。
第2圖的橫截面圖圖示在加工方法之後續製造階段的第1圖結構。
第2A圖圖示第2圖結構從與半導體鰭片長度平行的觀點繪出位在閘極結構之間的橫截面圖。
第3圖的橫截面圖圖示在加工方法之後續製造階段的第2圖結構。
第3A圖圖示第3圖結構從與半導體鰭片長度平行的觀點繪出位在閘極結構之間的橫截面圖。
第4圖的橫截面圖圖示在加工方法之後續製造階段的第3圖結構。
第4A圖圖示第4圖結構從與半導體鰭片長度平行的觀點繪出位在閘極結構之間的橫截面圖。
第5圖的橫截面圖根據本發明的替代具體實施例圖示實作成與單一擴散斷點(single diffusion break)有關聯的結構。
參考第1圖、第1A圖且根據本發明的具體實施例，數個閘極結構14配置在半導體鰭片10的頂面12上且在半導體鰭片10中於隔開位置處的各自的通道區11重疊。閘極結構14也可位在鄰接半導體鰭片10的溝槽隔離物13上。半導體鰭片10由單晶半導體材料構成，且在一具體實施例中，半導體鰭片10可由單晶矽構成。使用側壁成像轉移(SIT)製程、自對準雙重圖案化(SADP)、或自對準四重圖案化(SAQP)，藉由圖案化基板或成長於基板上的磊晶層，可形成半導體鰭片10。
各閘極結構14包括閘極電極15與插在閘極電極15與半導體鰭片10之間的閘極介電質17。閘極電極15可由複晶矽(亦即，多晶矽)構成，或可包括一或多個阻障金屬層，功函數金屬層，及/或由導體構成的填充金屬層，例如金屬(例如，鎢(W))及/或金屬氮化物或碳化物(例如，氮化鈦(TiN)及鈦碳化鋁(titanium aluminum carbide，TiAlC))。閘極介電質17可由介電質材料構成，例如二氧化矽(SiO2)或高k介電質材料，例如氧化鉿(HfO2)。閘極結構14可為功能閘極結構，或替代地，可為隨後在取代金屬閘極製程被移除且用功能閘極結構取代的犧牲閘極結構。如本文所用的用語“犧牲閘極結構”係指用於隨後將會形成之功能閘極結構的佔位結構。如本文所用的用語“功能閘極結構”係指用來控制場效電晶體之輸出電流(亦即，載子在通道中的流動)的永久閘極結構。
在與各閘極結構14之垂直側壁鄰接的位置 處，安置側壁間隔件18於半導體鰭片10的頂面12上。側壁間隔件18可由介電質材料構成，例如氮化矽(Si3N4)，其係用原子層沉積(ALD)沉積成為共形層且用定向蝕刻製程蝕刻，例如反應性離子蝕刻(RIE)。用來形成側壁間隔件18的共形層可為保護層，它在加工互補類型的場效電晶體時施塗於半導體鰭片10及閘極結構14上面。
也安置側壁間隔件19於半導體鰭片10的側壁上。側壁間隔件19可由介電質材料構成，例如氮化矽(Si3N4)，其係用ALD沉積成為共形層且用定向蝕刻製程蝕刻，例如反應性離子蝕刻(RIE)。在一具體實施例中，側壁間隔件18及側壁間隔件19可同時形成。
閘極結構14及側壁間隔件18覆蓋在半導體鰭片10之頂面及側面上的各個區域。閘極結構14也可配置成與包圍半導體鰭片10的淺溝槽隔離物(未圖示)重疊。在半導體鰭片10之頂面12及側面上的閘極結構14與其側壁間隔件18之間的區域被暴露。
帽蓋20配置在各閘極結構14之閘極電極15的頂面上並且橫向配置在側壁間隔件18之間的空間中。帽蓋20可由介電質材料構成，例如氮化矽(Si3N4)，其係用化學氣相沉積(CVD)沉積。
參考第2圖及第2A圖，其中與第1圖、第1A圖中類似的特徵用相同的元件符號表示，且在加工方法的後續製造階段，移除在暴露區上面之半導體鰭片10配置在閘極結構14之間的區段以形成朝垂直方向穿入半導 體鰭片10到給定深度的空腔22。可移除半導體鰭片10在側壁間隔件18之間的附加區段以形成空腔21，如第2A圖以虛線示意圖示者。使用等向性蝕刻製程，以適當的蝕刻化學物，可形成空腔21、22。形成空腔21、22的蝕刻製程可同時且從半導體鰭片10部分移除側壁間隔件19，如第2A圖所示。
空腔22具有側壁24，側壁24有賦予空腔22圓球形狀的給定曲度。空腔22在半導體鰭片10之頂面12的入口可具有寬度尺寸w0，其等於側壁間隔件18之間的距離。由於在非等向性蝕刻製程期間的底切，側壁24在側壁間隔件18下面向外彎曲到稍微大於寬度尺寸w0的寬度尺寸。空腔22因此底切側壁間隔件18。
參考第3圖、第3A圖，其中與第2圖、第2A圖中類似的特徵用相同的元件符號表示，且在加工方法的後續製造階段，形成疊加於空腔22上的空腔26。使用反應性離子蝕刻(RIE)製程，以適當的蝕刻化學物，可形成空腔26，例如使用四氟化碳(CH4)作為來源氣體以產生反應性離子的RIE製程。該蝕刻製程為定向的乾式非等向性蝕刻，且藉由在閘極結構14上的側壁間隔件18而自對準。結果，空腔26的寬度尺寸與側壁間隔件18之間的距離相關，而且通常比該距離小一點。
空腔26的容積小於空腔22，且空腔26界定有效地加深空腔22之中央區段的尖端。由於蝕刻的非等向性和自對準，空腔22之側壁24在側壁間隔件18下 面的部分會維持原始曲度且在形成空腔26時不被修改。 此外，在非等向性蝕刻製程期間的自對準與等向性蝕刻製程的等向性會導致空腔26對於平面25呈對稱，且相對於空腔22而位於中央。
空腔26有曲度與空腔22之側壁24之曲度不同的側壁28。特別是，側壁28的曲度小於側壁24的曲度。空腔26形塑成其橫截面為不完整圓形，具有與其曲度半徑相關的給定弧長。
形成空腔26的蝕刻製程可同時從半導體鰭片10移除側壁間隔件19的剩餘部份，如第3A圖所示。空腔22、26的複合形狀，特別是，加上空腔26，可促進側壁間隔件19的完全移除。
參考第4圖、第4A圖，其中與第3圖、第3A圖中類似的特徵用相同的元件符號表示，且在加工方法的後續製造階段，在空腔22、26中形成嵌入式源極/汲極區30且可完成多閘極鰭片型場效電晶體(FinFET)36的形成。嵌入式源極/汲極區30由成長於空腔22、26中的磊晶半導體材料構成且採用空腔22、26在鰭片10內部的形狀。特別是，嵌入式源極/汲極區30包括位在半導體鰭片10之空腔22中的區段32與位在半導體鰭片10之空腔26中的區段34。嵌入式源極/汲極區30的區段32配置在嵌入式源極/汲極區30的區段34與半導體鰭片10的頂面12之間。在鰭片10的空腔22、26之外，嵌入式源極/汲極區30的磊晶半導體材料採用在其外表面的切面形狀(faceted shape)，如第 4A圖所示。
磊晶成長製程可用來沉積磊晶半導體材料，例如矽鍺(SiGe)或摻碳矽(Si：C)，以形成嵌入式源極/汲極區30，且在成長期間可包括原位摻雜以賦予成長半導體材料的給定導電類型(conductivity type)。在一具體實施例中，可用選擇性磊晶成長製程來形成嵌入式源極/汲極區30，其中半導體材料使在半導體表面上的磊晶成長成核(nucleate)，但是不使絕緣體表面的磊晶成長成核。如本文所使用的，用語“源極/汲極區”意指可用作場效電晶體之源極或者是汲極的半導體材料摻雜區。對於p型場效電晶體，嵌入式源極/汲極區30的半導體材料可摻雜選自週期表第III族(例如，硼(B))可提供p型導電性的p型摻雜物。對於n型場效電晶體，嵌入式源極/汲極區30的半導體材料可摻雜選自週期表第V族(例如，磷(P)與砷(As))可提供n型導電性的n型摻雜物。
嵌入式源極/汲極區30可帶有應變且通過控制特徵化磊晶成長製程之條件及參數而含有內應力。嵌入式源極/汲極區30可作為嵌入式應力源，其使應力轉移到半導體鰭片10的通道區11致使通道區11受應變影響，這可增加在裝置運作期間的載子移動率。如果嵌入式源極/汲極區30由Si：C構成，通道區11中可產生適合用於n型場效電晶體的拉伸應變。如果嵌入式源極/汲極區30由SiGe構成，通道區11中可產生適合用於p型場效電晶體的壓縮應變。
參考第5圖，其中與第4圖中類似的特徵用相同的元件符號表示，且根據替代具體實施例，可實作與單一擴散斷點(SBD)有關聯之附加空腔26的引進，其中只有單一虛擬閘極位在主動區之間，相比之下，第1圖至第4圖為以雙重擴散斷點(DDB)實作的具體實施例。為此，可形成鄰接鰭片10的淺溝槽隔離區38。形成空腔22、26的蝕刻製程對淺溝槽隔離區38的介電質材料選擇性地蝕刻半導體鰭片10的半導體材料。如本文所使用的，涉及材料移除製程(例如，蝕刻)的用語“選擇性”表明，在適當的蝕刻劑選擇下，標的材料的材料移除率(亦即，蝕刻速率)大於暴露於材料移除製程之至少另一材料的移除率。用來形成嵌入式源極/汲極區30的磊晶半導體材料不會從淺溝槽隔離區38的介電質材料成核，進而修改嵌入式源極/汲極區30的形狀。
用兩個不同蝕刻製程來形成空腔22、26可讓空腔26的形成與空腔22的形成分開進行。用非等向性蝕刻製程引進空腔26可增加磊晶半導體材料包含在嵌入式源極/汲極區30中的容積。藉由有效植入物的充分表面積與著陸於SDB區的一致接觸，嵌入式源極/汲極區30由於添加區段34而增加的容積可與FinFET 36的裝置效能有關。嵌入式源極/汲極區30由於添加區段34而增加的容積可增加轉移到FinFET 36之通道的應力，這可進一步增加載子移動率，且可減少嵌入式源極/汲極區30的電阻，兩者都可增進裝置效能。
形成空腔22、26於鰭片10內部的蝕刻製程同時拆除側壁間隔件19。側壁間隔件19由附加空腔26促進的完全移除係藉由增加由鰭片10提供之成長種子的表面積來優化半導體材料在嵌入式源極/汲極區30中的容積。只增加空腔22的容積也會增加空腔深度，但是會使磊晶半導體材料的切面(faceting)劣化，特別是在SDB區中的，而導致洩露增加且由於難以接觸嵌入式源極/汲極區30而使良率減降低。在不改變空腔22的輪廓或形狀下達成空腔26的添加，這確保磊晶半導體材料的切面不劣化同時也增加磊晶半導體材料的容積。嵌入式源極/汲極區30與淺溝槽隔離區38之間的截取高度(height of the intercept)也增加藉此提高切面平面(facet plane)。
如以上所述的方法使用於積體電路晶片的製造。所產生之積體電路晶片可由製造者以原始晶圓形式(raw wafer form)(例如，具有多個未封裝晶片的單一晶圓)、作為裸晶粒(bare die)或已封裝的形式來銷售。在後一情形下，晶片裝在單晶片封裝中(例如，塑膠載體(plastic carrier)，具有固定至主機板或其他更高層載體的引腳(lead))，或多晶片封裝體中(例如，具有表面互連件(surface interconnection)或埋藏互連件(buried interconnection)任一或兩者兼具的陶瓷載體)。在任一情形下，該晶片可與其他晶片、離散電路元件及/或其他信號處理裝置集成為中間產品或者是最終產品。
本文所引用的用語，例如“垂直”、“水平”等， 係通過舉例而非用於限制的方式，來建立參考框架。如本文所用的用語“水平”界定為與半導體基板之習知平面平行的平面，而與實際三維空間取向無關。用語“垂直”及“法線”係指與剛剛所界定之水平垂直的方向。用語“橫向”係指在水平平面內的方向。用語“上方”及“下方”用來表示元件或結構相互之間的相對位置而不是相對高度。
“連接”或“耦合”至另一元件的特徵可直接連接或耦合至該另一元件，或是，可存在一或多個中介元件。如果不存在中介元件，特徵可“直接連接”或“直接耦合”至另一元件。如果存在至少一中介元件，特徵可“間接連接”或“間接耦合”至另一元件。
為了圖解說明已呈現本發明之各種具體實施例的描述，但是並非旨在窮盡或限定於所揭示的具體實施例。本技藝一般技術人員明白仍有許多修改及變體而不脫離所述具體實施例的範疇及精神。使用於本文的術語經選定成可最好地解釋具體實施例的原理、實際應用或優於在市上可找到之技術的技術改善，或使得本技藝一般技術人員能夠了解揭示於本文的具體實施例。
10‧‧‧半導體鰭片、鰭片
11‧‧‧通道區
12‧‧‧頂面
14‧‧‧閘極結構
15‧‧‧閘極電極
17‧‧‧閘極介電質
18‧‧‧側壁間隔件
20‧‧‧帽蓋
22‧‧‧溝槽或空腔
24‧‧‧側壁
25‧‧‧平面
26‧‧‧溝槽或空腔、附加空腔
28‧‧‧側壁

Claims (21)

  1. 一種用於形成場效電晶體之方法，該方法包含：形成閘極結構，該閘極結構係與在半導體鰭片中的通道區重疊；形成側壁間隔件在鄰接該通道區的該半導體鰭片上；用第一蝕刻製程蝕刻該半導體鰭片以形成伸入該半導體鰭片而鄰接該閘極結構的第一空腔；用該第一蝕刻製程從該半導體鰭片移除該側壁間隔件的第一部分以保留未被移除的第二部分；用第二蝕刻製程蝕刻該半導體鰭片以形成容積小於該第一空腔且毗鄰該第一空腔的第二空腔；以及用該第二蝕刻製程從該半導體鰭片移除該側壁間隔件的該第二部分。
  2. 如申請專利範圍第1項所述之方法，其中，該第一空腔在形成該第二空腔之前形成。
  3. 如申請專利範圍第1項所述之方法，其中，該半導體鰭片由矽構成，且該第二蝕刻製程為非等向性蝕刻製程。
  4. 如申請專利範圍第3項所述之方法，其中，該第一蝕刻製程為等向性蝕刻製程。
  5. 如申請專利範圍第1項所述之方法，其中，該第一空腔從該半導體鰭片的頂面延伸到一第一深度，且該第一空腔配置在該半導體鰭片的該第二空腔與該頂面之間。
  6. 如申請專利範圍第5項所述之方法，其中，該第二空腔相對於該第一空腔而位於中央。
  7. 如申請專利範圍第1項所述之方法，進一步包含：磊晶成長嵌入式源極/汲極區，該嵌入式源極/汲極區具有在該第一空腔中的第一區段與在該第二空腔中的第二區段。
  8. 如申請專利範圍第7項所述之方法，其中，該半導體鰭片由矽構成，且該嵌入式源極/汲極區包括轉移到該半導體鰭片之該通道區的內應力。
  9. 如申請專利範圍第8項所述之方法，其中，該嵌入式源極/汲極區由矽鍺構成，該場效電晶體為p型場效電晶體，且該嵌入式源極/汲極區將壓縮應變轉移到該通道區。
  10. 如申請專利範圍第8項所述之方法，其中，該嵌入式源極/汲極區由摻碳矽構成，該場效電晶體為n型場效電晶體，且該嵌入式源極/汲極區將拉伸應變轉移到該通道區。
  11. 如申請專利範圍第1項所述之方法，其中，該閘極結構包括閘極電極，且進一步包含：形成與該閘極電極鄰接的側壁間隔件，其中，該第一空腔底切該閘極電極上的該側壁間隔件。
  12. 如申請專利範圍第11項所述之方法，其中，該第二蝕刻製程藉由該側壁間隔件自對準，且該第二蝕刻製程 為非等向性。
  13. 一種用於場效電晶體之結構，該結構包含：半導體鰭片，包括通道區、第一空腔與容積小於該第一空腔且毗鄰該第一空腔的第二空腔，該第一空腔具有第一弧形側壁，該第二空腔具有曲度半徑小於該第一空腔之該第一弧形側壁的第二弧形側壁，且該第二空腔之該第二弧形側壁與該第一空腔之該第一弧形側壁相交；閘極結構，與該半導體鰭片內的該通道區重疊；以及源極/汲極區，包括在該第一空腔中的第一區段與在該第二空腔中的第二區段。
  14. 如申請專利範圍第13項所述之結構，其中，該半導體鰭片沒有側壁間隔件。
  15. 如申請專利範圍第13項所述之結構，其中，該第一空腔從該半導體鰭片的頂面延伸到一第一深度，且該第一空腔配置在該半導體鰭片的該第二空腔與該頂面之間。
  16. 如申請專利範圍第13項所述之結構，其中，該第二空腔相對於該第一空腔而位於中央。
  17. 如申請專利範圍第13項所述之結構，其中，該閘極結構包括閘極電極，且進一步包含：側壁間隔件，經配置成與該閘極電極鄰接，其中，該第一空腔底切該側壁間隔件。
  18. 如申請專利範圍第13項所述之結構，進一步包含：淺溝槽隔離區，其中，該源極/汲極區安置於該第一空腔的該第一弧形側壁與該淺溝槽隔離區之間，且該源極/汲極區安置於該第二空腔的該第二弧形側壁與該淺溝槽隔離區之間。
  19. 如申請專利範圍第18項所述之結構，其中，該第一空腔安置於該第二空腔的上方，且該第一空腔包含與該第一弧形側壁形狀不同的第三弧形側壁。
  20. 如申請專利範圍第18項所述之結構，其中，該源極/汲極區具有非對稱形狀。
  21. 如申請專利範圍第20項所述之結構，其中，該第一空腔安置於該第二空腔的上方，且該源極/汲極區具有鄰接該第一空腔的該第一弧形側壁的第一形狀及鄰接該第一空腔的該第三弧形側壁的第二形狀，且該第一形狀不同於該第二形狀。
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