CN109727871A - 用于外延半导体成长的双曲度空腔 - Google Patents

用于外延半导体成长的双曲度空腔 Download PDF

Info

Publication number
CN109727871A
CN109727871A CN201811254286.0A CN201811254286A CN109727871A CN 109727871 A CN109727871 A CN 109727871A CN 201811254286 A CN201811254286 A CN 201811254286A CN 109727871 A CN109727871 A CN 109727871A
Authority
CN
China
Prior art keywords
cavity
semiconductor fin
drain regions
etch process
curved wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201811254286.0A
Other languages
English (en)
Inventor
阿利纳·夫拉瓦
罗先庆
石勇军
彭建伟
晏江虎
亓屹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN109727871A publication Critical patent/CN109727871A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

本发明涉及用于外延半导体成长的双曲度空腔，提出数种形成场效应晶体管的方法及用于场效应晶体管的结构。形成在半导体鳍片中与沟道区重叠的栅极结构。用第一蚀刻制程蚀刻该半导体鳍片以形成伸入该半导体鳍片而邻接该沟道区的第一空腔。用第二蚀刻制程蚀刻该半导体鳍片以形成容积小于该第一空腔且毗邻该第一空腔的第二空腔。

Description

用于外延半导体成长的双曲度空腔
技术领域
本发明是有关于半导体装置制造和数种集成电路，且更特别的是，有关于用于场效应晶体管的结构及形成场效应晶体管的方法。
背景技术
用于场效应晶体管的装置结构通常包括本体区，界定在本体区中的源极及漏极，与经组配成可施加控制电压的栅极结构，控制电压是用以开关形成于本体区中的沟道里的载子流。当施加大于指定临界电压的控制电压时，载子流便出现于源极与漏极之间的沟道中以产生装置输出电流。
外延半导体膜可用来修改场效应晶体管的效能。例如，外延半导体膜通过在沟道中诱发应力可用来增加载子移动率(carrier mobility)。在p-沟道场效应晶体管中，通过施加压缩应力至沟道可增强空穴移动率。压缩应力的施加可通过在沟道的相对两侧形成外延半导体材料，例如硅锗。同样，在n-沟道场效应晶体管中，通过施加拉伸应力至沟道可增强电子移动率。拉伸应力的施加可通过在沟道的相对两侧形成外延半导体材料，例如掺碳硅。这些应力源(stressor)也可作为场效应晶体管的源极区及漏极区的一部分运作，且可充当源极区及漏极区的其他部分的掺杂物供应者。
应力源中含有的外延半导体材料容积可与装置效能及良率直接有关联。赋予沟道的应力随着容积增加而增加，这可优化移动率。容积增加也可减少源极及漏极电阻，且在某些情况也可提供一致的接触着陆区(contact landing area)。
因此，亟须用于场效应晶体管的改良结构与形成场效应晶体管的方法。
发明内容
在本发明的一具体实施例中，提供一种用于形成场效应晶体管的方法。形成在半导体鳍片中与沟道区重叠的栅极结构。用第一蚀刻制程蚀刻该半导体鳍片以形成伸入该半导体鳍片而邻接该沟道区的第一空腔。用第二蚀刻制程蚀刻该半导体鳍片以形成容积小于该第一空腔且毗邻该第一空腔的第二空腔。
在本发明的一具体实施例中，提供一种用于形成场效应晶体管的结构。该结构包括半导体鳍片，其具有沟道区、第一空腔、与容积小于该第一空腔且毗邻该第一空腔的第二空腔。该结构进一步包括与该沟道区重叠而邻接该第一空腔的栅极结构，与源极/漏极区，其具有在该第一空腔中的第一区段与在该第二空腔中的第二区段。
附图说明
并入本专利说明书且构成其一部分的附图图示本发明的各种具体实施例，其与以上的“发明内容”及以下的“具体实施方式”一起用来解释本发明的具体实施例。
图1A的横截面图根据本发明的具体实施例图示场效应晶体管在加工方法的初始制造阶段的结构。
图1B图标图1A结构从与半导体鳍片长度平行的观点绘出位在栅极结构之间的横截面图。
图2A的横截面图图示在加工方法的后续制造阶段的图1A结构。
图2B图标图2A结构从与半导体鳍片长度平行的观点绘出位在栅极结构之间的横截面图。
图3A的横截面图图示在加工方法的后续制造阶段的图2A结构。
图3B图标图3A结构从与半导体鳍片长度平行的观点绘出位在栅极结构之间的横截面图。
图4A的横截面图图示在加工方法的后续制造阶段的图3A结构。
图4B图标图4A结构从与半导体鳍片长度平行的观点绘出位在栅极结构之间的横截面图。
图5的横截面图根据本发明的替代具体实施例图示实作成与单一扩散断点(single diffusion break)有关联的结构。
具体实施方式
参考图1A、图1B且根据本发明的具体实施例，数个栅极结构14 配置在半导体鳍片10的顶面12上且在半导体鳍片10中于隔开位置处的各自的沟道区11重叠。栅极结构14也可位在邻接半导体鳍片10的沟槽隔离物13上。半导体鳍片10由单晶半导体材料构成，且在一具体实施例中，半导体鳍片10可由单晶硅构成。使用侧壁成像转移(SIT) 制程、自对准双重图案化(SADP)、或自对准四重图案化(SAQP)，通过图案化衬底或成长于衬底上的外延层，可形成半导体鳍片10。
各栅极结构14包括栅极电极15与插在栅极电极15与半导体鳍片 10之间的栅极介电质17。栅极电极15可由复晶硅(亦即，多晶硅)构成，或可包括一或多个阻障金属层，功函数金属层，及/或由导体构成的填充金属层，例如金属(例如，钨(W))及/或金属氮化物或碳化物(例如，氮化钛(TiN)及钛碳化铝(titanium aluminum carbide，TiAlC))。栅极介电质17可由介电质材料构成，例如二氧化硅(SiO2)或高k介电质材料，例如氧化铪(HfO2)。栅极结构14可为功能栅极结构，或替代地，可为随后在取代金属栅极制程被移除且用功能栅极结构取代的牺牲栅极结构。如本文所用的用语“牺牲栅极结构”是指用于随后将会形成的功能栅极结构的占位结构。如本文所用的用语“功能栅极结构”是指用来控制场效应晶体管的输出电流(亦即，载子在沟道中的流动)的永久栅极结构。
在与各栅极结构14的垂直侧壁邻接的位置处，安置侧壁间隔件18 于半导体鳍片10的顶面12上。侧壁间隔件18可由介电质材料构成，例如氮化硅(Si3N4)，其用原子层沉积(ALD)沉积成为共形层且用定向蚀刻制程蚀刻，例如反应性离子蚀刻(RIE)。用来形成侧壁间隔件18的共形层可为保护层，它在加工互补类型的场效应晶体管时施涂于半导体鳍片10与门极结构14上面。
也安置侧壁间隔件19于半导体鳍片10的侧壁上。侧壁间隔件19 可由介电质材料构成，例如氮化硅(Si3N4)，其用ALD沉积成为共形层且用定向蚀刻制程蚀刻，例如反应性离子蚀刻(RIE)。在一具体实施例中，侧壁间隔件18及侧壁间隔件19可同时形成。
栅极结构14及侧壁间隔件18覆盖在半导体鳍片10的顶面及侧面上的各个区域。栅极结构14也可配置成与包围半导体鳍片10的浅沟槽隔离物(未图示)重叠。在半导体鳍片10的顶面12及侧面上的栅极结构14与其侧壁间隔件18之间的区域被暴露。
帽盖20配置在各栅极结构14的栅极电极15的顶面上并且横向配置在侧壁间隔件18之间的空间中。帽盖20可由介电质材料构成，例如氮化硅(Si3N4)，其用化学气相沉积(CVD)沉积。
参考图2A及图2B，其中与图1A、图1B中类似的特征用相同的附图标记表示，且在加工方法的后续制造阶段，移除在暴露区上面的半导体鳍片10配置在栅极结构14之间的区段以形成朝垂直方向穿入半导体鳍片10到给定深度的沟槽或空腔22。可移除半导体鳍片10在侧壁间隔件18之间的附加区段以形成鳍片空腔21，如图2B以虚线示意图示者。使用等向性(isotropic)蚀刻制程，以适当的蚀刻化学物，可形成空腔21、22。形成空腔21、22的蚀刻制程可同时且从半导体鳍片 10部分移除侧壁间隔件19，如图2B所示。
空腔22具有侧壁24，侧壁24有赋予空腔22圆球形状的给定曲度。空腔22在半导体鳍片10的顶面12的入口可具有宽度尺寸w0，其等于侧壁间隔件18之间的距离。由于在非等向性(anisotropic)蚀刻制程期间的底切，侧壁24在侧壁间隔件18下面向外弯曲到稍微大于宽度尺寸w0的宽度尺寸。空腔22因此底切侧壁间隔件18。
参考图3A、图3B，其中与图2A、图2B中类似的特征用相同的附图标记表示，且在加工方法的后续制造阶段，形成迭加于空腔22上的沟槽或空腔26。使用反应性离子蚀刻(RIE)制程，以适当的蚀刻化学物，可形成空腔26，例如使用四氟化碳(CH4)作为来源气体以产生反应性离子的RIE制程。该蚀刻制程为定向的干式非等向性蚀刻，且通过在栅极结构14上的侧壁间隔件18而自对准。结果，空腔26的宽度尺寸与侧壁间隔件18之间的距离相关，而且通常比该距离小一点。
空腔26的容积小于空腔22，且空腔26界定有效地加深空腔22 的中央区段的尖端。由于蚀刻的非等向性和自对准，空腔22的侧壁24 在侧壁间隔件18下面的部分会维持原始曲度且在形成空腔26时不被修改。此外，在非等向性蚀刻制程期间的自对准与等向性蚀刻制程的等向性会导致空腔26对于平面25呈对称，且相对于空腔22而位于中央。
空腔26有曲度与空腔22的侧壁24的曲度不同的侧壁28。特别是，侧壁28的曲度小于侧壁24的曲度。空腔26形塑成其横截面为不完整圆形，具有与其曲度半径相关的给定弧长。
形成空腔26的蚀刻制程可同时从半导体鳍片10移除侧壁间隔件 19的剩余部份，如图3B所示。空腔22、26的复合形状，特别是，加上空腔26，可促进侧壁间隔件19的完全移除。
参考图4A、图4B，其中与图3A、图3B中类似的特征用相同的附图标记表示，且在加工方法的后续制造阶段，在空腔22、26中形成嵌入式源极/漏极区30且可完成多栅极鳍片型场效应晶体管(FinFET)36 的形成。嵌入式源极/漏极区30由成长于空腔22、26中的外延半导体材料构成且采用空腔22、26在鳍片10内部的形状。特别是，嵌入式源极/漏极区30包括位在半导体鳍片10的空腔22中的区段32与位在半导体鳍片10的空腔26中的区段34。嵌入式源极/漏极区30的区段 32配置在嵌入式源极/漏极区30的区段34与半导体鳍片10的顶面12之间。在鳍片10的空腔22、26之外，源极/漏极区30的外延半导体材料采用在其外表面的切面形状(faceted shape)，如图4B所示。
外延成长制程可用来沉积外延半导体材料，例如硅锗(SiGe)或掺碳硅(Si：C)，以形成嵌入式源极/漏极区30，且在成长期间可包括原位掺杂以赋予成长半导体材料的给定导电类型(conductivity type)。在一具体实施例中，可用选择性外延成长制程来形成嵌入式源极/漏极区30，其中半导体材料使在半导体表面上的外延成长成核 (nucleate)，但是不使绝缘体表面的外延成长成核。如本文所使用的，用语“源极/漏极区”意指可用作场效应晶体管的源极或者是漏极的半导体材料掺杂区。对于p型场效应晶体管，嵌入式源极/漏极区30 的半导体材料可掺杂选自周期表第III族(例如，硼(B))可提供p型导电性的p型掺杂物。对于n型场效应晶体管，嵌入式源极/漏极区30 的半导体材料可掺杂选自周期表第V族(例如，磷(P)与砷(As))可提供 n型导电性的n型掺杂物。
嵌入式源极/漏极区30可带有应变且通过控制特征化外延成长制程的条件及参数而含有内应力。嵌入式源极/漏极区30可作为嵌入式应力源，其使应力转移到半导体鳍片10的沟道区11致使沟道区11受应变影响，这可增加在装置运作期间的载子移动率。如果嵌入式源极/ 漏极区30由Si：C构成，沟道区11中可产生适合用于n型场效应晶体管的拉伸应变。如果嵌入式源极/漏极区30由SiGe构成，沟道区11 中可产生适合用于p型场效应晶体管的压缩应变。
参考图5，其中与图4A中类似的特征用相同的附图标记表示，且根据替代具体实施例，可实作与单一扩散断点(SBD)有关联的附加空腔 26的引进，其中只有单一虚拟栅极位在主动区之间，相比之下，图1A 至图4A为以双重扩散断点(DDB)实作的具体实施例。为此，可形成邻接鳍片10的浅沟槽隔离区38。形成空腔22、26的蚀刻制程对浅沟槽隔离区38的介电质材料选择性地蚀刻半导体鳍片10的半导体材料。如本文所使用的，涉及材料移除制程(例如，蚀刻)的用语“选择性”表明，在适当的蚀刻剂选择下，目标材料的材料移除率(亦即，蚀刻速率)大于暴露于材料移除制程的至少另一材料的移除率。用来形成嵌入式源极/漏极区30的外延半导体材料不会从浅沟槽隔离区38的介电质材料成核，进而修改嵌入式源极/漏极区30的形状。
用两个不同蚀刻制程来形成空腔22、26可让空腔26的形成与空腔22的形成分开进行。用非等向性蚀刻制程引进空腔26可增加外延半导体材料包含在嵌入式源极/漏极区30中的容积。通过有效植入物的充分表面积与着陆于SDB区的一致接触，源极/漏极区30由于添加区段34而增加的容积可与FinFET 36的装置效能有关。源极/漏极区 30由于添加区段34而增加的容积可增加转移到FinFET 36的沟道的应力，这可进一步增加载子移动率，且可减少源极/漏极区30的电阻，两者都可增进装置效能。
形成空腔22、26于鳍片10内部的蚀刻制程同时拆除侧壁间隔件 19。侧壁间隔件19由附加空腔26促进的完全移除是通过增加由鳍片 10提供的成长种子的表面积来优化半导体材料在源极/漏极区30中的容积。只增加空腔22的容积也会增加空腔深度，但是会使外延半导体材料的切面(faceting)劣化，特别是在SDB区中的，而导致泄露增加且由于难以接触源极/漏极区30而使良率减降低。在不改变空腔22的轮廓或形状下达成空腔26的添加，这确保外延半导体材料的切面不劣化同时也增加外延半导体材料的容积。源极/漏极区30与浅沟槽隔离区38之间的截取高度(height of the intercept)也增加由此提高切面平面(facet plane)。
如以上所述的方法使用于集成电路芯片的制造。所产生的集成电路芯片可由制造者以原始晶圆形式(raw wafer form)(例如，具有多个未封装芯片的单一晶圆)、作为裸晶粒(bare die)或已封装的形式来销售。在后一情形下，芯片装在单芯片封装中(例如，塑料载体(plastic carrier)，具有固定至主板或其他更高层载体的引脚(lead))，或多芯片封装体中(例如，具有表面互连件(surface interconnection)或埋藏互连件(buriedinterconnection)任一或两者兼具的陶瓷载体)。在任一情形下，该芯片可与其他芯片、离散电路组件及/或其他信号处理装置集成为中间产品或者是最终产品。
本文所引用的用语，例如“垂直”、“水平”等，是通过举例而非用于限制的方式，来建立参考框架。如本文所用的用语“水平”界定为与半导体衬底的习知平面平行的平面，而与实际三维空间取向无关。用语“垂直”及“法线”是指与刚刚所界定的水平垂直的方向。用语“横向”是指在水平平面内的方向。用语“上方”及“下方”用来表示组件或结构相互之间的相对位置而不是相对高度。
“连接”或“耦合”至另一组件的特征可直接连接或耦合至该另一组件，或是，可存在一或多个中介组件。如果不存在中介组件，特征可“直接连接”或“直接耦合”至另一组件。如果存在至少一中介组件，特征可“间接连接”或“间接耦合”至另一组件。
为了图解说明已呈现本发明的各种具体实施例的描述，但是并非旨在穷尽或限定于所揭示的具体实施例。本领域技术人员明白仍有许多修改及变体而不脱离所述具体实施例的范畴及精神。使用于本文的术语经选定成可最好地解释具体实施例的原理、实际应用或优于在市上可找到的技术的技术改善，或使得本领域技术人员能够了解揭示于本文的具体实施例。

Claims (20)

1.一种用于形成场效应晶体管的方法，该方法包含：
形成栅极结构，该栅极结构与在半导体鳍片中的沟道区重叠；
用第一蚀刻制程蚀刻该半导体鳍片以形成伸入该半导体鳍片而邻接该栅极结构的第一空腔；以及
用第二蚀刻制程蚀刻该半导体鳍片以形成容积小于该第一空腔且毗邻该第一空腔的第二空腔。
2.如权利要求1所述的方法，其中，该第一空腔在形成该第二空腔之前形成。
3.如权利要求1所述的方法，其中，该半导体鳍片由硅构成，且该第二蚀刻制程为非等向性蚀刻制程。
4.如权利要求3所述的方法，其中，该第一蚀刻制程为等向性蚀刻制程。
5.如权利要求1所述的方法，其中，该半导体鳍片在该半导体鳍片用该第一蚀刻制程蚀刻之前包括侧壁间隔件，且该第一蚀刻制程与该第二蚀刻制程共同从该半导体鳍片移除该侧壁间隔件。
6.如权利要求1所述的方法，其中，该第一空腔从该半导体鳍片的顶面延伸到一第一深度，且该第一空腔配置在该半导体鳍片的该第二空腔与该顶面之间。
7.如权利要求6所述的方法，其中，该第二空腔相对于该第一空腔而位于中央。
8.如权利要求1所述的方法，进一步包含：
外延成长嵌入式源极/漏极区，该嵌入式源极/漏极区具有在该第一空腔中的第一区段与在该第二空腔中的第二区段。
9.如权利要求8所述的方法，其中，该半导体鳍片由硅构成，且该嵌入式源极/漏极区包括转移到该半导体鳍片的该沟道区的内应力。
10.如权利要求9所述的方法，其中，该嵌入式源极/漏极区由硅锗构成，该场效应晶体管为p型场效应晶体管，且该嵌入式源极/漏极区将压缩应变转移到该沟道区。
11.如权利要求9所述的方法，其中，该嵌入式源极/漏极区由掺碳硅构成，该场效应晶体管为n型场效应晶体管，且该嵌入式源极/漏极区将拉伸应变转移到该沟道区。
12.如权利要求1所述的方法，其中，该第一空腔具有弧形侧壁，该第二空腔具有曲度半径小于该第一空腔的该弧形侧壁的弧形侧壁，且该第二空腔的该弧形侧壁与该第一空腔的该弧形侧壁相交。
13.如权利要求1所述的方法，其中，该栅极结构包括栅极电极，且进一步包含：
形成与该栅极电极邻接的侧壁间隔件，
其中，该第一空腔底切该侧壁间隔件。
14.如权利要求13所述的方法，其中，该第二蚀刻制程通过该侧壁间隔件自对准，且该第二蚀刻制程为非等向性。
15.一种用于场效应晶体管的结构，该结构包含：
半导体鳍片，包括沟道区、第一空腔与容积小于该第一空腔且毗邻该第一空腔的第二空腔；
栅极结构，与该沟道区重叠而邻接该沟道区；以及
源极/漏极区，包括在该第一空腔中的第一区段与在该第二空腔中的第二区段。
16.如权利要求15所述的结构，其中，该半导体鳍片没有垂直邻接该源极/漏极区的侧壁间隔件。
17.如权利要求15所述的结构，其中，该第一空腔从该半导体鳍片的顶面延伸到一第一深度，且该第一空腔配置在该半导体鳍片的该第二空腔与该顶面之间。
18.如权利要求15所述的结构，其中，该第二空腔相对于该第一空腔而位于中央。
19.如权利要求15所述的结构，其中，该第一空腔具有弧形侧壁，该第二空腔具有曲度半径小于该第一空腔的该弧形侧壁的弧形侧壁，且该第二空腔的该弧形侧壁与该第一空腔的该弧形侧壁相交。
20.如权利要求15所述的结构，其中，该栅极结构包括栅极电极，且进一步包含：
侧壁间隔件，经配置成与该栅极电极邻接，
其中，该第一空腔底切该侧壁间隔件。
CN201811254286.0A 2017-10-27 2018-10-26 用于外延半导体成长的双曲度空腔 Withdrawn CN109727871A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/795,879 2017-10-27
US15/795,879 US10297675B1 (en) 2017-10-27 2017-10-27 Dual-curvature cavity for epitaxial semiconductor growth

Publications (1)

Publication Number Publication Date
CN109727871A true CN109727871A (zh) 2019-05-07

Family

ID=66243508

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811254286.0A Withdrawn CN109727871A (zh) 2017-10-27 2018-10-26 用于外延半导体成长的双曲度空腔

Country Status (3)

Country Link
US (2) US10297675B1 (zh)
CN (1) CN109727871A (zh)
TW (1) TWI684215B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410231A (zh) * 2020-03-16 2021-09-17 格芯(美国)集成电路科技有限公司 具有分段外延半导体层的晶体管
CN113972267A (zh) * 2020-07-24 2022-01-25 格芯(美国)集成电路科技有限公司 具有混合源极/漏极区的晶体管

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102020112695A1 (de) * 2019-05-31 2020-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Optimiertes näheprofil für verspanntes source/drain-merkmal und verfahren zu dessen herstellung
US11489062B2 (en) * 2019-05-31 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd Optimized proximity profile for strained source/drain feature and method of fabricating thereof
US11107696B1 (en) 2019-10-29 2021-08-31 Xilinx, Inc. Implantation for etch stop liner
KR20220090672A (ko) 2020-12-22 2022-06-30 삼성전자주식회사 반도체 소자

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102656672A (zh) * 2009-12-23 2012-09-05 英特尔公司 具有自对准外延源和漏的多栅半导体器件
US20150097242A1 (en) * 2013-03-08 2015-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Channel Epitaxial Regrowth Flow (CRF)
CN104576739A (zh) * 2013-10-22 2015-04-29 国际商业机器公司 半导体结构及其制造方法
CN106469653A (zh) * 2015-08-21 2017-03-01 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN106601735A (zh) * 2015-10-15 2017-04-26 台湾积体电路制造股份有限公司 鳍式场效应晶体管结构及其制造方法
CN107230728A (zh) * 2016-03-24 2017-10-03 台湾积体电路制造股份有限公司 半导体器件、finfet器件及其形成方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6881635B1 (en) 2004-03-23 2005-04-19 International Business Machines Corporation Strained silicon NMOS devices with embedded source/drain
US7335959B2 (en) * 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
EP1994567A2 (fr) 2006-02-14 2008-11-26 STMicroeletronics Crolles 2 SAS Transistor mos a seuil reglable
US8138053B2 (en) 2007-01-09 2012-03-20 International Business Machines Corporation Method of forming source and drain of field-effect-transistor and structure thereof
JP2010003916A (ja) 2008-06-20 2010-01-07 Elpida Memory Inc 半導体装置及びその製造方法
KR101668097B1 (ko) * 2010-03-12 2016-10-24 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성 방법
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US20120205716A1 (en) 2011-02-16 2012-08-16 International Business Machines Corporation Epitaxially Grown Extension Regions for Scaled CMOS Devices
US8946064B2 (en) 2011-06-16 2015-02-03 International Business Machines Corporation Transistor with buried silicon germanium for improved proximity control and optimized recess shape
CN103632973B (zh) 2012-08-23 2017-01-25 中国科学院微电子研究所 半导体器件及其制造方法
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US9640531B1 (en) 2014-01-28 2017-05-02 Monolithic 3D Inc. Semiconductor device, structure and methods
US9293534B2 (en) * 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US9093298B2 (en) * 2013-08-22 2015-07-28 Texas Instruments Incorporated Silicide formation due to improved SiGe faceting
US9246003B2 (en) 2013-11-19 2016-01-26 Globalfoundries Inc. FINFET structures with fins recessed beneath the gate
US9483481B2 (en) * 2013-12-06 2016-11-01 International Business Machines Corporation Files having unallocated portions within content addressable storage
US9287398B2 (en) * 2014-02-14 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor strain-inducing scheme
KR102170856B1 (ko) * 2014-02-19 2020-10-29 삼성전자주식회사 반도체 장치 및 그 제조 방법
TWI637514B (zh) * 2015-04-24 2018-10-01 聯華電子股份有限公司 半導體結構及其製作方法
US10276715B2 (en) 2016-02-25 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
CN107403835B (zh) * 2016-05-19 2021-12-14 联芯集成电路制造(厦门)有限公司 半导体装置及其制作工艺
US10056465B2 (en) 2016-06-20 2018-08-21 Semiconductor Manufacturing International (Shanghai) Corporation Transistor device and fabrication method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102656672A (zh) * 2009-12-23 2012-09-05 英特尔公司 具有自对准外延源和漏的多栅半导体器件
US20150097242A1 (en) * 2013-03-08 2015-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Channel Epitaxial Regrowth Flow (CRF)
CN104576739A (zh) * 2013-10-22 2015-04-29 国际商业机器公司 半导体结构及其制造方法
CN106469653A (zh) * 2015-08-21 2017-03-01 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN106601735A (zh) * 2015-10-15 2017-04-26 台湾积体电路制造股份有限公司 鳍式场效应晶体管结构及其制造方法
CN107230728A (zh) * 2016-03-24 2017-10-03 台湾积体电路制造股份有限公司 半导体器件、finfet器件及其形成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410231A (zh) * 2020-03-16 2021-09-17 格芯(美国)集成电路科技有限公司 具有分段外延半导体层的晶体管
CN113972267A (zh) * 2020-07-24 2022-01-25 格芯(美国)集成电路科技有限公司 具有混合源极/漏极区的晶体管

Also Published As

Publication number Publication date
TW201917785A (zh) 2019-05-01
US10297675B1 (en) 2019-05-21
US20190131433A1 (en) 2019-05-02
US20190181243A1 (en) 2019-06-13
TWI684215B (zh) 2020-02-01

Similar Documents

Publication Publication Date Title
TWI688096B (zh) 具有二極體隔離之堆疊奈米片場效電晶體
US9805942B2 (en) Method of modifying epitaxial growth shape on source drain area of transistor
US11081394B2 (en) Method of making a FinFET device
CN109727871A (zh) 用于外延半导体成长的双曲度空腔
CN103227202B (zh) FinFET体接触件及其制造方法
CN103325831B (zh) 用于FinFET的源极/漏极轮廓
KR102323733B1 (ko) 콘택 플러그를 갖는 반도체 소자 및 그 형성 방법
KR101435710B1 (ko) 고밀도 게이트 디바이스 및 방법
US11948999B2 (en) Semiconductor device
US9793401B1 (en) Vertical field effect transistor including extension and stressors
US9966456B1 (en) Methods of forming gate electrodes on a vertical transistor device
US10121870B1 (en) Semiconductor device structure with strain-relaxed buffer
US10361310B2 (en) Method of fabricating semiconductor devices
US20200152504A1 (en) Airgap spacers formed in conjunction with a late gate cut
KR20180135085A (ko) 트랜지스터의 소스/드레인 영역 상의 에피택셜 필름에 대한 선택적 식각 방법
US10699957B2 (en) Late gate cut using selective dielectric deposition
US9929153B2 (en) Method of making a FinFET device
US20150187654A1 (en) Method of Manufacturing a Semiconductor Device with Buried Channel/Body Zone and Semiconductor Device
CN108074968A (zh) 具有自对准栅极的穿隧finfet
US20190027370A1 (en) Shaped cavity for epitaxial semiconductor growth
US8957479B2 (en) Formation of multi-height MUGFET
CN105405890B (zh) 包括带电荷体侧墙的半导体器件及其制造方法
US11264499B2 (en) Transistor devices with source/drain regions comprising an interface layer that comprises a non-semiconductor material
US10727067B2 (en) Late gate cut using selective conductor deposition
US10269812B1 (en) Forming contacts for VFETs

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication

Application publication date: 20190507

WW01 Invention patent application withdrawn after publication