CN107146779A - The encapsulating structure and method for packing of fingerprint recognition chip - Google Patents
The encapsulating structure and method for packing of fingerprint recognition chip Download PDFInfo
- Publication number
- CN107146779A CN107146779A CN201710523587.8A CN201710523587A CN107146779A CN 107146779 A CN107146779 A CN 107146779A CN 201710523587 A CN201710523587 A CN 201710523587A CN 107146779 A CN107146779 A CN 107146779A
- Authority
- CN
- China
- Prior art keywords
- fingerprint recognition
- recognition chip
- wiring layer
- packing
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000012856 packing Methods 0.000 title claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 239000000463 material Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 42
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 106
- 238000005516 engineering process Methods 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000011241 protective layer Substances 0.000 claims description 19
- 239000003822 epoxy resin Substances 0.000 claims description 17
- 229920000647 polyepoxide Polymers 0.000 claims description 17
- 239000010931 gold Substances 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 14
- 229910052709 silver Inorganic materials 0.000 claims description 13
- 238000003466 welding Methods 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000000741 silica gel Substances 0.000 claims description 12
- 229910002027 silica gel Inorganic materials 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000010944 silver (metal) Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 238000007731 hot pressing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 241000416536 Euproctis pseudoconspersa Species 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 150000003949 imides Chemical class 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000001721 transfer moulding Methods 0.000 claims 1
- -1 which is selected Substances 0.000 claims 1
- 230000008901 benefit Effects 0.000 abstract description 8
- 238000005538 encapsulation Methods 0.000 description 22
- 229910052594 sapphire Inorganic materials 0.000 description 8
- 239000010980 sapphire Substances 0.000 description 8
- OINMNSFDYTYXEQ-UHFFFAOYSA-M 2-bromoethyl(trimethyl)azanium;bromide Chemical compound [Br-].C[N+](C)(C)CCBr OINMNSFDYTYXEQ-UHFFFAOYSA-M 0.000 description 3
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000011946 reduction process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 206010065954 Stubbornness Diseases 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010257 thawing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
- H01L23/4924—Bases or plates or solder therefor characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
- H01L2224/83491—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Human Computer Interaction (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of encapsulating structure and method for packing of fingerprint recognition chip, and the encapsulating structure includes：Silicon substrate；Re-wiring layer, is formed on the silicon substrate；Metal lead wire, is welded on the re-wiring layer by bonding wire craft；Fingerprint recognition chip, is installed on the re-wiring layer by metal solder joints, wherein, the front of the fingerprint recognition chip is toward the re-wiring layer；And encapsulating material, the fingerprint recognition chip is covered in, and the metal lead wire is exposed to the encapsulating material.The present invention uses fan-out package（Fan out）Fingerprint recognition chip, for existing other fingerprint recognition chip packages, has the advantages that cost is low, thickness is small, yield is high.Using bonding wire craft, technological temperature can be substantially reduced, the scope of application of technique is improved.
Description
Technical field
The present invention relates to a kind of semiconductor package and method for packing, more particularly to a kind of envelope of fingerprint recognition chip
Assembling structure and method for packing.
Background technology
As function increasingly stronger, performance and the integrated level more and more higher of integrated circuit, and new integrated circuit go out
Existing, encapsulation technology plays more and more important role in IC products, shared in the value of whole electronic system
Ratio it is increasing.Meanwhile, as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
Because fan-out wafer level encapsulation (fowlp) technology is due to having the advantages that miniaturization, low cost and high integration, with
And the energy efficiency with better performance and Geng Gao, the movement as high request of fan-out wafer level encapsulation (fowlp) technology/
The important method for packing of the electronic equipments such as wireless network, is one of encapsulation technology most with prospects at present.
Fingerprint identification technology is biometrics identification technology most ripe and cheap at present.For at present, fingerprint is known
Other technology is most widely used, not only it can be seen that the figure of fingerprint identification technology, in the market has in gate inhibition, attendance checking system
The applications of more fingerprint recognitions：As notebook computer, mobile phone, automobile, bank paying all can employing fingerprint identification technology.
A kind of method for packing of existing fingerprint recognition chip is as shown in Fig. 1 a~Fig. 1 c：
The first step, as shown in Figure 1a, deep trouth is made in fingerprint recognition chip 101, and is bonded on FPC plates 102, so
Metal connecting line 103 is made by routing technique afterwards, the electrical connection of fingerprint recognition chip 101 and FP C plates 102 is realized, wherein, FPC
It is Flexible Printed Circuit abbreviation, also known as FPC, it has, and Distribution density is high, lightweight, thickness
Thin the characteristics of.
Second step, as shown in Figure 1 b, produces framework 104；
3rd step, shown in scholar 1c, is capped sapphire cover plate 105 on the fingerprint recognition chip, to complete encapsulation.
This method has the disadvantages that：Including FPC plates, fingerprint recognition chip and sapphire cover plate three-decker, envelope
Fill thickness thicker, metal connecting line is easily broken caused by FPC soft boards are pullled etc., and overall yield is relatively low.
The method for packing of another fingerprint recognition chip is as shown in Fig. 2 a~Fig. 2 c：
The first step, as shown in Figure 2 a, through hole electrode is formed by silicon perforation TSV technology in fingerprint recognition chip 101
106；
Second step, as shown in Figure 2 b, one is layered in by sapphire cover plate 105, fingerprint recognition chip 101 and FPC plates 102
Rise, make metal connecting line 103 to connect the fingerprint recognition chip 101 and FPC plates 102 by routing technique；
3rd step, as shown in Figure 2 c, produces framework 104.
This method has the disadvantages that：Need to be encapsulated with sapphire cover plate, thickness is thicker, silicon perforation process costs compared with
Height, metal connecting line is easily broken caused by FPC soft boards are pullled etc., and the thinner thickness of fingerprint recognition chip, is easily split
Piece phenomenon, overall yield is relatively low.
Encapsulation based on the fingerprint recognition chip described above that yield is encapsulated there is provided a kind of low cost, low thickness and height
Structure and method for packing are necessary.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of encapsulation of fingerprint recognition chip
Structure and method for packing, for solving the problem of fingerprint recognition package thickness is larger, yield is more low in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of encapsulating structure of fingerprint recognition chip, institute
Stating encapsulating structure includes：Silicon substrate；Re-wiring layer, is formed on the silicon substrate；Metal lead wire, is welded by bonding wire craft
In on the re-wiring layer；Fingerprint recognition chip, is installed on the re-wiring layer by metal solder joints, wherein, it is described
The front of fingerprint recognition chip is toward the re-wiring layer；And encapsulating material, the fingerprint recognition chip is covered in, and
The metal lead wire is exposed to the encapsulating material.
Preferably, have between the fingerprint recognition chip and the re-wiring layer in gap, the gap and be formed with
The front of the fingerprint recognition chip is completely covered in protective layer, the protective layer.
Further, it is epoxy resin that the protective layer, which is selected,.
Preferably, in addition to PCB, the encapsulating material and the metal lead wire are gluing by ACF out-phase conductions
Together in the PCB, to realize the electric connection of the fingerprint recognition chip and the PCB.
Preferably, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip includes continuous dielectric layer,
And not comprising metal level, using the identification window as the fingerprint recognition chip.
Preferably, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
Preferably, the re-wiring layer includes patterned dielectric layer and patterned metal wiring layer.
Further, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
Glass, one or both of fluorine-containing glass combination of the above, the material of the metal wiring layer is included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.
Preferably, the material of the metal lead wire includes one kind in Au, Ag, Cu, Al.
Preferably, the thickness range of the silicon substrate is 1 μm~700 μm.
The present invention also provides a kind of method for packing of fingerprint recognition chip, and the method for packing includes step：1) one is provided
Silicon substrate, the silicon substrate has relative first surface and second surface；2) in formation on the first surface of the silicon substrate
Re-wiring layer, and by bonding wire craft in forming metal lead wire on the re-wiring layer；3) a fingerprint recognition chip is provided,
The fingerprint recognition chip is installed on the re-wiring layer by metal solder joints, wherein, the fingerprint recognition chip
Front is toward the re-wiring layer；4) the fingerprint recognition chip is encapsulated using encapsulating material, the metal lead wire exposes
In the encapsulating material；And 5) from the second surface of the silicon substrate silicon substrate is thinned.
Preferably, step 3) in, the fingerprint recognition chip is installed on the re-wiring layer by metal solder joints
Afterwards, there is gap, step 3 between the fingerprint recognition chip and the re-wiring layer) also it is included in formation in the gap
The front of the fingerprint recognition chip is completely covered in the step of protective layer, the protective layer.
Further, it is epoxy resin that the protective layer, which is selected, and the finger is formed at by the way of dispensing or molding
Gap between line identification chip and the re-wiring layer.
Preferably, in addition to step 6), the encapsulating material and the metal lead wire are bonded using ACF out-phase conducting resinl
In in PCB, to realize the electric connection of the fingerprint recognition chip and the PCB.
Preferably, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip includes continuous dielectric layer,
And not comprising metal level, using the identification window as the fingerprint recognition chip.
Preferably, step 2) make the re-wiring layer and include step：2-1) use chemical vapor deposition method or thing
Physical vapor deposition technique performs etching to form patterned Jie in surface of silicon formation dielectric layer to the dielectric layer
Matter layer；2-2) using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in the figure
Shape dielectric layer surface formation metal level, and the metal level is performed etching to form patterned metal wiring layer.
Further, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
Glass, one or both of fluorine-containing glass combination of the above, the material of the metal wiring layer is included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.
Preferably, step 2) in, the bonding wire craft includes hot pressing bonding wire craft, supersonic welding Wiring technology and hot pressing ultrasound
One kind in wave soldering Wiring technology..
Preferably, step 2) in, the material of the metal lead wire includes one kind in Au, Ag, Cu, Al.
Preferably, the method for the fingerprint recognition chip being encapsulated using encapsulating material include compression forming, transfer modling into
One kind in type, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material includes polyimides, silica gel and epoxy resin
In one kind.
Step 5) in, the silicon substrate is thinned using mechanical milling tech, the thickness model of the silicon substrate after being thinned
Enclose for 0 μm~700 μm.
As described above, the encapsulating structure and method for packing of the fingerprint recognition chip of the present invention, have the advantages that：
1) present invention uses fan-out package (Fan out) fingerprint recognition chip, compared to existing other fingerprint recognitions
For chip package, have the advantages that cost is low, thickness is small, yield is high；
2) present invention is without the need for routing technique, it is not required that the silicon perforation technique (TSV) of high cost, and can realize and refer to
The encapsulation of line identification chip, greatly reduces technology difficulty and cost；
3) present invention is directly known using re-wiring layer or re-wiring layer and the lamination of silicon substrate sheet as fingerprint
The cover plate of other chip, it is not necessary to increase sapphire cover plate in addition, greatly reduce the thickness and cost of encapsulation；
4) present invention is using encapsulation (Fan out) technique is fanned out to, and the electricity extraction of chip does not need traditional FPC plates, can be with
The thickness of encapsulation and the stability of electrical deriving structure are reduced, encapsulation yield is improved；
5) encapsulating material and the metal lead wire are bonded in PCB by ACF out-phase conducting resinl, are not required to
Wanting the welding procedure of high temperature just can realize the electric connection of the fingerprint recognition chip and the PCB, substantially increase
Technology stability and applicable scope.
6) present invention process is simple, creatively using packaging technology encapsulation fingerprint recognition chip is fanned out to, in semiconductor package
Dress technical field is with a wide range of applications.
Brief description of the drawings
What each step of method for packing that Fig. 1 a~Fig. 1 c are shown as a kind of fingerprint recognition chip of the prior art was presented
Structural representation.
Each step of method for packing that Fig. 2 a~Fig. 2 c are shown as another fingerprint recognition chip of the prior art is presented
Structural representation.
Fig. 3~Figure 11 is shown as the structural representation that each step of method for packing of the fingerprint recognition chip of the present invention is presented
Figure, wherein, Figure 11 is shown as the structural representation of the encapsulating structure of the fingerprint recognition chip of the present invention.
Figure 12 is shown as the use principle schematic diagram of the encapsulating structure of the fingerprint recognition chip of the present invention.
Component label instructions
201 silicon substrates
202 identification windows
203 dielectric layers
204 metal wiring layers
205 metal lead wires
206 fingerprint recognition chips
207 metal solder joints
208 protective layers
209 encapsulating materials
210 ACF out-phase conducting resinls
211 PCBs
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 3~Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only display is with relevant component in the present invention rather than according to package count during actual implement in illustrating then
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 3~Figure 11, the present embodiment provides a kind of method for packing of fingerprint recognition chip 206, and the fingerprint is known
Other chip 206 includes the fingerprint recognition core of the fingerprint recognition chip, capacitive fingerprint recognition chip and ultrasonic type of optical profile type
Piece, the method for packing includes step：
As shown in figure 3, carrying out step 1 first) there is provided a silicon substrate 201, the silicon substrate has relative first surface
And second surface.
The silicon substrate 201 is used to make re-wiring layer in its first surface, can obtain high-quality rewiring
Layer, the silicon substrate 201 subsequently after reduction process, can as fingerprint recognition chip-packaging structure cover sheet,
Sapphire cover plate need not additionally be increased, technique is smooth, while saving cost.
As shown in Fig. 4~Fig. 6, step 2 is then carried out), in forming re-wiring layer on the silicon substrate 201, and pass through
Bonding wire craft is in formation metal lead wire 205 on the re-wiring layer.
As an example, step 2) make the re-wiring layer and include step：
As shown in figure 4, carrying out step 2-1), using chemical vapor deposition method or physical gas-phase deposition in the silicon
The surface of substrate 201 forms dielectric layer 203, and the dielectric layer 203 is performed etching to form patterned dielectric layer 203.
As an example, the material of the dielectric layer 203 includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon
Glass, one or both of fluorine-containing glass combination of the above.In the present embodiment, it is silica that the dielectric layer 203, which is selected,.
As shown in figure 5, carrying out step 2-2), using chemical vapor deposition method, evaporation process, sputtering technology, galvanizer
Skill or chemical plating process perform etching to be formed in the patterned media 203 forming metal layer on surface of layer to the metal level
Patterned metal wiring layer 204.
As an example, the material of the metal wiring layer 204 include one or both of copper, aluminium, nickel, gold, silver, titanium with
Upper combination.In the present embodiment, the material selection of the metal wiring layer 204 is copper.
It should be noted that the re-wiring layer can include the multiple dielectric layers 203 and multiple gold stacked gradually
Belong to wiring layer 204, according to line demand, each layer metal is realized by being patterned or making through hole to each dielectric layer 203
Interconnection between wiring layer 204, to realize the line demand of difference in functionality.
As an example, the bonding wire craft includes hot pressing bonding wire craft, supersonic welding Wiring technology and thermosonic bonding wire
One kind in technique.As an example, the material of the metal lead wire 205 includes one kind in Au, Ag, Cu, Al.
For example, it is Al that the metal lead wire, which can be selected, at a lower temperature just can be complete using supersonic welding Wiring technology
Into welding, technological temperature can be greatly reduced.
And for example, the metal lead wire 205 can obtain excellent electric conductivity from being Au.
There are traditional hot welding some to be difficult to the defect overcome, be asked for example, being cleaned after the generation of thermal stress, welding
Topic, shortage flexibility and quality are difficult to control to.To make the input/output tie point of core on-chip circuit and being inscribed for lead frame
The lead of electrical connection is realized between contact, bonding wire craft (Wire Bonding) there should be conductance as connection lead
Rate is high, and conductive capability is strong, and the adhesion with conductor material is strong, the feature performance benefit such as stable chemical performance.
Specifically, the application has advantages below using bonding wire craft (Wire Bonding)：1) using aluminium wire weldering or aluminium
During tape welding, carry out at room temperature.Do not need any external temperature, weld zone temperature when ultrasonic friction is welded will not on
Rise.And other traditional welding manners then need heating could be by metal melt.2) Wire bonding are a clean welderings
Connection technology, and do not need the hygienic cleaning work after any welding.Had after conventional soldering techniques some welding assisted agent residuals or
The metal eruption of thawing needs to remove, it is to avoid produce integrity problem.And wire bonding then only have one on surface
Just need to be cleaned when a little pollutants or the oxide of stubbornness.3) Wire bonding have considerable flexibility, compatible
Property it is stronger, containing low gold thread height, the selection of many stitch, wide working range, banding or round wires shape selection.4) wire can have very well
Direction flexibility, mismatch can be controlled well between a variety of thermal expansion parameters.
As an example, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip 206 includes continuous Jie
Matter layer 203, and not comprising metal level, using the identification window 202 as the fingerprint recognition chip 206.Refer to for capacitive
Line identification chip and ultrasonic type, especially for the fingerprint recognition chip of optical profile type, the identification window 202 can obtain good
Good recognition effect.
As shown in Fig. 7~8, step 3 is then carried out) there is provided a fingerprint recognition chip 206, by metal solder joints 207 by institute
Fingerprint recognition chip 206 is stated to be installed on the re-wiring layer, wherein, the fingerprint recognition chip 206 front toward
The re-wiring layer；
As an example, the material that the metal solder joints 207 can be can be the metal materials such as copper, gold, silver, aluminium, tin.
As an example, step 3) in, by metal solder joints 207 by the fingerprint recognition chip 206 be installed in it is described again
After on wiring layer, there is gap, step 3 between the fingerprint recognition chip 206 and the re-wiring layer) be also included in it is described
The step of forming protective layer 208 in gap, the front of the fingerprint recognition chip 206 is completely covered in the protective layer 208.
As an example, the protective layer 208 is transparent polymeric layer, in the present embodiment, the protective layer 208 is selected
For epoxy resin, be formed at by the way of dispensing or molding the fingerprint recognition chip 206 and the re-wiring layer it
Between gap.The protective layer 208 can effectively protect the fingerprint recognition chip 206, for example, the entry types such as steam can be prevented
The other chip of fingerprint, and can as such as hit, press excessively etc. buffer structure.
Of course, it is possible to not make the protective layer 208 and directly the fingerprint recognition chip 206 is entered using encapsulating material
Row encapsulation.
As shown in figure 9, then carrying out step 4), the fingerprint recognition chip 206 is encapsulated using encapsulating material 209, it is described
Metal lead wire 205 is exposed to the encapsulating material 209.
As an example, the method for encapsulating the fingerprint recognition chip 206 using encapsulating material 209 includes compression forming, passed
Pass one kind in molded, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material 209 include polyimides, silica gel with
And one kind in epoxy resin.After encapsulation, the metal lead wire 205 is exposed to the encapsulating material 209, in favor of its with it is other
The electrical connection of device or the electrical extraction of itself.
As shown in Figure 10, step 5 is finally carried out), the silicon substrate 201 is thinned from the second surface of the silicon substrate 201.
As an example, the silicon substrate 201 is thinned using mechanical milling tech, the silicon substrate 201 after being thinned
Thickness range is 0 μm~700 μm.For example, the thickness of the silicon substrate 201 is preferably 50~100 μm, it on the one hand can be ensured
Mechanical strength, on the other hand can ensure the thickness of less encapsulating structure.Further illustrate, the silicon substrate 201 can
To be removed completely by reduction process, now, the fingerprint recognition chip can be by the re-wiring layer and/or the protection
Layer 208 is protected.Certainly, other reduction process are equally applicable, however it is not limited to example recited herein.
As shown in figure 11, step 6 is finally carried out), using ACF out-phase conducting resinl 210 by the encapsulating material 209 and described
Metal lead wire 205 is bonded in PCB 211, to realize the fingerprint recognition chip 206 and the PCB 211
It is electrically connected with.
The present invention is using anisotropic conductive adhesive paste (anisotropicconductivefilm, acf), by the encapsulating material
209 and the metal lead wire 205 be bonded in PCB 211 so that electric current can only by vertical PCB direction pass
Broadcast, and horizontal current spread can not be carried out, have unilateal conduction and glued fixed function concurrently, be avoided that adjacent two metal lead wire
Short circuit is turned between 205.
Finally, suitable framework is configured to packaged fingerprint recognition chip 206, so that it is applied to different function groups
In part, such as mobile phone, tablet personal computer, gate inhibition.
As shown in figure 11, the present embodiment also provides a kind of encapsulating structure of fingerprint recognition chip 206, the encapsulating structure bag
Include：Silicon substrate 201；Re-wiring layer, is formed on the surface of silicon substrate 201；Metal lead wire 205, is welded by bonding wire craft
It is connected on the re-wiring layer；Fingerprint recognition chip 206, is installed on the re-wiring layer by metal solder joints 207, its
In, the front of the fingerprint recognition chip 206 is toward the re-wiring layer；And encapsulating material 209, it is covered in the finger
Line identification chip 206, and the metal lead wire 205 is exposed to the encapsulating material 209.
As an example, having shape in gap, the gap between the fingerprint recognition chip 206 and the re-wiring layer
Into matcoveredn 208, the front of the fingerprint recognition chip 206 is completely covered in the protective layer 208.Further, it is described to protect
It is epoxy resin that sheath 208, which is selected,.
As an example, also including PCB 211, the encapsulating material 209 and the metal lead wire 205 are different by ACF
Phase conducting resinl 210 is bonded in the PCB 211, to realize the fingerprint recognition chip 206 and the PCB
211 electric connection.
As an example, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip 206 includes continuous Jie
Matter layer 203, and not comprising metal level, using the identification window 202 as the fingerprint recognition chip 206.
As an example, the encapsulating material 209 includes one kind in polyimides, silica gel and epoxy resin.
As an example, the re-wiring layer includes patterned dielectric layer 203 and patterned metal wiring layer
204.Further, the material of the dielectric layer 203 includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass,
One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer 204 is included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.
As an example, the material of the metal lead wire 205 includes one kind in Au, Ag, Cu, Al
As an example, the thickness range of the silicon substrate 201 is 1 μm~700 μm.For example, in the fingerprint recognition of this example
In the encapsulating structure of chip, the thickness of the silicon substrate 201 is preferably 50~100 μm, on the one hand can ensure its mechanical strength,
On the other hand the thickness of less encapsulating structure can be ensured.The silicon substrate 201 is used as fingerprint recognition chip-packaging structure
Cover sheet, it is not necessary to extra increase sapphire cover plate, technique is smooth, while saving cost.
As shown in figure 12, the use principle of the encapsulating structure of the fingerprint recognition chip 206 of the present embodiment is as shown in figure 12, its
Including：
The first step, the image of identification fingerprint needed for being obtained by the encapsulating structure of fingerprint recognition chip 206.In the present embodiment
In, the image of identification fingerprint needed for being obtained by the identification window 202.
Second step, is pre-processed as follows to the fingerprint image of collection, including：Picture quality judgement, image enhaucament, fingerprint
The gray value of each pixel in fingerprint image (is set to 0 by region detection, fingerprint orientation and frequence estimation, image binaryzation
255) and image thinning or.
3rd step, from pretreated image, obtains the crestal line data of fingerprint.
4th step, from the crestal line data of fingerprint, the characteristic point needed for the identification that takes the fingerprint.
5th step, the feature that takes the fingerprint (information of characteristic point) is matched one by one with the fingerprint characteristic preserved in database,
Determine whether identical fingerprints.
6th step, completes after fingerprint matching processing, exports the result of fingerprint recognition.
As described above, the encapsulating structure and method for packing of the fingerprint recognition chip 206 of the present invention, with following beneficial effect
Really：
1) present invention uses fan-out package (Fan out) fingerprint recognition chip 206, knows compared to existing other fingerprints
For other chip 206 is encapsulated, have the advantages that cost is low, thickness is small, yield is high；
2) present invention is without the need for routing technique, it is not required that the silicon perforation technique (TSV) of high cost, and can realize and refer to
The encapsulation of line identification chip 206, greatly reduces technology difficulty and cost；
3) present invention is directly known using re-wiring layer or re-wiring layer and the lamination of silicon substrate sheet as fingerprint
The cover plate of other chip 206, it is not necessary to increase sapphire cover plate in addition, greatly reduce the thickness and cost of encapsulation；
4) present invention is using encapsulation (Fan out) technique is fanned out to, and the electricity extraction of chip does not need traditional FPC plates, can be with
The thickness of encapsulation and the stability of electrical deriving structure are reduced, encapsulation yield is improved；
5) encapsulating material and the metal lead wire are bonded in PCB by ACF out-phase conducting resinl, are not required to
Wanting the welding procedure of high temperature just can realize the electric connection of the fingerprint recognition chip and the PCB, substantially increase
Technology stability and applicable scope.
6) present invention process is simple, creatively using packaging technology encapsulation fingerprint recognition chip is fanned out to, in semiconductor package
Dress technical field is with a wide range of applications.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (21)
1. a kind of encapsulating structure of fingerprint recognition chip, it is characterised in that the encapsulating structure includes：
Silicon substrate；
Re-wiring layer, is formed on the silicon substrate；
Metal lead wire, is welded on the re-wiring layer by bonding wire craft；
Fingerprint recognition chip, is installed on the re-wiring layer by metal solder joints, wherein, the fingerprint recognition chip is just
Facing in the re-wiring layer；And
Encapsulating material, is covered in the fingerprint recognition chip, and the metal lead wire is exposed to the encapsulating material.
2. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：The fingerprint recognition chip with
Have between the re-wiring layer in gap, the gap and form matcoveredn, the fingerprint is completely covered in the protective layer
The front of identification chip.
3. the encapsulating structure of fingerprint recognition chip according to claim 2, it is characterised in that：It is ring that the protective layer, which is selected,
Oxygen tree fat.
4. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：Also include PCB, institute
State encapsulating material and the metal lead wire to be bonded in the PCB by ACF out-phase conducting resinls, to realize the fingerprint
Identification chip and the electric connection of the PCB.
5. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：The re-wiring layer is with referring to
The vertical corresponding region of line identification chip includes continuous dielectric layer, and not comprising metal level, to be used as the fingerprint recognition
The identification window of chip.
6. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：The encapsulating material includes poly-
One kind in acid imide, silica gel and epoxy resin.
7. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：The re-wiring layer includes
Patterned dielectric layer and patterned metal wiring layer.
8. the method for packing of fingerprint recognition chip according to claim 7, it is characterised in that：The material bag of the dielectric layer
Include epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or both of fluorine-containing glass combination of the above, institute
Stating the material of metal wiring layer includes one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.
9. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：The material of the metal lead wire
Including one kind in Au, Ag, Cu, Al.
10. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that：The thickness of the silicon substrate
Scope is 1 μm~700 μm.
11. a kind of method for packing of fingerprint recognition chip, it is characterised in that the method for packing includes step：
1) silicon substrate is provided, the silicon substrate has relative first surface and second surface；
2) in forming re-wiring layer on the first surface of the silicon substrate, and by bonding wire craft on the re-wiring layer
Form metal lead wire；
3) a fingerprint recognition chip is provided, the fingerprint recognition chip is installed in the re-wiring layer by metal solder joints
On, wherein, the front of the fingerprint recognition chip is toward the re-wiring layer；
4) the fingerprint recognition chip is encapsulated using encapsulating material, the metal lead wire is exposed to the encapsulating material；And
5) silicon substrate is thinned from the second surface of the silicon substrate.
12. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Step 3) in, pass through gold
After the fingerprint recognition chip is installed on the re-wiring layer by category solder joint, the fingerprint recognition chip and the cloth again
There is gap, step 3 between line layer) also it is included in the step of forming protective layer in the gap, the protective layer is completely covered
The front of the fingerprint recognition chip.
13. the method for packing of fingerprint recognition chip according to claim 12, it is characterised in that：The protective layer is selected
Epoxy resin, between being formed between the fingerprint recognition chip and the re-wiring layer by the way of the dispensing or molding
Gap.
14. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Also include step 6), adopt
The encapsulating material and the metal lead wire are bonded in PCB with ACF out-phase conducting resinl, to realize that the fingerprint is known
Other chip and the electric connection of the PCB.
15. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：The re-wiring layer with
The vertical corresponding region of fingerprint recognition chip includes continuous dielectric layer, and not comprising metal level, to know as the fingerprint
The identification window of other chip.
16. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Step 2) make described heavy
New route layer includes step：
Dielectric layer 2-1) is formed in the surface of silicon using chemical vapor deposition method or physical gas-phase deposition, and it is right
The dielectric layer performs etching to form patterned dielectric layer；
2-2) using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in the figure
Change dielectric layer surface formation metal level, and the metal level is performed etching to form patterned metal wiring layer.
17. the method for packing of fingerprint recognition chip according to claim 16, it is characterised in that：The material of the dielectric layer
Including epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or both of fluorine-containing glass combination of the above,
The material of the metal wiring layer includes one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.
18. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Step 2) in, the weldering
Wiring technology includes one kind in hot pressing bonding wire craft, supersonic welding Wiring technology and thermosonic bonding wire craft.
19. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Step 2) in, the gold
Belonging to the material of lead includes one kind in Au, Ag, Cu, Al.
20. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Encapsulated using encapsulating material
The method of the fingerprint recognition chip includes one in compression forming, Transfer molding, fluid-tight shaping, vacuum lamination and spin coating
Kind, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
21. the method for packing of fingerprint recognition chip according to claim 11, it is characterised in that：Step 5) in, using machine
The silicon substrate is thinned tool grinding technics, and the thickness range of the silicon substrate after being thinned is 0 μm~700 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710523587.8A CN107146779B (en) | 2017-06-30 | 2017-06-30 | Packaging structure and packaging method of fingerprint identification chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710523587.8A CN107146779B (en) | 2017-06-30 | 2017-06-30 | Packaging structure and packaging method of fingerprint identification chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107146779A true CN107146779A (en) | 2017-09-08 |
| CN107146779B CN107146779B (en) | 2020-03-24 |
Family
ID=59784804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710523587.8A Active CN107146779B (en) | 2017-06-30 | 2017-06-30 | Packaging structure and packaging method of fingerprint identification chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107146779B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107491772A (en) * | 2017-09-26 | 2017-12-19 | 硕诺科技（深圳）有限公司 | A kind of fingerprint recognition module and PCB main board |
| CN108155160A (en) * | 2018-01-29 | 2018-06-12 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of fingerprint recognition chip |
| CN109181558A (en) * | 2018-08-16 | 2019-01-11 | 昆山建皇光电科技有限公司 | Adhesive process is welded in precuring |
| CN110571307A (en) * | 2019-09-16 | 2019-12-13 | 无锡中微晶园电子有限公司 | Photoelectric detection product bonding wire coating process |
| CN110600496A (en) * | 2019-09-20 | 2019-12-20 | 上海显耀显示科技有限公司 | Micro-LED chip packaging structure |
| CN111029261A (en) * | 2019-11-22 | 2020-04-17 | 徐州顺意半导体科技有限公司 | Biological identification module and preparation method thereof |
| CN111092019A (en) * | 2019-11-22 | 2020-05-01 | 徐州顺意半导体科技有限公司 | Fingerprint identification module and preparation method thereof |
| CN111952203A (en) * | 2020-08-25 | 2020-11-17 | 山东砚鼎电子科技有限公司 | Fingerprint identification package and forming method thereof |
| CN113035795A (en) * | 2019-06-14 | 2021-06-25 | 深圳市汇顶科技股份有限公司 | Chip packaging structure and electronic equipment |
| WO2021218161A1 (en) * | 2020-04-30 | 2021-11-04 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system encapsulation structure and method for manufacturing same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060065964A1 (en) * | 2004-09-30 | 2006-03-30 | Takashi Ohsumi | Semiconductor device comprising light-emitting element and light-receiving element, and manufacturing method therefor |
| CN103681362A (en) * | 2012-09-14 | 2014-03-26 | 新科金朋有限公司 | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
| CN105140213A (en) * | 2015-09-24 | 2015-12-09 | 中芯长电半导体（江阴）有限公司 | Chip packaging structure and chip packaging method |
| CN105470207A (en) * | 2015-12-24 | 2016-04-06 | 华天科技（西安）有限公司 | Fingerprint identification chip packaging structure based on high-flatness substrate and manufacturing method thereof |
| CN207165545U (en) * | 2017-06-30 | 2018-03-30 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure of fingerprint recognition chip |
-
2017
- 2017-06-30 CN CN201710523587.8A patent/CN107146779B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060065964A1 (en) * | 2004-09-30 | 2006-03-30 | Takashi Ohsumi | Semiconductor device comprising light-emitting element and light-receiving element, and manufacturing method therefor |
| CN103681362A (en) * | 2012-09-14 | 2014-03-26 | 新科金朋有限公司 | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
| CN105140213A (en) * | 2015-09-24 | 2015-12-09 | 中芯长电半导体（江阴）有限公司 | Chip packaging structure and chip packaging method |
| CN105470207A (en) * | 2015-12-24 | 2016-04-06 | 华天科技（西安）有限公司 | Fingerprint identification chip packaging structure based on high-flatness substrate and manufacturing method thereof |
| CN207165545U (en) * | 2017-06-30 | 2018-03-30 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure of fingerprint recognition chip |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107491772A (en) * | 2017-09-26 | 2017-12-19 | 硕诺科技（深圳）有限公司 | A kind of fingerprint recognition module and PCB main board |
| CN108155160A (en) * | 2018-01-29 | 2018-06-12 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of fingerprint recognition chip |
| CN109181558A (en) * | 2018-08-16 | 2019-01-11 | 昆山建皇光电科技有限公司 | Adhesive process is welded in precuring |
| CN113035795A (en) * | 2019-06-14 | 2021-06-25 | 深圳市汇顶科技股份有限公司 | Chip packaging structure and electronic equipment |
| US11545517B2 (en) | 2019-06-14 | 2023-01-03 | Shenzhen GOODIX Technology Co., Ltd. | Chip package structure, electronic device and method for preparing a chip package structure |
| CN110571307A (en) * | 2019-09-16 | 2019-12-13 | 无锡中微晶园电子有限公司 | Photoelectric detection product bonding wire coating process |
| CN110600496A (en) * | 2019-09-20 | 2019-12-20 | 上海显耀显示科技有限公司 | Micro-LED chip packaging structure |
| CN111029261A (en) * | 2019-11-22 | 2020-04-17 | 徐州顺意半导体科技有限公司 | Biological identification module and preparation method thereof |
| CN111092019A (en) * | 2019-11-22 | 2020-05-01 | 徐州顺意半导体科技有限公司 | Fingerprint identification module and preparation method thereof |
| CN111092019B (en) * | 2019-11-22 | 2021-11-02 | 绥化市鸿骏智能科技有限公司 | Fingerprint identification module and preparation method thereof |
| WO2021218161A1 (en) * | 2020-04-30 | 2021-11-04 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system encapsulation structure and method for manufacturing same |
| CN111952203A (en) * | 2020-08-25 | 2020-11-17 | 山东砚鼎电子科技有限公司 | Fingerprint identification package and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107146779B (en) | 2020-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107146779A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| US6344683B1 (en) | Stacked semiconductor package with flexible tape | |
| US6518097B1 (en) | Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive | |
| CN105140253B (en) | A kind of backside illuminated image chip die grade 3D stacked structures and packaging technology | |
| CN107507821A (en) | The encapsulating structure and method for packing of integrated image sensor chip and logic chip | |
| CN107146778A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| CN108155160A (en) | The encapsulating structure and packaging method of fingerprint recognition chip | |
| CN207977307U (en) | The encapsulating structure of fingerprint recognition chip | |
| CN212392240U (en) | Fan-out type packaging structure | |
| CN207165545U (en) | The encapsulating structure of fingerprint recognition chip | |
| CN107481979B (en) | The encapsulating structure and packaging method of fingerprint recognition chip | |
| CN107481992A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| CN107170721A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| CN207503967U (en) | The encapsulating structure of fingerprint recognition chip | |
| CN103915356B (en) | A kind of method for packing of chip | |
| CN207353228U (en) | The encapsulating structure of fingerprint recognition chip | |
| CN207165562U (en) | The chip-packaging structure of EMI protection | |
| CN110085973A (en) | Antenna packages structure and packaging method | |
| CN107644845A (en) | The encapsulating structure and method for packing of fingerprint recognition chip | |
| CN207852656U (en) | The encapsulating structure of fingerprint recognition chip | |
| US20150179557A1 (en) | Semiconductor chips having heat conductive layer with vias | |
| CN108109928A (en) | The encapsulating structure and method for packing of semiconductor chip | |
| CN207587718U (en) | The encapsulating structure of fingerprint recognition chip | |
| CN209804640U (en) | Packaging structure of fingerprint identification chip | |
| CN207852655U (en) | The encapsulating structure of semiconductor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Chen Yanheng Inventor after: Lin Zhengzhong Inventor after: He Zhihong Inventor after: Wu Zhengda Inventor before: Chen Yanheng Inventor before: Lin Zhengzhong Inventor before: He Zhihong Inventor before: Lin Zhengda |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |