CN107481979B - The encapsulating structure and packaging method of fingerprint recognition chip - Google Patents
The encapsulating structure and packaging method of fingerprint recognition chip Download PDFInfo
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- CN107481979B CN107481979B CN201710801546.0A CN201710801546A CN107481979B CN 107481979 B CN107481979 B CN 107481979B CN 201710801546 A CN201710801546 A CN 201710801546A CN 107481979 B CN107481979 B CN 107481979B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2512—Layout
- H01L2224/25171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The present invention provides the encapsulating structure and packaging method of a kind of fingerprint recognition chip, and the encapsulating structure includes: silicon substrate；Re-wiring layer is formed on the silicon substrate, and the re-wiring layer includes dielectric layer and metal wiring layer；Metal coupling is formed on metal wiring layer；Fingerprint recognition chip is installed on the metal wiring layer by metal solder joints, wherein the front of the fingerprint recognition chip is lower than the metal coupling upper surface toward the metal wiring layer, the back side of the fingerprint recognition chip.Chip protection layer, in the gap between the fingerprint recognition chip and re-wiring layer.The present invention has the advantages that at low cost, high production efficiency, thickness are small, yield is high for existing other fingerprint recognition chip packages using fan-out-type (Fan out) encapsulation fingerprint recognition chip.
Description
Technical field
The present invention relates to a kind of semiconductor package and packaging methods, more particularly to a kind of envelope of fingerprint recognition chip
Assembling structure and packaging method.
Background technique
As the function of integrated circuit is increasingly stronger, performance and integrated level is higher and higher and novel integrated circuit goes out
Existing, encapsulation technology plays an increasingly important role in IC products, shared in the value of entire electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when
The development of clock frequency, encapsulation also develop to more highdensity direction.
Fan-out wafer grade encapsulates (FOWLP) technology due to having many advantages, such as miniaturization, low cost and high integration, and tool
Have better performance and higher energy efficiency, therefore, it has also become the electronic equipments such as movement/wireless network of high request it is important
Packaging method, be one of encapsulation technology most with prospects at present.
Fingerprint identification technology is biometrics identification technology most mature and cheap at present.For at present, fingerprint is known
Other technical application is the most extensive, not only it can be seen that the figure of fingerprint identification technology, has in the market in gate inhibition, attendance checking system
The application of more fingerprint recognitions: as laptop, mobile phone, automobile, bank paying all can the technologies that identify of employing fingerprint.
Existing identification of fingerprint chip package substantially can be divided into using flexible circuit board or rigid circuit board as load-bearing part
Packaged type.The identification of fingerprint chip-packaging structure of flexible circuit board is usually will be to the sense wire for the fingerprint for recognizing user
Road is set on flexible circuit board, and user carries out identification of fingerprint by the sense line on contact flexible circuit board.So
And such packaged type is that identification of fingerprint chip is sent a signal to by the sense line on flexible circuit board, compared to directly existing
The mode of fingerprint sensing is carried out on identification of fingerprint chip, reaction speed is slower.And another common identification of fingerprint chip envelope
Assembling structure includes mainly then line carrier plate, identification of fingerprint chip, multiple bonding wires and packing colloid, wherein to recognize user
The sensing region of fingerprint be active surface positioned at identification of fingerprint chip mostly.And identification of fingerprint chip is usually with its back side
It fits on line carrier plate, and is electrically connected the active surface and line of identification of fingerprint chip with bonding wire in such a way that routing engages
Road-load plate.Therefore, need to be formed packing colloid on line carrier plate to coat identification of fingerprint chip and bonding wire.
A kind of packaging method of existing fingerprint recognition chip is as shown in Figure 1:
Fingerprint recognition chip 101 is bonded on FPC plate 102 using Flip Chip technique, fingerprint recognition chip 101 is logical
It crosses metal solder joints 103 and realizes being electrically connected for fingerprint recognition chip 101 and FPC plate 102, wherein FPC plate 102 is Flexible
The abbreviation of Printed Circuit, also known as flexible circuit board have the characteristics that Distribution density is high, light-weight, thickness is thin,
Inside includes sense line 104.Metal coupling 105 is formed on FPC plate 102, is filled out in the gap of chip 101 and FPC plate 102
Protection materials 106 are filled, encapsulation is completed.
This method, which has the disadvantages that, need to use that FPC plate is at high cost, need to carry out that production efficiency is slow, passes through sensing by item
Line transmissioning signal is slower to identification of fingerprint chip reaction speed.
The packaging method of another fingerprint recognition chip is as shown in Figure 2:
Fingerprint recognition chip 111 is pasted on pcb board 112 by adhesive 114, then passes through routing technique production gold
Belong to line 115, realization fingerprint recognition chip 111 is electrically connected with pcb board 112, wherein PCB is Printed Circuit
Circuit layer 113 is contained in the abbreviation of Board, inside.Packing colloid is coated in pcb board 112 and 111 surface of identification of fingerprint chip
116, packing colloid 116 coats metal connecting line 113 and fingerprint recognition chip 111.
This method has the disadvantages that including pcb board, fingerprint recognition chip, packing colloid three-decker.Need using
Pcb board is at high cost, it is slow to carry out production efficiency by item；Packing colloid is needed to encapsulate, thickness is thicker, at high cost.
Based on the above, a kind of encapsulation of the fingerprint recognition chip of low cost, high efficiency and low thickness is provided
Structure and packaging method are necessary.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of encapsulation of fingerprint recognition chip
Structure and packaging method are asked for solve that fingerprint recognition packaging cost in the prior art is high, production efficiency is low, thickness is larger etc.
Topic.
In order to achieve the above objects and other related objects, the present invention provides a kind of encapsulating structure of fingerprint recognition chip, institute
Stating encapsulating structure includes: silicon substrate；Re-wiring layer is formed on the silicon substrate, and the re-wiring layer includes dielectric layer
And metal wiring layer；Metal coupling is formed on the metal wiring layer；Fingerprint recognition chip, is installed by metal solder joints
In on the metal wiring layer, wherein know toward the metal wiring layer, the fingerprint in the front of the fingerprint recognition chip
The back side of other chip is lower than the metal coupling upper surface.Chip protection layer is located at the fingerprint recognition chip and rewiring
In gap between layer.
Preferably, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip includes continuous dielectric layer,
And do not include metal wiring layer, using the identification window as the fingerprint recognition chip.
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, silica, phosphorosilicate glass, in fluorine-containing glass
One or more combination, the material of the metal wiring layer include one or both of copper, aluminium, nickel, gold, silver, titanium with
Upper combination.
Preferably, the re-wiring layer includes N layers of dielectric layer and metal wiring layer, N >=1.
Preferably, the metal coupling includes solder bump or the metal coupling includes metal column and is located at golden
Belong to the solder bump above column.
Further, the material of the metal column includes one of copper, nickel, the material of the solder bump include copper,
One of nickel, tin and silver or alloy comprising any one of the above solder metal.
Preferably, the material of the protective layer includes epoxy resin.
Preferably, the thickness range of the silicon substrate is 1 μm~700 μm.
Preferably, the identification window thickness range is 701 μm~1400 μm.
The present invention also provides a kind of packaging method of fingerprint recognition chip, 1) packaging method is comprising steps of provide one
Silicon substrate, the silicon substrate have opposite first surface and second surface；2) it is formed on the first surface of Yu Suoshu silicon substrate
Re-wiring layer, the re-wiring layer include dielectric layer and metal wiring layer, and golden in being formed on the metal wiring layer
Belong to convex block；3) a fingerprint recognition chip is provided, the fingerprint recognition chip is installed in the metal line by metal solder joints
On layer, wherein toward the metal wiring layer, the back side of the fingerprint recognition chip is low in the front of the fingerprint recognition chip
In the metal coupling upper surface；4) chip protection layer is filled, between the fingerprint recognition chip and re-wiring layer
The silicon substrate is thinned in gap and 5) from the second surface of the silicon substrate.
Preferably, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip includes continuous dielectric layer,
And do not include metal wiring layer, using the identification window as the fingerprint recognition chip.
Preferably, the material of the dielectric layer include epoxy resin, silica gel, silica, phosphorosilicate glass, in fluorine-containing glass
One or more combination, the material of the metal wiring layer include one or both of copper, aluminium, nickel, gold, silver, titanium with
Upper combination.
Preferably, the re-wiring layer includes N layers of dielectric layer and metal wiring layer, N >=1.
Preferably, the metal coupling includes solder bump；Or the metal coupling includes metal column and is located at golden
Belong to the solder bump above column.
Further, the material of the metal column includes one of copper, nickel, the material of the solder bump include copper,
One of nickel, tin and silver or alloy comprising any one of the above solder metal.
Preferably, step 2) makes the re-wiring layer comprising steps of 2-1) use chemical vapor deposition process or object
Physical vapor deposition technique forms dielectric layer in the surface of silicon, and performs etching to form patterned Jie to the dielectric layer
Matter layer；2-2) using chemical vapor deposition process, evaporation process, sputtering technology, electroplating technology or chemical plating process in the figure
Shape dielectric layer surface forms metal layer, and performs etching to form patterned metal wiring layer to the metal layer.
Preferably, the preparation method of the metal coupling is comprising steps of a) using galvanoplastic in the metal wiring layer table
Face forms the solder bump or forms metal column and solder bump；B) metal coupling is formed using high temperature reflow processes.
Preferably, in step 4), the material of the protective layer includes epoxy resin, the shape by the way of dispensing or molding
Gap between fingerprint recognition chip and the re-wiring layer described in Cheng Yu.
Preferably, in step 5), thinned silicon substrate after being thinned is carried out to the silicon substrate using mechanical milling tech
Thickness range is 1 μm~700 μm.
Preferably, the identification window thickness range is 701 μm~1400 μm.
As described above, the encapsulating structure and packaging method of fingerprint recognition chip of the invention, have the advantages that this
Invention encapsulates fingerprint recognition chip using fan-out-type (Fan out), does not need routing technique, circuit board, capsulation material and can
It carries out more chips to stack to form stacked body, for existing other fingerprint recognition chip packages, saves cost, it is good
Rate is high, and thickness is small；Due to carrying out the mode of fingerprint sensing directly above identification of fingerprint chip, reaction speed is very fast；Medium
Layer and protective layer cover chip surface, prevent the direct contact chip front of finger, avoid wafer surface contamination；Meanwhile it can be with
It is manufactured with wafer scale, is improved relative to its production efficiency is produced by item.Therefore, the present invention has at low cost, production efficiency
The advantage high, thickness is small, yield is high, meanwhile, present invention process is simple, creatively uses and is fanned out to packaging technology encapsulation fingerprint knowledge
Other chip, is with a wide range of applications in technical field of semiconductor encapsulation.
Detailed description of the invention
Fig. 1 is shown as the structural schematic diagram that a kind of packaging method of fingerprint recognition chip in the prior art is presented.
Fig. 2 is shown as the structural schematic diagram that the packaging method of another fingerprint recognition chip in the prior art is presented.
Fig. 3~Fig. 9 is shown as the structural schematic diagram that each step of packaging method of fingerprint recognition chip of the invention is presented.
Fig. 9 is shown as the structural schematic diagram of the encapsulating structure of fingerprint recognition chip of the invention.
Figure 10 is shown as the use schematic illustration of the encapsulating structure of fingerprint recognition chip of the invention.
Component label instructions
201 silicon substrates
202 identification windows
203 dielectric layers
204 metal wiring layers
205 metal couplings
206 fingerprint recognition chips
207 metal solder joints
208 protective layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 3~Figure 10.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in diagram then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 3~Fig. 9, the present embodiment provides a kind of packaging method of fingerprint recognition chip 206, the fingerprint recognitions
The fingerprint recognition chip of the fingerprint recognition chip of chip 206 including optical profile type, capacitive fingerprint recognition chip and ultrasonic type
One of or it is a variety of, the packaging method comprising steps of
As shown in figure 3, carrying out step 1) first, a silicon substrate 201 is provided, the silicon substrate has opposite first surface
And second surface.
The silicon substrate 201 is used to make re-wiring layer in its first surface, can obtain the rewiring of high quality
Layer, the silicon substrate 201 after reduction process, can be used as the cover sheet of fingerprint recognition chip-packaging structure subsequent,
It does not need additionally to increase sapphire cover board or capsulation material, technique is smooth, while saving cost.
As shown in Fig. 4~Fig. 6, step 2) is then carried out, forms re-wiring layer on Yu Suoshu silicon substrate 201, it is described heavy
New route layer includes dielectric layer 203 and metal wiring layer 204, and in formation metal coupling 205 on the re-wiring layer.
As an example, step 2) make the re-wiring layer comprising steps of
As shown in figure 4, carrying out step 2-1), using chemical vapor deposition process or physical gas-phase deposition in the silicon
201 surface of substrate forms dielectric layer 203, and performs etching to form patterned dielectric layer 203 to the dielectric layer 203.
As an example, the material of the dielectric layer 203 includes epoxy resin, silica gel, silica, phosphorosilicate glass, fluorine-containing glass
The combination of one or more of glass.In the present embodiment, it is silica that the dielectric layer 203, which is selected,.
As shown in figure 5, carrying out step 2-2), using chemical vapor deposition process, evaporation process, sputtering technology, galvanizer
Skill or chemical plating process form metal wiring layer 204 in 203 surface of patterned media layer, and to the metal wiring layer
204 perform etching to form patterned metal wiring layer 204.
As an example, the material of the metal wiring layer 204 include one or both of copper, aluminium, nickel, gold, silver, titanium with
Upper combination.In the present embodiment, the material selection of the metal wiring layer 204 is copper.
As an example, the re-wiring layer includes N layers of dielectric layer and metal wiring layer, N >=1 leads to according to line demand
It crosses and is patterned or makes through-hole to each dielectric layer 203 and realize interconnection between each layer metal wiring layer 204, to realize not
The line demand of congenerous.
As an example, the metal coupling 205 includes solder bump；Or the metal coupling includes metal column and position
Solder bump above metal column.
As an example, the material of the metal column includes one of copper, nickel, the material of the solder bump include copper,
One of nickel, tin and silver or alloy comprising any one of the above solder metal.
Specifically, the metal coupling 205 can select for solder bump, copper post and solder above copper post it is convex
Point, nickel column and combination of the solder bump above nickel column etc..In the present embodiment, the metal coupling 205 is selected as weldering
Expect salient point (such as tin ball), the preparation method of the metal coupling 205 comprising steps of
Step a) forms solder bump (such as tin ball) in the rewiring layer surface using galvanoplastic；
Step b) forms the metal coupling 205 using high temperature reflow processes.
As an example, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip 206 includes continuous Jie
Matter layer 203, and do not include metal wiring layer 204, using the identification window 202 as the fingerprint recognition chip 206.For capacitor
The fingerprint recognition chip of formula and ultrasonic type, especially for the fingerprint recognition chip of optical profile type, the identification window 202 can be with
Obtain good recognition effect.
As shown in Fig. 7~8, step 3) is then carried out, a fingerprint recognition chip 206 is provided, by metal solder joints 207 by institute
Fingerprint recognition chip 206 is stated to be installed on the metal wiring layer 204, wherein the fingerprint recognition chip 206 just facing towards
It is lower than 205 upper surface of metal coupling in the back side of the metal wiring layer 204, the fingerprint recognition chip 206, in favor of
Its being electrically connected with other devices or the electrical of itself are drawn.
As an example, the material of the metal solder joints 207 includes one of copper, gold, silver, aluminium, tin or comprising above-mentioned
It anticipates the alloy of solder metal a kind of.
As an example, the fingerprint recognition chip 206 is installed in the metal by metal solder joints 207 in step 3)
On wiring layer 204, there is gap between the fingerprint recognition chip 206 and the re-wiring layer.
As an example, step 4) fills chip protection layer 208, the fingerprint recognition core is completely covered in the protective layer 208
The front of piece 206.
As an example, the protective layer 208 is transparent polymeric layer, in the present embodiment, the protective layer 208 is selected
For epoxy resin, be formed in by the way of dispensing or molding the fingerprint recognition chip 206 and the re-wiring layer it
Between gap.The protective layer 208 can effectively protect the fingerprint recognition chip 206, for example, the entry types such as steam can be prevented
The other chip of fingerprint, and can be used as and such as hit, press excessive buffer structure.
As shown in figure 9, finally carrying out step 5), the silicon substrate 201 is thinned from the second surface of the silicon substrate 201.
As an example, thinned silicon substrate 201 after being thinned is carried out to the silicon substrate 201 using mechanical milling tech
Thickness range is 1 μm~700 μm.For example, the thickness of the silicon substrate 201 is preferably 50~100 μm, it on the one hand can guarantee it
On the other hand mechanical strength can guarantee the thickness of lesser encapsulating structure.Certainly, other reduction process are equally applicable,
It is not limited to example recited herein.
As an example, 202 thickness range of identification window is 701 μm~1400 μm.202 thickness of identification window is with described
The thickness change of re-wiring layer and the silicon substrate 201 and change, the thickness to fingerprint recognition chip 206 receive fingerprint
Information has an impact, and identification window 202 is blocked up, and the reception of fingerprint recognition chip 206 finger print information intensity is weak, the reaction time is long and seals
It is thick to fill thickness, identification window 202 is excessively thin, and it is poor to 206 protective effect of fingerprint recognition chip, good protection cannot be played and made
With.The present embodiment preferred thickness is 100~200 μm.
Finally, the encapsulating structure of fingerprint recognition chip 206 is configured into suitable frame or is applied in package stack stack, with
It is applied to it in different functional units, such as mobile phone, tablet computer, gate inhibition.
As shown in figure 9, the present embodiment also provides a kind of encapsulating structure of fingerprint recognition chip 206, the encapsulating structure packet
It includes: silicon substrate 201；Re-wiring layer is formed on the silicon substrate 201, the re-wiring layer include dielectric layer 203 and
Metal wiring layer 204；Metal coupling 205 is formed on the metal wiring layer 204；Fingerprint recognition chip 206, passes through metal
Solder joint 207 is installed on the metal wiring layer 204, wherein the front of the fingerprint recognition chip 206 is toward the metal
The back side of wiring layer 204, the fingerprint recognition chip 206 is lower than 205 upper surface of metal coupling；Chip protection layer 208, position
In gap between the fingerprint recognition chip 206 and re-wiring layer.
As an example, the vertical corresponding region of the re-wiring layer and fingerprint recognition chip 206 includes continuous Jie
Matter layer 203, and do not include metal wiring layer, using the identification window 202 as the fingerprint recognition chip 206.
As an example, the material of the dielectric layer 203 includes epoxy resin, silica gel, silica, phosphorosilicate glass, fluorine-containing glass
The combination of one or more of glass, the material of the metal wiring layer 204 includes one of copper, aluminium, nickel, gold, silver, titanium
Or two or more combinations.
As an example, the re-wiring layer includes N layers of dielectric layer and metal wiring layer, N >=1 leads to according to line demand
It crosses and is patterned or makes through-hole to each dielectric layer 203 and realize interconnection between each layer metal wiring layer 204, to realize not
The line demand of congenerous.
As an example, the metal coupling 205 includes solder bump；Or the metal coupling includes metal column and position
Solder bump above metal column.
As an example, the material of the metal column includes one of copper, nickel, the material of the solder bump include copper,
One of nickel, tin and silver or alloy comprising any one of the above solder metal.
Specifically, the metal coupling 205 can select for solder bump, copper post and solder above copper post it is convex
Point, nickel column and combination of the solder bump above nickel column etc..
As an example, the front of the fingerprint recognition chip 206 is completely covered in the protective layer 208.Further, described
It is epoxy resin that protective layer 208, which is selected,.
As an example, the thickness range of the silicon substrate 201 is 1 μm~700 μm.For example, in this exemplary fingerprint recognition
In the encapsulating structure of chip, the thickness of the silicon substrate 201 is preferably 50~100 μm, on the one hand can guarantee its mechanical strength,
On the other hand it can guarantee the thickness of lesser encapsulating structure.The silicon substrate 201 is as fingerprint recognition chip-packaging structure
Cover sheet does not need additionally to increase sapphire cover board or capsulation material, and technique is smooth, while saving cost.
As an example, 202 thickness range of identification window is 701 μm~1400 μm.202 thickness of identification window is with described
The thickness change of re-wiring layer and the silicon substrate 201 and change, the thickness to fingerprint recognition chip 206 receive fingerprint
Information has an impact, and identification window 202 is blocked up, and the reception of fingerprint recognition chip 206 finger print information intensity is weak, the reaction time is long and seals
It is thick to fill thickness, identification window 202 is excessively thin, and it is poor to 206 protective effect of fingerprint recognition chip, good protection cannot be played and made
With.The present embodiment preferred thickness is 100~200 μm.
As shown in Figure 10, the use principle of the encapsulating structure of the fingerprint recognition chip 206 of the present embodiment is as shown in Figure 10,
Include:
The first step, the image of identification fingerprint needed for being obtained by the encapsulating structure of fingerprint recognition chip 206.In the present embodiment
In, the image of identification fingerprint needed for being obtained by the identification window 202.
Second step pre-processes the fingerprint image of acquisition as follows, comprising: picture quality judgement, image enhancement, fingerprint
Region detection, fingerprint orientation and frequence estimation, image binaryzation (set 0 for the gray value of pixel each in fingerprint image
Or 255) and image thinning.
Third step obtains the crestal line data of fingerprint from pretreated image.
4th step takes the fingerprint from the crestal line data of fingerprint and identifies required characteristic point.
5th step matches the feature that takes the fingerprint (information of characteristic point) with the fingerprint characteristic saved in database one by one,
Judge whether it is identical fingerprints.
6th step exports the processing result of fingerprint recognition after completing fingerprint matching processing.
As described above, the encapsulating structure and packaging method of fingerprint recognition chip 206 of the invention, have below beneficial to effect
Fruit: the present invention using fan-out-type (Fan out) encapsulate fingerprint recognition chip, do not need routing technique, circuit board, capsulation material with
And more chips can be carried out and stack to form stacked body, for existing other fingerprint recognition chip packages, save into
This, yield is high, and thickness is small；Due to carrying out the mode of fingerprint sensing directly above identification of fingerprint chip, reaction speed is very fast；
Dielectric layer and protective layer cover chip surface, prevent the direct contact chip front of finger, avoid wafer surface contamination；Meanwhile
It can be manufactured with wafer scale, be improved relative to its production efficiency is produced by item.Therefore, the present invention has at low cost, production
Advantage high-efficient, thickness is small, yield is high, meanwhile, present invention process is simple, and creatively use is fanned out to packaging technology encapsulation and refers to
Line identification chip is with a wide range of applications in technical field of semiconductor encapsulation.So the present invention effectively overcomes existing skill
Various shortcoming in art and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (14)
1. a kind of encapsulating structure of fingerprint recognition chip, which is characterized in that the encapsulating structure includes:
Silicon substrate, the thickness range of the silicon substrate after being thinned are 50~100 μm；
Re-wiring layer is formed on the silicon substrate, and the re-wiring layer includes dielectric layer and metal wiring layer；
Metal coupling is formed on the metal wiring layer；
Fingerprint recognition chip is installed on the metal wiring layer by metal solder joints, wherein the fingerprint recognition chip is just
It is lower than the metal coupling upper surface facing towards in the back side of the metal wiring layer, the fingerprint recognition chip；
The vertical corresponding region of the re-wiring layer and fingerprint recognition chip includes continuous dielectric layer, and is not included described
Metal wiring layer, using the identification window as the fingerprint recognition chip；
Chip protection layer, in the gap between the fingerprint recognition chip and the re-wiring layer；
The identification window thickness range is 100 μm~200 μm.
2. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that: the material packet of the dielectric layer
Include epoxy resin, silica gel, silica, phosphorosilicate glass, the combination of one or more of fluorine-containing glass, the metal wiring layer
Material include one or more of copper, aluminium, nickel, gold, silver, titanium combination.
3. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that: the re-wiring layer includes
N layers of dielectric layer and metal wiring layer, N >=1.
4. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that: the metal coupling includes weldering
Expect salient point；Or the metal coupling includes metal column and the solder bump above metal column.
5. the encapsulating structure of fingerprint recognition chip according to claim 4, it is characterised in that: the material packet of the metal column
Include one of copper, nickel, the material of the solder bump includes one of copper, nickel, tin and silver or comprising any one of the above
The alloy of solder metal.
6. the encapsulating structure of fingerprint recognition chip according to claim 1, it is characterised in that: the material packet of the protective layer
Include epoxy resin.
7. a kind of packaging method of fingerprint recognition chip, which is characterized in that the packaging method comprising steps of
1) silicon substrate is provided, the silicon substrate has opposite first surface and second surface；
2) re-wiring layer is formed on the first surface of Yu Suoshu silicon substrate, the re-wiring layer includes dielectric layer and metal
Wiring layer, and in forming metal coupling on the metal wiring layer；
3) a fingerprint recognition chip is provided, the fingerprint recognition chip is installed in the metal wiring layer by metal solder joints
On, wherein toward the metal wiring layer, the back side of the fingerprint recognition chip is lower than in the front of the fingerprint recognition chip
The metal coupling upper surface；The vertical corresponding region of the re-wiring layer and fingerprint recognition chip includes continuous medium
Layer, and do not include the metal wiring layer, using the identification window as the fingerprint recognition chip, the identification window thickness model
Enclose is 100 μm~200 μm；
4) chip protection layer is filled, in the gap between the fingerprint recognition chip and the re-wiring layer, and
5) silicon substrate is thinned from the second surface of the silicon substrate, the thickness range of the silicon substrate after being thinned is 50~100 μ
m。
8. the packaging method of fingerprint recognition chip according to claim 7, it is characterised in that: the material packet of the dielectric layer
Include the combination of one or more of epoxy resin, silica gel, silica, phosphorosilicate glass, fluorine-containing glass, the metal wiring layer
Material include one or more of copper, aluminium, nickel, gold, silver, titanium combination.
9. the packaging method of fingerprint recognition chip according to claim 7, it is characterised in that: the re-wiring layer includes
N layers of dielectric layer and metal wiring layer, N >=1.
10. the packaging method of fingerprint recognition chip according to claim 7, it is characterised in that: the metal coupling includes
Solder bump；Or the metal coupling includes metal column and the solder bump above metal column.
11. the packaging method of fingerprint recognition chip according to claim 10, it is characterised in that: the material of the metal column
Including one of copper, nickel, the material of the solder bump includes one of copper, nickel, tin and silver or comprising above-mentioned any one
The alloy of kind solder metal.
12. the packaging method of fingerprint recognition chip according to claim 7, it is characterised in that: step 2) production is described heavy
New route layer comprising steps of
Dielectric layer 2-1) is formed in the surface of silicon using chemical vapor deposition process or physical gas-phase deposition, and right
The dielectric layer performs etching to form patterned dielectric layer；
2-2) using chemical vapor deposition process, evaporation process, sputtering technology, electroplating technology or chemical plating process in the figure
Change dielectric layer surface and form metal layer, and the metal layer is performed etching to form patterned metal wiring layer.
13. the packaging method of fingerprint recognition chip according to claim 10, it is characterised in that: the system of the metal coupling
Preparation Method comprising steps of
A) solder bump is formed in the metal line layer surface using galvanoplastic or form metal column and solder bump；
B) metal coupling is formed using high temperature reflow processes.
14. the packaging method of fingerprint recognition chip according to claim 7, it is characterised in that: in step 4), the protection
The material of layer includes epoxy resin, and the fingerprint recognition chip and the cloth again are formed in by the way of dispensing or molding
Gap between line layer.
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| CN110148567A (en) * | 2019-06-06 | 2019-08-20 | 中芯长电半导体（江阴）有限公司 | A kind of encapsulating structure and packaging method of fingerprint recognition chip |
| CN111952202B (en) * | 2020-08-25 | 2022-09-09 | 山东乾元半导体科技有限公司 | Packaging structure of fingerprint identification sensor and forming method thereof |
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| CN105405816A (en) * | 2015-12-28 | 2016-03-16 | 江阴长电先进封装有限公司 | Packaging structure of fingerprint identification sensor |
| CN105470207A (en) * | 2015-12-24 | 2016-04-06 | 华天科技（西安）有限公司 | Fingerprint identification chip packaging structure based on high-flatness substrate and manufacturing method thereof |
| CN106657478A (en) * | 2017-01-20 | 2017-05-10 | 广东欧珀移动通信有限公司 | Fingerprint recognition module and mobile terminal |
| CN107170721A (en) * | 2017-06-30 | 2017-09-15 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of fingerprint recognition chip |
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| JP2006128625A (en) * | 2004-09-30 | 2006-05-18 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
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|---|---|---|---|---|
| CN105470207A (en) * | 2015-12-24 | 2016-04-06 | 华天科技（西安）有限公司 | Fingerprint identification chip packaging structure based on high-flatness substrate and manufacturing method thereof |
| CN105405816A (en) * | 2015-12-28 | 2016-03-16 | 江阴长电先进封装有限公司 | Packaging structure of fingerprint identification sensor |
| CN106657478A (en) * | 2017-01-20 | 2017-05-10 | 广东欧珀移动通信有限公司 | Fingerprint recognition module and mobile terminal |
| CN107170721A (en) * | 2017-06-30 | 2017-09-15 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of fingerprint recognition chip |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |