CN107112199B - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN107112199B
CN107112199B CN201580069954.0A CN201580069954A CN107112199B CN 107112199 B CN107112199 B CN 107112199B CN 201580069954 A CN201580069954 A CN 201580069954A CN 107112199 B CN107112199 B CN 107112199B
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bonding
intermediate layer
substrates
wafer
semiconductor device
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Chinese (zh)
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CN107112199A (zh
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内海淳
后藤崇之
铃木毅典
井手健介
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Mitsubishi Heavy Industries Ltd
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Mitsubishi Heavy Industries Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
CN201580069954.0A 2014-12-22 2015-10-07 半导体装置及半导体装置的制造方法 Active CN107112199B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014-259115 2014-12-22
JP2014259115A JP6165127B2 (ja) 2014-12-22 2014-12-22 半導体装置及び半導体装置の製造方法
PCT/JP2015/078518 WO2016103846A1 (ja) 2014-12-22 2015-10-07 半導体装置及び半導体装置の製造方法

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CN107112199A CN107112199A (zh) 2017-08-29
CN107112199B true CN107112199B (zh) 2021-08-17

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US (1) US10486263B2 (cg-RX-API-DMAC10.html)
EP (1) EP3240015B1 (cg-RX-API-DMAC10.html)
JP (1) JP6165127B2 (cg-RX-API-DMAC10.html)
KR (1) KR101994011B1 (cg-RX-API-DMAC10.html)
CN (1) CN107112199B (cg-RX-API-DMAC10.html)
TW (1) TWI596651B (cg-RX-API-DMAC10.html)
WO (1) WO2016103846A1 (cg-RX-API-DMAC10.html)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
TWI910033B (zh) 2016-10-27 2025-12-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN111370339B (zh) * 2020-03-20 2022-02-22 中国科学院半导体研究所 晶圆的室温等静压金属键合方法
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
CN114628240B (zh) * 2020-12-10 2024-10-15 武汉新芯集成电路股份有限公司 芯片晶圆的堆叠方法
TW202618935A (zh) 2020-12-30 2026-05-01 美商艾德亞半導體接合科技有限公司 具有導電特徵的結構以及形成此結構的方法
US20220285303A1 (en) * 2021-03-03 2022-09-08 Invensas Bonding Technologies, Inc. Contact structures for direct bonding
JP7222493B2 (ja) 2021-04-28 2023-02-15 日本電産マシンツール株式会社 半導体装置の製造方法、及び常温接合装置
US12622307B2 (en) 2021-12-23 2026-05-05 Adeia Semiconductor Bonding Technologies Inc. Controlled grain growth for bonding and bonded structure with controlled grain growth
JP2023137581A (ja) 2022-03-18 2023-09-29 キオクシア株式会社 半導体装置、半導体装置の製造方法
FR3134227A1 (fr) * 2022-04-04 2023-10-06 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de collage d’un premier substrat au niveau d’une surface présentant une nanotopologie élastique
JP2025514099A (ja) 2022-04-25 2025-05-02 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド ダイレクトボンディング用膨張制御型構造体及びその形成方法
CN114999948A (zh) * 2022-06-06 2022-09-02 闽南师范大学 一种高真空磁控溅射热压键合一体机以及键合方法
US12545010B2 (en) 2022-12-29 2026-02-10 Adeia Semiconductor Bonding Technologies Inc. Directly bonded metal structures having oxide layers therein
US12506114B2 (en) 2022-12-29 2025-12-23 Adeia Semiconductor Bonding Technologies Inc. Directly bonded metal structures having aluminum features and methods of preparing same
CN116092953B (zh) * 2023-03-07 2023-07-18 天津中科晶禾电子科技有限责任公司 一种晶圆键合装置、方法及复合衬底组件
JP7526450B1 (ja) * 2024-03-22 2024-08-01 エスエイチダブリュウテクノロジーズ(シャンハイ)ユウゲンコウシ 半導体ウエーハの接合装置及び接合方法
JP7856933B2 (ja) * 2024-03-29 2026-05-12 ダイキン工業株式会社 積層体の製造方法および積層体

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070128825A1 (en) * 2005-12-02 2007-06-07 Tadatomo Suga Method for bonding substrates and device for bonding substrates
CN102782850A (zh) * 2010-03-02 2012-11-14 美光科技公司 绝缘体上半导体金属结构、形成此些结构的方法及包含此些结构的半导体装置
JP2012238729A (ja) * 2011-05-12 2012-12-06 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
CN103460339A (zh) * 2011-01-31 2013-12-18 须贺唯知 接合面制作方法、接合基板、基板接合方法、接合面制作装置以及基板接合体

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2642645B2 (ja) * 1987-11-19 1997-08-20 株式会社日立製作所 半導体基板の製造方法及び半導体装置の製造方法
JPH0684733A (ja) * 1992-09-03 1994-03-25 Hitachi Ltd 半導体集積回路装置とその製造方法及び半導体集積回路製造装置
JP2791429B2 (ja) * 1996-09-18 1998-08-27 工業技術院長 シリコンウェハーの常温接合法
DE19648759A1 (de) * 1996-11-25 1998-05-28 Max Planck Gesellschaft Verfahren zur Herstellung von Mikrostrukturen sowie Mikrostruktur
JP3171322B2 (ja) * 1997-03-11 2001-05-28 日本電気株式会社 Soi基板およびその製造方法
FR2783969B1 (fr) * 1998-09-28 2002-01-18 Commissariat Energie Atomique Dispositif hybride et procede de realisation de composants electriquement actifs par assemblage
US6387736B1 (en) * 1999-04-26 2002-05-14 Agilent Technologies, Inc. Method and structure for bonding layers in a semiconductor device
JP4275806B2 (ja) * 1999-06-01 2009-06-10 株式会社ルネサステクノロジ 半導体素子の実装方法
FR2798224B1 (fr) * 1999-09-08 2003-08-29 Commissariat Energie Atomique Realisation d'un collage electriquement conducteur entre deux elements semi-conducteurs.
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
US7330612B2 (en) * 2002-05-28 2008-02-12 Matsushita Electric Works, Ltd. Material for substrate mounting optical circuit-electric circuit mixedly and substrate mounting optical circuit-electric circuit mixedly
US7114361B2 (en) * 2003-09-12 2006-10-03 Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College Microscale compression molding of metals with surface engineered LIGA inserts
FR2864336B1 (fr) * 2003-12-23 2006-04-28 Commissariat Energie Atomique Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci
EP1557449A1 (en) * 2004-01-22 2005-07-27 3M Innovative Properties Company Adhesive tape for structural bonding
JP3790995B2 (ja) * 2004-01-22 2006-06-28 有限会社ボンドテック 接合方法及びこの方法により作成されるデバイス並びに接合装置
FR2872625B1 (fr) * 2004-06-30 2006-09-22 Commissariat Energie Atomique Assemblage par adhesion moleculaire de deux substrats, l'un au moins supportant un film conducteur electrique
US7345344B2 (en) * 2006-02-16 2008-03-18 Freescale Semiconductor, Inc. Embedded substrate interconnect for underside contact to source and drain regions
JP4162094B2 (ja) 2006-05-30 2008-10-08 三菱重工業株式会社 常温接合によるデバイス、デバイス製造方法ならびに常温接合装置
JP4172806B2 (ja) * 2006-09-06 2008-10-29 三菱重工業株式会社 常温接合方法及び常温接合装置
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
JP4967842B2 (ja) * 2007-06-18 2012-07-04 セイコーエプソン株式会社 シリコン基材の接合方法、液滴吐出ヘッド、液滴吐出装置および電子デバイス
RU2010114227A (ru) * 2007-09-12 2011-10-20 Смольтек Аб (Se) Соединение и связывание соседних слоев наноструктурами
JP4786693B2 (ja) * 2008-09-30 2011-10-05 三菱重工業株式会社 ウェハ接合装置およびウェハ接合方法
JP5342210B2 (ja) * 2008-10-30 2013-11-13 三菱重工業株式会社 アライメント装置制御装置およびアライメント方法
JP5389627B2 (ja) * 2008-12-11 2014-01-15 信越化学工業株式会社 ワイドバンドギャップ半導体を積層した複合基板の製造方法
JP4796120B2 (ja) * 2008-12-11 2011-10-19 三菱重工業株式会社 常温接合装置
JP2010278337A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 表面欠陥密度が少ないsos基板
US8507966B2 (en) * 2010-03-02 2013-08-13 Micron Technology, Inc. Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same
US8647962B2 (en) * 2010-03-23 2014-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging bond
JP4831844B1 (ja) * 2010-09-28 2011-12-07 三菱重工業株式会社 常温接合装置および常温接合方法
US8563396B2 (en) * 2011-01-29 2013-10-22 International Business Machines Corporation 3D integration method using SOI substrates and structures produced thereby
KR101985526B1 (ko) * 2011-01-31 2019-06-03 다다또모 스가 접합 기판 제작 방법, 접합 기판, 기판 접합 방법, 접합 기판 제작 장치 및 기판 접합체
KR20130016682A (ko) * 2011-08-08 2013-02-18 에스케이하이닉스 주식회사 듀얼 레이어 구조의 반도체칩과 듀얼 레이어 구조의 반도체칩을 갖는 패키지들 및 그 제조방법
JP2013098186A (ja) * 2011-10-27 2013-05-20 Mitsubishi Heavy Ind Ltd 常温接合装置
CN104349892B (zh) * 2012-06-15 2017-06-09 三菱丽阳株式会社 层积体
KR20150032845A (ko) * 2012-06-15 2015-03-30 스미또모 가가꾸 가부시키가이샤 복합 기판의 제조 방법 및 복합 기판
US9837301B2 (en) * 2012-07-25 2017-12-05 Shin-Etsu Chemical Co., Ltd. Method for producing hybrid substrates, and hybrid substrate
CN102759816B (zh) * 2012-08-02 2015-09-09 深圳市华星光电技术有限公司 具有光伏电池的液晶显示模组的制作方法及其制得的液晶显示模组
JP6037734B2 (ja) * 2012-09-07 2016-12-07 三菱重工工作機械株式会社 常温接合装置および常温接合方法
JP6065176B2 (ja) * 2012-09-27 2017-01-25 三菱重工工作機械株式会社 常温接合装置および常温接合方法
JP5896038B2 (ja) * 2012-10-15 2016-03-30 信越化学工業株式会社 ナノカーボン膜の作製方法
JP2014107393A (ja) * 2012-11-27 2014-06-09 Mitsubishi Heavy Ind Ltd 常温接合デバイス、常温接合デバイスを有するウェハおよび常温接合方法
US9446467B2 (en) * 2013-03-14 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrate rinse module in hybrid bonding platform
US20150048509A1 (en) * 2013-08-16 2015-02-19 Globalfoundries Singapore Pte. Ltd. Cmos compatible wafer bonding layer and process
US9293303B2 (en) * 2013-08-30 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Low contamination chamber for surface activation
JP6330151B2 (ja) * 2013-09-17 2018-05-30 パナソニックIpマネジメント株式会社 半導体装置及びその製造方法
JP6212720B2 (ja) * 2013-09-20 2017-10-18 パナソニックIpマネジメント株式会社 半導体装置及びその製造方法
JP6082866B2 (ja) * 2013-09-27 2017-02-22 国立研究開発法人産業技術総合研究所 ステンレス鋼部材の接合方法およびステンレス鋼
JP2015115446A (ja) * 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) * 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
JP6125443B2 (ja) * 2014-01-17 2017-05-10 三菱重工工作機械株式会社 常温接合装置
US9478471B2 (en) * 2014-02-19 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for verification of bonding alignment
US9190345B1 (en) * 2014-03-28 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9257414B2 (en) * 2014-04-10 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor structure and method
US9455158B2 (en) * 2014-05-30 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect devices and methods of forming same
US9508685B2 (en) * 2014-07-29 2016-11-29 Empire Technology Development Llc Vertically integrated wafers with thermal dissipation
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
US9852988B2 (en) * 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10020336B2 (en) * 2015-12-28 2018-07-10 Semiconductor Energy Laboratory Co., Ltd. Imaging device and electronic device using three dimentional (3D) integration
JP2017139266A (ja) * 2016-02-01 2017-08-10 株式会社東芝 複合基板、半導体装置、およびこれらの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070128825A1 (en) * 2005-12-02 2007-06-07 Tadatomo Suga Method for bonding substrates and device for bonding substrates
CN102782850A (zh) * 2010-03-02 2012-11-14 美光科技公司 绝缘体上半导体金属结构、形成此些结构的方法及包含此些结构的半导体装置
CN103460339A (zh) * 2011-01-31 2013-12-18 须贺唯知 接合面制作方法、接合基板、基板接合方法、接合面制作装置以及基板接合体
JP2012238729A (ja) * 2011-05-12 2012-12-06 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法

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