CN107068674B - 一种面积高效的抗单粒子闩锁加固版图结构 - Google Patents

一种面积高效的抗单粒子闩锁加固版图结构 Download PDF

Info

Publication number
CN107068674B
CN107068674B CN201611244566.4A CN201611244566A CN107068674B CN 107068674 B CN107068674 B CN 107068674B CN 201611244566 A CN201611244566 A CN 201611244566A CN 107068674 B CN107068674 B CN 107068674B
Authority
CN
China
Prior art keywords
type mos
contact
substrate
trap
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611244566.4A
Other languages
English (en)
Other versions
CN107068674A (zh
Inventor
赵元富
王亮
刘家齐
岳素格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Microelectronic Technology Institute
Mxtronics Corp
Original Assignee
Beijing Microelectronic Technology Institute
Mxtronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Microelectronic Technology Institute, Mxtronics Corp filed Critical Beijing Microelectronic Technology Institute
Priority to CN201611244566.4A priority Critical patent/CN107068674B/zh
Publication of CN107068674A publication Critical patent/CN107068674A/zh
Application granted granted Critical
Publication of CN107068674B publication Critical patent/CN107068674B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种面积高效的抗单粒子闩锁加固版图结构，通过优化版图结构的设计，基于这种单元形成的集成电路，能够使用较小的面积开销解决单粒子效应引起的闩锁问题。N型MOS晶体管和P型MOS晶体管间形成叉指交错的阱、衬底结构，并通过阱上形成的阱接触、衬底上形成的衬底接触进行电荷收集，使得N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路。以较小的面积开销解决了单粒子效应引起的闩锁问题。

Description

一种面积高效的抗单粒子闩锁加固版图结构
技术领域
本发明属于半导体集成电路技术领域，尤其涉及一种面积高效的抗单粒子闩锁加固版图结构。
背景技术
单粒子效应是空间粒子，尤其是高能量粒子撞击半导体器件，产生瞬间的光电流所致。由于标准CMOS工艺下N型MOS晶体管和P型MOS晶体管间存在寄生的PNPN结构，单粒子效应能够导致半导体器件和电路产生闩锁问题，而且一旦发生闩锁，就有可能毁坏整个器件甚至电路。单粒子闩锁常用的加固方式是采用保护环结构，在N型MOS晶体管周围包围P衬底(或P阱)保护环、在P型MOS晶体管周围包围N阱(或N衬底)保护环。通过保护环进行电荷收集，使得N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路。
常用的抗单粒子闩锁加固结构如图2所示，版图结构100包括P衬底101，在衬底101上形成N阱102；在N阱102外的P型衬底101中形成N型MOS的有源区103，并在此有源区中形成N型MOS晶体管，N型MOS晶体管的源区(漏区)115和漏区(源区)116皆为N+注入层形成；在这个N型MOS晶体管的周围包围由P+注入层形成的P衬底保护环105，保护环105在P衬底101内，保护环105通过一些接触孔111与其它导电层连接；在N阱102中形成P型MOS的有源区104，并在此有源区中形成P型MOS晶体管，P型MOS晶体管的源区(漏区)113和漏区(源区)114皆为P+注入层形成；在这个P型MOS晶体管的周围包围由N+注入层形成的N阱保护环106，保护环106在N阱内，保护环106通过一些接触孔112与其它导电层连接；N型MOS栅107、P型MOS栅108通过接触孔110引出并通过金属109进行连接。
上述版图设计虽然能够有效抗单粒子闩锁，但是由于增加了保护环，其需要使用的面积开销很大，而限制了其使用。
发明内容
本发明的技术解决问题是：为克服现有技术的不足，提供一种面积高效的抗单粒子闩锁加固版图结构，以较小的面积开销解决了单粒子效应引起的闩锁问题。
为解决上述技术问题，本发明采用的技术方案包括：
一种面积高效的抗单粒子闩锁加固版图结构，包括P型衬底、N阱、N型MOS有源区、P型MOS有源区、P衬底接触、N阱接触、P型MOS栅、N型MOS栅、P衬底接触的接触孔和N阱接触的接触孔，
在衬底上形成N阱；在N阱外的P型衬底中形成N型MOS有源区，并在此有源区中形成N型MOS晶体管，N型MOS晶体管的源区和漏区皆为N+注入层形成，在N型MOS晶体管的源区和漏区中间位置淀积形成N型MOS栅；在N阱中形成P型MOS有源区，并在此有源区中形成P型MOS晶体管，P型MOS晶体管的源区和漏区皆为P+注入层形成，在P型MOS晶体管的源区和漏区中间位置淀积形成P型MOS栅；
在N型MOS晶体管靠近P型MOS晶体管的一侧由P+注入层形成多指型的P衬底接触，P衬底接触在多指型P型衬底内，P衬底接触通过P衬底接触的接触孔与其它导电层连接；
在P型MOS晶体管靠近N型MOS晶体管一侧由N+注入层形成多指型的N阱接触，N阱接触在多指型N阱内，N阱接触通过N阱接触的接触孔与其它导电层连接。
均为多指型的N阱接触、P衬底接触相互交错形成叉指结构。
N型MOS栅和P型MOS栅可采用多晶硅直接进行连接。
N阱接触和P衬底接触可在NMOS和PMOS间进行电荷收集，使N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路。
N阱接触和P衬底接触的形状为矩形、多边形、圆型或者椭圆中的任意一种。
P衬底接触和N阱接触的多指数量至少为两指。
版图结构的P型衬底可以换用N型衬底，在N型衬底上形成P阱、N型MOS有源区、P型MOS有源区、N衬底接触、P阱接触、N型MOS栅、P型MOS栅、N衬底接触的接触孔和P阱接触的接触孔。
本发明与现有技术相比的优点在于：
(1)本发明通过优化版图结构的设计，基于这种单元形成的集成电路，能够使用较小的面积开销解决单粒子效应引起的闩锁问题，N型MOS晶体管和P型MOS晶体管间形成叉指交错的阱、衬底结构相互交错，并通过阱上形成的阱接触、衬底上形成的衬底接触进行电荷收集，使得N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路，以较小的面积开销解决了单粒子效应引起的闩锁问题；
(2)本发明N型MOS栅和P型MOS栅可采用多晶硅直接进行连接，它们的连接可以不穿过P衬底接触和N阱接触，不用通过接触孔由金属层进行连接，简化了连接结构，可以直接实现连接；
(3)本发明可根据加固性能的要求和实际情况选择叉指的阱结构和衬底结构的多指数量和每指上阱接触和衬底接触的数量以达到不同闩锁加固性能要求。
附图说明
图1为本发明版图结构示意图；
图2为传统保护环加固的版图结构示意图。
具体实施方式
下面将结合附图对本发明做进一步详细的说明。
一种面积高效的抗单粒子闩锁加固版图结构，如图1所示，版图结构200包括P型衬底201、N阱202、N型MOS有源区203、P型MOS有源区204、P衬底接触205、N阱接触206、P型MOS栅209、N型MOS栅210、P衬底接触的接触孔207和N阱接触的接触孔208，
在衬底201上形成N阱202；在N阱202外的P型衬底201中形成N型MOS有源区203，并在此有源区中形成N型MOS晶体管，N型MOS晶体管的源区和漏区皆为N+注入层形成，在N型MOS晶体管的源区和漏区中间位置淀积形成N型MOS栅210；在N阱202中形成P型MOS有源区204，并在此有源区中形成P型MOS晶体管，P型MOS晶体管的源区和漏区皆为P+注入层形成，在P型MOS晶体管的源区和漏区中间位置淀积形成P型MOS栅209；
在N型MOS晶体管靠近P型MOS晶体管的一侧由P+注入层形成多指型的P衬底接触205，P衬底接触205在多指型P型衬底201内，P衬底接触205通过P衬底接触的接触孔207与其它导电层连接；
在P型MOS晶体管靠近N型MOS晶体管一侧由N+注入层形成多指型的N阱接触206，N阱接触206在多指型N阱202内，N阱接触206通过N阱接触的接触孔208与其它导电层连接，进而连接到适当电位上。
均为多指型的N阱接触206、P衬底接触205相互交错形成叉指结构，N型MOS栅210和P型MOS栅209可直接进行连接，N阱接触和P衬底接触可在NMOS和PMOS间进行电荷收集，使N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路，N阱接触和P衬底接触的形状为矩形、多边形、圆型或者椭圆中的任意一种。
上述版图结构的P型衬底201可以换用N型衬底，在N型衬底上形成P阱、N型MOS有源区、P型MOS有源区、N衬底接触、P阱接触、N型MOS栅、P型MOS栅、N衬底接触的接触孔和P阱接触的接触孔。
P型MOS晶体管和N型MOS晶体管的N阱接触(或N衬底接触)和P衬底接触(或P阱接触)位于两者之间，至少两指的N阱(或N衬底)和至少两指的P衬底(或P阱)结构相互交错形成叉指交错的阱、衬底结构。在多指结构的N阱(或N衬底)上通过N+注入层形成N阱接触(或N衬底接触)，在多指结构的P衬底(或P阱)上通过P+注入层形成P衬底接触(或P阱接触)。可根据加固性能的要求和实际情况选择叉指的阱结构和衬底结构的多指数量和每指上阱接触和衬底接触的数量以达到不同闩锁加固性能要求。
本发明通过优化版图结构的设计，基于这种单元形成的集成电路，能够使用较小的面积开销解决单粒子效应引起的闩锁问题。N型MOS晶体管和P型MOS晶体管间形成叉指交错的阱、衬底结构相互交错，并通过阱上形成的阱接触、衬底上形成的衬底接触进行电荷收集，使得N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路。以较小的面积开销解决了单粒子效应引起的闩锁问题。
本说明书中未详细描述的内容，是本领域技术人员公知常识。

Claims (6)

1.一种面积高效的抗单粒子闩锁加固单元版图结构，其特征在于，包括P型衬底(201)、N阱(202)、N型MOS有源区(203)、P型MOS有源区(204)、P衬底接触(205)、N阱接触(206)、P型MOS栅(209)、N型MOS栅(210)、P衬底接触的接触孔(207)和N阱接触的接触孔(208)，
在衬底(201)上形成N阱(202)；在N阱(202)外的P型衬底(201)中形成N型MOS有源区(203)，并在此有源区中形成N型MOS晶体管，N型MOS晶体管的源区和漏区皆为N+注入层形成，在N型MOS晶体管的源区和漏区中间位置淀积形成N型MOS栅(210)；在N阱(202)中形成P型MOS有源区(204)，并在此有源区中形成P型MOS晶体管，P型MOS晶体管的源区和漏区皆为P+注入层形成，在P型MOS晶体管的源区和漏区中间位置淀积形成P型MOS栅(209)；
在N型MOS晶体管靠近P型MOS晶体管的一侧由P+注入层形成多指型的P衬底接触(205)，P衬底接触(205)在多指型P型衬底(201)内，P衬底接触(205)通过P衬底接触的接触孔(207)与其它导电层连接；
在P型MOS晶体管靠近N型MOS晶体管一侧由N+注入层形成多指型的N阱接触(206)，N阱接触(206)在多指型N阱(202)内，N阱接触(206)通过N阱接触的接触孔(208)与其它导电层连接；
均为多指型的N阱接触(206)、P衬底接触(205)相互交错形成叉指结构。
2.如权利要求1所述的一种面积高效的抗单粒子闩锁加固单元版图结构，其特征在于，N型MOS栅(210)和P型MOS栅(209)可采用多晶硅直接进行连接。
3.如权利要求1所述的一种面积高效的抗单粒子闩锁加固单元版图结构，其特征在于，N阱接触和P衬底接触可在NMOS和PMOS间进行电荷收集，使N型MOS晶体管和P型MOS晶体管间寄生的PNPN结构不被高能粒子撞击所触发形成正反馈通路。
4.如权利要求1所述的一种面积高效的抗单粒子闩锁加固单元版图结构，其特征在于，N阱接触和P衬底接触的形状为矩形、多边形、圆型或者椭圆中的任意一种。
5.如权利要求1所述的一种面积高效的抗单粒子闩锁加固单元版图结构，其特征在于，P衬底接触(205)和N阱接触(206)的多指数量至少为两指。
6.如权利要求1所述的一种面积高效的抗单粒子闩锁加固单元版图结构，其特征在于，版图结构的P型衬底(201)可以换用N型衬底，在N型衬底上形成P阱、N型MOS有源区、P型MOS有源区、N衬底接触、P阱接触、N型MOS栅、P型MOS栅、N衬底接触的接触孔和P阱接触的接触孔。
CN201611244566.4A 2016-12-29 2016-12-29 一种面积高效的抗单粒子闩锁加固版图结构 Active CN107068674B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611244566.4A CN107068674B (zh) 2016-12-29 2016-12-29 一种面积高效的抗单粒子闩锁加固版图结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611244566.4A CN107068674B (zh) 2016-12-29 2016-12-29 一种面积高效的抗单粒子闩锁加固版图结构

Publications (2)

Publication Number Publication Date
CN107068674A CN107068674A (zh) 2017-08-18
CN107068674B true CN107068674B (zh) 2019-04-02

Family

ID=59623238

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611244566.4A Active CN107068674B (zh) 2016-12-29 2016-12-29 一种面积高效的抗单粒子闩锁加固版图结构

Country Status (1)

Country Link
CN (1) CN107068674B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110676252B (zh) * 2019-09-12 2022-05-13 北京时代民芯科技有限公司 一种抗瞬时辐射加固的集成电路版图结构
CN111009523B (zh) * 2019-10-08 2022-03-22 芯创智（北京）微电子有限公司 一种衬底隔离环的版图结构
CN112395823B (zh) * 2020-11-17 2022-08-16 湘潭大学 一种标准单元抗单粒子效应加固的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295224B1 (en) * 1999-12-30 2001-09-25 Stmicroelectronics, Inc. Circuit and method of fabricating a memory cell for a static random access memory
CN103545365A (zh) * 2012-07-12 2014-01-29 上海华虹Nec电子有限公司 用于静电保护的高压nldmos结构
KR20140122891A (ko) * 2013-04-11 2014-10-21 삼성전자주식회사 가드 밴드 및 가드 링을 포함하는 반도체 메모리 장치
WO2015037086A1 (ja) * 2013-09-11 2015-03-19 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339850A (zh) * 2010-07-19 2012-02-01 中国人民解放军国防科学技术大学 一种八边形网格状mosfet功率管版图结构
US9287253B2 (en) * 2011-11-04 2016-03-15 Synopsys, Inc. Method and apparatus for floating or applying voltage to a well of an integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295224B1 (en) * 1999-12-30 2001-09-25 Stmicroelectronics, Inc. Circuit and method of fabricating a memory cell for a static random access memory
CN103545365A (zh) * 2012-07-12 2014-01-29 上海华虹Nec电子有限公司 用于静电保护的高压nldmos结构
KR20140122891A (ko) * 2013-04-11 2014-10-21 삼성전자주식회사 가드 밴드 및 가드 링을 포함하는 반도체 메모리 장치
WO2015037086A1 (ja) * 2013-09-11 2015-03-19 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置

Also Published As

Publication number Publication date
CN107068674A (zh) 2017-08-18

Similar Documents

Publication Publication Date Title
US11735589B2 (en) S-contact for SOI
CN107068674B (zh) 一种面积高效的抗单粒子闩锁加固版图结构
CN101657900B (zh) 具有减小的触发电压的堆叠式静电放电保护电路
US9202696B2 (en) Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits
US20130092976A1 (en) A semiconductor power device integratred with improved gate source esd clamp diodes
CN105655325A (zh) 静电放电保护电路、结构及其制造方法
CN103258814A (zh) 一种集成电路芯片esd防护用ldmos scr器件
CN102956632A (zh) 一种低寄生电容的双向scr静电放电保护结构
US8866229B1 (en) Semiconductor structure for an electrostatic discharge protection circuit
CN102025135A (zh) 一种esd保护装置
CN107564901B (zh) 具有esd保护功能的ldmos器件及其版图
CN102034857B (zh) 一种pmos场效应晶体管辅助触发的双向可控硅
CN105489503B (zh) 半导体结构及其形成方法、静电保护电路
CN105633127B (zh) 一种超结mosfet
CN107039422A (zh) 一种集成电路esd全芯片防护电路
CN108258038A (zh) 神经元晶体管结构及其制备方法
CN108063134B (zh) 一种基于soi工艺的nmos器件及其构成的静电保护电路
CN102208455B (zh) 硅控整流器
CN104124275A (zh) 回形多叉指场效应晶体管及其制备方法
CN109742070A (zh) 一种fdsoi可控硅静电保护器件
CN106158744A (zh) 静电保护结构及其制作方法、芯片及其制作方法
Lin et al. 3D simulation of substrate noise coupling from through silicon via (TSV) and noise isolation methods
CN102693980A (zh) 一种低触发电压的可控硅静电放电保护结构
CN102315217B (zh) 多指条形ggnmos、静电保护电路
CN102244076B (zh) 一种用于射频集成电路的静电放电防护器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant