CN107039386A - 组装印刷电路板及引线架封装 - Google Patents
组装印刷电路板及引线架封装 Download PDFInfo
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Abstract
本发明公开一种组装印刷电路板及引线架封装。组装印刷电路板包括:印刷电路板,其包含芯板、设置在所述印刷电路板的第一面上的多个导电布线、以及设置在所述印刷电路板的第二面上的接地层,其中所述多个导电布线包含一对差动信号布线;中介基准布线,设置在所述对差动信号布线之间;连接器,设置在所述多个导电布线的一端;以及半导体封装,装设在所述多个导电布线的另一端。本发明所公开的组装印刷电路板及引线架封装,可以提高电路设计的效能。
Description
技术领域
本发明有关于一种印刷电路板,特别是有关于一种组装印刷电路板及引线架封装。
背景技术
如本领域技术人员所周知,半导体集成电路(integrated circuit,IC)芯片会具有输入/出(I/O)接垫连接至外部电路,以成为电子系统中的一部分,其连接媒介(connection media)可为引线架(leadframe)等金属导线阵列,或是球闸阵列(ball gridarray,BGA)基板等支撑性电路结构。打线接合(wire bonding)与覆晶接合(flip-chipbonding)是其中两种广为使用的接合技术。就打线接合的作法来说,导线会通过超声波(ultrasonic)或热压工序(thermocompression process)从芯片上一条一条的接合到外部电路上。打线接合期间一般会施加压力等机械力或是超声波震动等波冲(burst),再加上升温动作来达成导线(wire)或凸块与预定接合面之间的冶金熔接(metallurgicalwelding)。
覆晶接合则牵涉到在接垫上设置预先形成的焊锡凸块,接着将芯片翻面使得接垫那一面朝下并与接合位置上对应的接触点对齐,之后焊锡凸块会被熔化以润湿接垫与接合处。经过锡回焊步骤后,焊锡凸块会被冷却固化形成接垫与接合处之间的焊锡接点。覆晶接合相较于打线接合,其主要优点在于芯片与外部电路之间的连接路径较短,因此会具有较佳的电性,如较低的电感噪声(inductive noise)、串音(cross-talk),以及较少发生传播延迟(propagation delay)以及波形失真(waveform distortion)等问题。
引线架通常会含有多条金属引线(lead),其在封装制作期间会受到一个矩形框架的固定而沿着中央区域的周边平面排列,晶粒接垫(die pad)在所述中央区域上则会受到连接在所述矩形框架上的多条连接杆(tie bar)的支撑。引线会从与框架连接的第一端延伸至邻近的相对的第二端,但是会与晶粒接垫隔开。封装期间,半导体晶粒会粘接至晶粒接垫。之后晶粒上用来打线接合的接垫会以纤细、具有导电性的接线(bonding wire)连接至其中一个所选的内引线(inner lead),以在晶粒与引线之间传递电力、信号或是接地等。整个封装体上会模塑(mold)上环氧树脂保护体,以包覆并密封所述晶粒、内引线、以及接线等,使其与外在有害的因素隔绝。上述的矩形框架以及引线的外端会暴露在保护体的外头,在模塑后,框架会从引线上剪下(cut away)并丢弃,如此便可形成适当的引线外端使封装体得以与外部的印刷电路板互连。
半导体芯片的输入/出单元可以生成或接收高速的输入/出信号,并可从封装终端传送或接收信号。此高速输入/出信号会行经(travel)可维持信号保真度(signalfidelity)的传输线一段距离。信号完整度(signal integrity)是电子信号的一组品质量测。不论在电子封装与组装的哪个层级(level),如从IC的内部连接,到封装、印刷电路板、背板(backplane)、以及系统间连接,信号完整度工程都是其间重要的一环。在130奈米(0.13μm)及以下的奈米技术中,信号之间非预期的互动(如串音)已然成为了数字电路设计中的重要考量。就这样的技术环节,为了电路设计的效能以及其信号正确性,无法不考虑噪声在其间的影响。
信号完整度的问题主要来自于串音,其主要起因在于耦合电容(couplingcapacitance),但大体来说其是由互感(mutual inductance)、基材偶合(substratecoupling)、非理想的闸极操作(non-ideal gate operation)、以及其他因素造成。其解法一般会涉及到改变驱动器的尺寸及/或隔开导线等。在数字IC中,关键信号(signal ofinterest)中的噪声主要是由其他信号切换时的耦合作用引起。增加的互连密度(interconnect density)会使导线彼此之间更靠近,导致相邻网络间的耦合电容增加。较大的互容(mutual capacitance)与互感亦会引起较大的共模阻抗与较小的差动阻抗。信号反射(signal reflection)亦会因为阻抗不匹配的缘故造成信号完整度下降。
根据莫尔定律(Moore's law),随着电路不断的缩小,噪声问题会因为某些效应的产生而变得更糟。举例来说,为了维持电阻的容受度(tolerable)但又不减少线宽,现在的导线尺寸会比他们彼此之间的间距还大。这无疑是以接地电容换来侧壁电容(sidewallcapacitance)的增加,也因此增加了感应出的噪声电压(induced noise voltage)。这样的效应会使得信号间的互动增加并降低数字电路的抗扰性,以至于噪声变成了数字IC与高速信号传输应用的重要问题。
因为阻抗匹配需要低阻抗之故,印刷电路板的信号布线(signal trace)会携带比芯片上更多的电流。这样较多的电流主要会引起磁模式(magnetic mode)或是电感式(inductive mode)的串音,而非电容式的串音。信号本身与其回归的信号路径都能够生成电感串音。尽管差动布线对(differential trace pair)有助于减少这些效应,在某些情况下其仍有缺点待克服。举例来说,在引线架封装或是双层PCB电路板中,缺乏基准面(如电力面(power plane)或接地面(ground plane))会引起较大的互感与互容,其复会造成较小的差动阻抗(Zdiff)与较大的共模阻抗(Zcom),这些都是高速信号传输应用等所不乐见的,如资料经兼容移动高清链接(Mobile High-Definition Link,MHL)规格的接口传输。
发明内容
有鉴于此,本发明提供一种组装印刷电路板和引线架封装。
依据本发明一实施方式,提供一种组装印刷电路板,包括:印刷电路板,其包含芯板、设置在所述印刷电路板的第一面上的多个导电布线、以及设置在所述印刷电路板的第二面上的接地层,其中所述多个导电布线包含一对差动信号布线;中介基准布线,设置在所述对差动信号布线之间;连接器,设置在所述多个导电布线的一端;以及半导体封装,装设在所述多个导电布线的另一端。
依据本发明另一实施方式,提供一种引线架封装,包括:一种引线架封装,其特征在于,包含:晶粒接垫;半导体晶粒,装设在所述晶粒接垫上;多条引线,沿着所述晶粒接垫的周边设置在第一水平面上,其中所述多条引线中的每一条包含裸露引线以及内嵌且半蚀刻的内引线,所述内引线接合在所述裸露引线上;中介基准引线,介于所述多条引线中的两条引线之间,所述两条引线为相邻且连续的高速信号引线;多条连接杆,从所述晶粒接垫向外延伸;多条第一接线,分别将所述半导体晶粒电连接至所述多条引线;以及模塑材料,其至少密封住所述半导体晶粒、所述多条第一接线、所述多条引线、所述多条连接杆、以及所述晶粒接垫,其中所述裸露引线与所述晶粒接垫从所述模塑材料的底面中裸露而出。
依据本发明又一实施方式,提供一种引线架封装,包括:晶粒接垫;半导体晶粒,装设在所述晶粒接垫上;多条引线,沿着所述晶粒接垫的周边设置在第一水平面上,其中所述多条引线中的每一条至少包含内引线与外引线;多条连接杆,从所述晶粒接垫向外延伸;多条接线,分别将所述半导体晶粒电连接至所述多条引线;模塑材料,密封住所述半导体晶粒、所述多条接线、所述多条内引线、所述多条连接杆、以及所述晶粒接垫,其中所述晶粒接垫从所述模塑材料的底面中裸露而出;以及延伸金属层,设置在所述引线架封装的底面上。
依据本发明又一实施方式,提供一种引线架封装,包括:晶粒接垫;半导体晶粒,装设在所述晶粒接垫上;多条引线,沿着所述晶粒接垫的周边设置在第一水平面上,其中所述多条引线中的每一条至少包含内引线与外引线;引线固定胶带,跨粘在所述晶粒接垫的周边的所述多条内引线上;金属层,设置在所述引线固定胶带上;接地排,从所述第一水平面下延至第二水平面并经由下延的桥接部连接至所述晶粒接垫;多条连接杆,从所述晶粒接垫的四个角落向外延伸;多条第一接线,分别将所述半导体晶粒电连接至所述多条内引线;以及模塑材料,至少密封住所述半导体晶粒、所述多条第一接线、所述多条内引线、所述引线固定胶带、所述金属层、所述接地排、所述多条连接杆、以及所述晶粒接垫,其中所述晶粒接垫从所述模塑材料的底面中裸露而出。
本发明所提供的组装印刷电路板和引线架封装,可以提高电路设计的效能。
对于已经阅读后续由各附图及内容所显示的较佳实施方式的本领域的技术人员来说,本发明的各目的是明显的。
附图说明
图1A为一接口装置(如HDMI装置)的双层PCB板的部分平面图;
图1B为沿图1A中I-I’所作的剖视图;
图1C与图1D分别为相关的差动布线的对应的端部的放大图;
图2为具有GSGSG架构的PCB板的剖视图,其中的中介基准布线(interveningreference trace)并不与邻近的高速导电布线(high-speed conductive trace)共平面;
图3为使用SGS布线架构或是GSGSG布线架构的双层TFBGA封装基板的实施例的剖视图;
图4A为E-pad引线架封装相关部位的部分俯视图;
图4B为引线架封装的部分剖视图;
图4C与图4D为引线架封装中SGS引线架构的剖视图;
图5A至图5C描绘出多种根据本发明实施例的引线架封装形式;
图6为E-pad引线架封装的剖视图,其底面与下延的内引线上具有额外的接地层;
图7A为附有引线固定胶带的额外导电层的部分俯视图;
图7B为图7A引线架封装中的额外接地层与引线固定胶带的相对位置的部分截面图;以及
图7C为用来将引线固定胶带上方的金属层电连接至连接杆或接地排(groundbar)的接线的放大图。
具体实施方式
在权利要求书及说明书中使用了某些词汇来指称特定的组件。所属领域中的技术人员应可理解,硬件制造商可能会用不同的名词来称呼同样的组件。本权利要求书及说明书并不以名称的差异来作为区分组件的方式,而是以组件在功能上的差异来作为区分的准则。在权利要求书及说明书中所提及的「包括」为开放式的用语,故应解释成「包括但不限定于」。另外,「耦接」一词在此包括任何直接及间接的电气连接手段。因此,若文中描述第一装置耦接于第二装置,则代表所述第一装置可直接电连接于所述第二装置,或通过其他装置或连接手段间接地电连接至所述第二装置。
现在文中将参照附图来说明本发明的一或多个实施例,通篇说明书中会使用相同的元件符号来代表相同的元件,且其中所描绘的结构并不一定是依照实际的尺度比例来绘示。
本发明属于一种改良后的传输通道结构,例如,其可同时传输差动信号与共模信号,适合用在兼容移动高清链接(Mobile High-Definition Link,MHL)规格的资料传输接口等高速信号传输应用当中。本发明会以多种形式来体现,例如在印刷电路板(PCB)、组装印刷电路板(PCB assembly,PCBA)、引线架等芯片封装结构(chip package)、或任何牵涉到集聚式(crowded)或成对式(paired)的高速或高频布线(在PCB板中)或引线(在封装结构中)的信号传输通道或连接器/装置,如PCB板中成对的MHL+与MHL-差动信号布线。
MHL是一种高清视频与数字音频接口的规格,用来将移动电话与可携式装置连接到高清电视机(HDTVs)或其他家庭娱乐产品。它采用定制的连接器,并设有单条具有5脚位接口的信号线,支持1080p HD视频与数字音频,并可同时供电到移动装置。它也让使用者可使用TV遥控器来控制手机并存取其中的内容。
为了符合高速信号传输应用中的MHL规格,MHL规格的接口装置中一般都会需要用到昂贵的四层(4-layer)PCB板及/或BGA封装基板。在本发明中,通过采用创新的SGS或GSGSG通道电路设计,差动阻抗(Zdiff)与共模阻抗(Zcom)皆可符合MHL规格,其中Zdiff值接近100Ω(±15Ω)而Zcom值接近30Ω(±6Ω),这样的数值表现使用一般划算(cost-effective)的双层PCB板就可达到,且不会牺牲双层PCB板上的绕线空间(routing space)。然而,须注意本发明也可应用在多层印刷电路板上。
下文中将以「双层PCB板」一词来指称那些芯板(core substrate)两侧分别仅具有一层导电布线的PCB板,而「PCBA」一词则用来指称那些设有至少一个电子元件(例如装设在PCB板元件侧的芯片或封装结构)的组装后PCB板。「SGS」一词指的是一种电路布局结构,其包含中介基准(intervening reference)布线或引线夹设在一对以大于1Gb/s的速度运作的高速/高频信号布线或引线之间。「GSGSG」指的也是一种电路布局结构,其包含前述的SGS布局结构以及一对接地保护线设在所述SGS图形的两边。
现在请参照图1A至图1D。图1A为一接口装置(如高清多媒体接口(High-Definition Multimedia Interface,HDMI)装置)的双层PCB板的部分平面图。图1B为以图1A中I-I’所作的剖视图。图1C与1D则分别为相关的差动布线的对应的端部(respectiveend portions)的放大图。首先,如图1A与图1B所示,组装后的PCB板1包含了双层PCB板10,其具有两个相对(opposite)的表面10a与10b。双层PCB板10可包含一个以绝缘材料制成的芯板100。芯板100的厚度C约大于20密耳(mils),如30~70mils。表面10a上设有多条导电布线11,如HDMI汇流排线(bus line)以及其它的信号传输线。根据一实施例,表面10b上则设有至少一接地层或接地面(ground layer or ground plane)120。导电布线11包含(但不限定)一对差动信号布线110a与110b,其夹设在一对接地保护线(ground guard line)112a与112b之间,接地保护线112a与差动信号布线110a之间以及接地保护线112b与差动信号布线110b之间有间隔GS1。差动信号布线110a与110b之间设有中介基准布线(interveningreference trace)114,其中中介基准布线114与差动信号布线110a之间以及中介基准布线114与差动信号布线110b之间有间隔GS2。表面10a上可涂布上一层防焊层130以盖住导电布线11。根据本发明一实施例,导电布线11的厚度T约为1.34mils,位于布线11正上方的防焊层130厚度H约为0.4mils,而成对的差动信号布线110a与110b的长度可大于或等于2毫米(millimeter,mm)。
根据本发明一实施例,接地保护线112a与112b的线宽GW1都约为20mils,差动信号布线110a与110b的线宽W都约为20mils,而中介基准布线114的线宽GW2则约大于或等于3mils,如5mils。根据本发明一实施例,间距GS1约为6mils,间距GS2约为4mils。通道跨距D定义为差动信号布线110a与110b的线宽W加上中介基准布线114的线宽GW2、中介基准布线114与差动信号布线110a之间以及中介基准布线114与差动信号布线110b之间的间距GS2。举例来说,根据本发明一实施例,通道跨距D约为53mils(D=2×W+GW2+2×GS2)。以如此独特的SGS(或GSGSG)设定,本发明可达到约89Ω的模拟Zdiff值/27Ω的模拟Zcom值(使用ANSYSQ2D的双层PCB板的阻抗模拟,其中ANSYS Q2D为ANSYS公司开发出来的以二维方式来模拟结构体的阻抗)。
如图1A和1C所示,组装后的PCB板1还可包含连接器区域(connector region)20。连接器区域20中设有HDMI连接器,其具有对应的连接垫或接脚202a与202b来电耦合差动信号布线110a与110b。此外,连接垫202a与差动信号布线110a之间以及连接垫202b与差动信号布线110b之间可分别增设串联电阻(series resistor,Rs)116a与116b,或是其他的静电放电保护元件。假如串联电阻116a与116b均为13Ω,则Zdiff与Zcom会分别约为115Ω与33.5Ω,其阻抗仍符合MHL规格。根据本发明一实施例,串联电阻116a与116b均为6Ω的电阻,如此Zdiff与Zcom约分别为101Ω与30Ω。从图1C可以清楚的看到,中介基准布线114经由位于连接器区域20附近的导电通孔114b电连接至对侧表面10b上的接地面120。然而,阅者须了解到在其它实施例中,中介基准布线114也可连接到电力面。或者,中介基准布线114可连接到连接器区域20中的HDMI连接器的接地脚位或是电力脚位。
如图1A和1D所示,组装后的PCB板1还可包含芯片封装装设区域30位于导电布线11的另一端上。在芯片封装装设区域30中,芯片封装结构(未具体示出)可装设在PCB板10的表面10a或表面10b上,并经由多个接合处、接垫302、或是镀通孔(plated through hole)(未示出)等部位电耦合至PCB板10上对应的布线11。芯片封装的细部结构将在后文中进行说明。从图1D可以清楚的看到,差动信号布线110a与110b会伸入芯片封装装设区30以连接对应的接合处或接垫302a与302b。中介基准布线114可结束于芯片封装装设区域30之外。然而,须了解到中介基准布线114也可伸入芯片封装装设区域30,以连接那些对应的接地引线或电力引线的接垫或是芯片封装的脚位或锡球。
在图1A至1D中,中介基准布线114会与邻近PCB板10表面10a上包含差动信号布线110a与110b的导电布线11共平面。然而阅者须了解到,在其它实施例中,中介基准布线114也可能不会与邻近的导电布线11共平面。如图2所示,根据本发明另一实施例,中介基准布线114会直接设置在防焊层130顶面。举例来说,中介基准布线114可由银胶(silverpaste)、石墨(graphite)等导电材料构成,并可以印刷、涂布、或任何合适的方式形成。上层的中介基准布线114可电耦合至电力或接地网络。以通道跨距D约为24mils(W为8mils;S为8mils,其中S定义为差动信号布线110a与110b之间的间距)、GS为6mils、以及GW2为5mils这样的设定,本发明可达成约93Ω的模拟Zdiff值/29Ω的模拟Zcom值。
前文中说明的SGS或GSGSG设定可应用在BGA或是双层薄形微节距式BGA(thinfine-pitch BGA,TFBGA)封装板上。如图3所示,根据本发明又一实施例,BGA或双层TFBGA封装板10’同样会包含一个以绝缘材料制成的芯板100。芯板100的厚度C可为150~600μm,如250μm。表面10a(或称为元件侧)上设有多个导电布线11。根据本发明一实施例,对侧的表面10b(或称为锡球侧)上设有至少一接地层或接地面120。表面10b上可设置有多个BGA锡球接垫(未示出)。导电布线11包含(但不限定)一对差动信号布线110a与110b,其夹设在一对接地保护线112a与112b之间,接地保护线112a与差动信号布线110a之间以及接地保护线112b与差动信号布线110b之间有间隔GS1。差动信号布线110a与110b之间设有中介基准布线114,其中中介基准布线114与差动信号布线110a之间以及中介基准布线114与差动信号布线110b之间有间隔GS2。表面10a上可涂布上一层防焊层130以盖住导电布线11。根据本发明一实施例,导电布线11的厚度T约为20μm,位于布线11正上方的防焊层130厚度H约为30μm。以通道跨距D约为250μm(W=GS2=GW2=50μm)、GS1为50μm、以及GW1为50μm,本发明可达成约98Ω的模拟Zdiff值/27Ω的模拟Zcom值。相较于现有的双层TFBGA封装板,本发明所提出的双层TFBGA封装板10'中的GSGSG图形设计,其由于通道跨距D(D=2×W+GW2+2×GS2)较小,因此会占用较少的绕线区域。
前文中所讨论的SGS设定可应用在裸露式晶粒接垫(die pad,后文中称为E-pad)等引线架封装中。E-pad引线架封装会将其晶粒接垫的底面裸露出封装体外,其可作为散热片(heat sink)来改善散热效率。一般来说,E-pad会电连接至外部的PCB板或主机板的接地面。在其他方面,E-pad式的薄型四方平坦封装(low-profile quad flat package,LQFP)也被认为是多媒体芯片的低成本解决方案。
现在请参照图4A至4D。图4A为E-pad引线架封装300的相关部位(germaneportion)的部分顶视图。图4B为引线架封装300的部分截面图。图4C与4D为所述引线架封装中SGS引线设定的剖视图。如图4A与4B所示,E-pad引线架封装300包含半导体晶粒320、多条引线310以及接地排(ground bar)303,半导体晶粒320装设在金属引线架的晶粒接垫302上,多条引线310沿着晶粒接垫302的周边(peripheral edges)设置在第一水平面上,接地排303从所述第一水平面经由桥接部305下延并连接至第二水平面上的晶粒接垫。此处以四条连接杆(tie bar)为例(但不限定),四条连接杆304会从晶粒接垫302的四个角落向外延伸(图中仅为连接杆)。为简洁起见,图4A中仅为部分位于相邻连接杆之间的部分区域(sector region)中的引线310。
E-pad引线架封装300还包含多条接线330用来将半导体晶粒320电连接至引线310,以及多条接线340用来将接地排303电连接至半导体晶粒320上对应的接地接垫(图中未明确示出)。模塑材料或模塑体350会至少包覆住半导体晶粒320、接线330与340、引线310中的内引线310’、接地排303、连接杆304、以及部分的晶粒接垫302,且晶粒接垫302的底面会裸露出模塑材料350的底面。内引线310’是每条引线310嵌在模塑材料350中的部分,其长度为L。外引线310”是每条引线310从模塑材350料边缘伸出的部分。
从图4A中可以清楚的看到,根据本发明一实施例,E-pad引线架封装300还包含基准内引线(reference inner lead)314介于两相邻且连续的、以高于1Gb/s的速度运作的高速信号引线310a与310b之间。高速信号引线310a与310b系分别经由接线330a与330b电连接至半导体晶粒320上对应的信号接垫。基准内引线314可经由接线330c电连接至半导体晶粒320上对应的接地接垫或电力接垫。为了达到较佳的阻抗控制,基准内引线314的长度最好大于或等于高速信号引线310a与310b中的内引线长度L的三分之一(L为引线310a/310b的内引线长度)。
如图4C所示,图中为引线架封装中SGS图形的尺寸范例。基准内引线314系位于高速信号引线310a与310b之间,基准内引线314的线宽为GW,基准内引线314与引线310a之间以及基准内引线314与引线310b之间的间距为GS。信号引线310/310a/310b的线宽与厚度分别为W与T。举例来说,线宽GW与W可为75μm,而间距GS可为100μm。如此引线跨距D’会约为425μm(D’=2×W+GW+2×GS)。以通道跨距D约为425μm(W=GW=75μm;GS=100μm;T=0.127mm)这样的设定,本发明可达到约91Ω的模拟Zdiff值/28Ω的模拟Zcom值。
如图4D所示,根据本发明另一实施例,基准内引线314并不与引线310以及高速信号引线310a与310b共平面。基准内引线314可设置在晶粒接垫周边跨设在多条引线310上的引线固定胶带(lead-lock tape)410上。基准内引线314可由铜、银胶、或石墨等导电碳材构成,并可以印刷、涂覆、电镀或任何合适的方式来形成。上层的基准引线314可电耦合至电力或接地网络。以W为75μm、S为100μm(其中S为高速信号引线310a与310b之间的间距)、GW为160μm、H为50μm(H是引线固定胶带410的厚度)这样的设定,本发明可达到约31.6Ω的模拟Zcom值。
尽管图中仅为E-pad引线架封装,阅者须了解到本发明并未局限在这样的应用。举例来说,本发明也可应用在非裸露式接垫的引线架封装设计中。
图5A至5C为多种根据本发明实施例的引线架封装形式。如图5A所示,基准内引线314更经由下延的桥接部314a向内延伸至与接地排303接合。因此,基准内引线314与接地排303都是接地的。此例中并不需要接线来将基准内引线314连接至半导体晶粒。
如图5B所示,基准内引线314更向内延伸与杆部314b接合,经由至少两个桥接部314a来与接地排303接合。两桥接部提供了不错的支撑性。或者,在其他实施例中,基准内引线314可横向延伸至与连接杆304接合。图5C为前文中所讨论具有SGS图形的四方平坦无引线(quad-flat non-leaded,QFN)封装50的底部布局范例。
如图5C所示,QFN封装50包含多条引线510、四个连接杆540、以及至少一中介基准引线514a,引线510包含沿着E-pad 520的四个周边设置的多条裸露引线511、多条内嵌半蚀刻的内引线512,内引线512接在相应的裸露引线511上,中介基准引线514a介于两邻近且连续的、以高于1Gb/s速度运作的高速引线510a与510b之间。每条内嵌半蚀刻的内引线512都会从裸露引线511的一端延伸到靠近晶粒接垫520的另一端,但内引线512与晶粒接垫520之间间隔一段距离。如同内引线512,中介基准引线514a也是半蚀刻嵌入模塑材料550中。中介基准引线514a可与晶粒接垫520一体成形并延伸至封装体边缘。根据本发明另一实施例,其中提供了一种具有外端从封装体边缘拉回或切断的中介基准引线514b。或者,QFN封装50上可设有内端与晶粒接垫520间隔开的中介基准引线514c。在此例中,中介基准引线514b与中介基准引线514c可通过使用接线(未示出)电连接至晶粒接垫。
为了进一步减少引线的共模阻抗,可将引线架封装的E-pad延伸额外的接地层。如图6所示,引线架封装60包含多条引线610,其包含设置在晶粒接垫602周边的第一水平面上长度为L的内引线610’、以及从模塑材料650外下弯的外引线610”。半导体芯片620装设在晶粒接垫602上并被模塑材料650密封。引线架封装60还包含接地排603从所述第一水平面下延至第二水平面。多条接线630用来将内引线610’电连接至半导体晶粒620上对应的输入/出接垫(未示出),其中至少有接线640用来将接地排603电连接至半导体晶粒620的接地接垫(未示出)。引线架封装60的底面上设有延伸的金属层660,其与晶粒接垫602互相接触。金属层660可由铜、银胶、或石墨等导电碳材构成,并可使用印刷、涂覆、电镀、溅镀或任何适合的方式来形成。因此,延伸的金属层660与晶粒接垫602可具有相同的电压层级,如接地层级。至少一内引线610a(如以高于1Gb/s速度运作的高速或高频引线)会从第一水平面下压并延伸至第二水平面,使得下延的内引线610a与延伸的金属层660之间的距离H可小于0.5mm。在较佳的情况下,下延的内引线610a的长度L’最好大于或等于长度L的三分之一。
引线架封装可设有额外的接地面并嵌入模塑材料中。同样地,如第7A与7B图所示,引线架封装70包含多条引线710,引线710设置在由连接杆704所支撑的晶粒接垫702周边的第一水平面上。在某些例子中,每条引线710可包含至少一内引线711与外引线712。半导体芯片720装设在晶粒接垫702上并为模塑材料750所密封。引线架封装70还包含接地排703从第一水平面下延至第二水平面。多条接线730用来将内引线711电连接至半导体晶粒720上对应的输入/出接垫(未示出),其中至少一接线740是用来将接地排703电连接至半导体晶粒720的接地接垫(未示出)。引线固定胶带762跨黏在晶粒接垫702周边多条的内引线711上。引线固定胶带762上设置有金属层764,且其中至少一接线736是用来将金属层764电连接至半导体晶粒720中的接地网络。在图7A中,金属层764大致呈方形,与此区间中以高于1Gb/s速度运作的高速或高频内引线710a与710b相互重叠。在较佳的情况下,至少三分之一长度的内引线会为金属层764所覆盖。再者,阅者须了解到金属层764可使用多种作法连接至接地区域。举例来说,金属层764可使用接线、跳线、连接片、含金属成分的环氧树脂等连接至连接杆,或是打线接合至接地排或接地引线等。金属层764可为固态金属、网状金属、或复合金属。再者,引线固定胶带762可含有通孔来增加模固强度。如图7C所示,接线736系用来将引线固定胶带上方的金属层764电连接至连接杆704或接地排703。在较佳的情况下,接线736会在内引线正上方的位置处与金属层764接合。
以上所述仅为本发明的较佳实施方式,凡依本发明权利要求所做的均等变化和修饰,均应属本发明的涵盖范围。
Claims (28)
1.一种组装印刷电路板,其特征在于,包括:
印刷电路板,其包含芯板、设置在所述印刷电路板的第一面上的多个导电布线、以及设置在所述印刷电路板的第二面上的接地层,其中所述多个导电布线包含一对差动信号布线;
中介基准布线,设置在所述对差动信号布线之间;
连接器,设置在所述多个导电布线的一端;以及
半导体封装,装设在所述多个导电布线的另一端。
2.如权利要求1所述的组装印刷电路板,其特征在于,所述差动信号布线设置在一对接地保护线之间。
3.如权利要求1所述的组装印刷电路板,其特征在于,所述中介基准布线与所述差动信号布线共平面。
4.如权利要求1所述的组装印刷电路板,其特征在于,所述中介基准布线不与所述对差动信号布线共平面。
5.如权利要求4所述的组装印刷电路板,其特征在于,所述中介基准布线设置在覆盖所述多个导电布线与所述第一面的防焊层的顶面上。
6.如权利要求1所述的组装印刷电路板,其特征在于,所述印刷电路板是双层印刷电路板。
7.如权利要求1所述的组装印刷电路板,其特征在于,所述芯板的厚度大于20mils。
8.如权利要求1所述的组装印刷电路板,其特征在于,所述多个导电布线包含高清多媒体接口汇流排线。
9.如权利要求1所述的组装印刷电路板,其特征在于,所述连接器是高清多媒体接口连接器。
10.如权利要求1所述的组装印刷电路板,其特征在于,静电放电保护元件串联至所述差动信号布线。
11.如权利要求10所述的组装印刷电路板,其特征在于,所述静电放电保护元件包含串联电阻。
12.如权利要求11所述的组装印刷电路板,其特征在于,所述串联电阻的电阻值小于15Ω。
13.如权利要求1所述的组装印刷电路板,其特征在于,所述中介基准布线的线宽大于或等于3mils。
14.如权利要求1所述的组装印刷电路板,其特征在于,所述中介基准布线的至少一端会接地或通电。
15.一种引线架封装,其特征在于,包含:
晶粒接垫;
半导体晶粒,装设在所述晶粒接垫上;
多条引线,沿着所述晶粒接垫的周边设置在第一水平面上,其中所述多条引线中的每一条包含裸露引线以及内嵌且半蚀刻的内引线,所述内引线接合在所述裸露引线上;
中介基准引线,介于所述多条引线中的两条引线之间,所述两条引线为相邻且连续的高速信号引线;
多条连接杆,从所述晶粒接垫向外延伸;
多条第一接线,分别将所述半导体晶粒电连接至所述多条引线;以及
模塑材料,其至少密封住所述半导体晶粒、所述多条第一接线、所述多条引线、所述多条连接杆、以及所述晶粒接垫,其中所述裸露引线与所述晶粒接垫从所述模塑材料的底面中裸露而出。
16.如权利要求15所述的引线架封装,其特征在于,所述引线架封装是一种四方平坦无引线封装。
17.如权利要求15所述的引线架封装,其特征在于,所述中介基准引线为半蚀刻并嵌入所述模塑材料内。
18.如权利要求15所述的引线架封装,其特征在于,所述中介基准引线与所述晶粒接垫一体成形。
19.如权利要求15所述的引线架封装,其特征在于,所述中介基准引线具有内端,所述内端与所述晶粒接垫间隔开,且所述中介基准引线使用第二接线电连接至所述晶粒接垫。
20.一种引线架封装,其特征在于,包含:
晶粒接垫;
半导体晶粒,装设在所述晶粒接垫上;
多条引线,沿着所述晶粒接垫的周边设置在第一水平面上,其中所述多条引线中的每一条至少包含内引线与外引线;
多条连接杆,从所述晶粒接垫向外延伸;
多条接线,分别将所述半导体晶粒电连接至所述多条引线;
模塑材料,密封住所述半导体晶粒、所述多条接线、所述多条内引线、所述多条连接杆、以及所述晶粒接垫,其中所述晶粒接垫从所述模塑材料的底面中裸露而出;以及
延伸金属层,设置在所述引线架封装的底面上。
21.如权利要求20所述的引线架封装,其特征在于,所述金属层与所述晶粒接垫相接触。
22.如权利要求20所述的引线架封装,其特征在于,位于所述延伸金属层正上方的至少一条所述内引线被下压并从所述第一水平面下延至第二水平面,使得所述内引线比其他所述多条内引线距离所述延伸金属层更近。
23.如权利要求20所述的引线架封装,其特征在于,下压的所述内引线与所述延伸金属层之间的距离小于0.5mm。
24.一种引线架封装,其特征在于,包含:
晶粒接垫;
半导体晶粒,装设在所述晶粒接垫上;
多条引线,沿着所述晶粒接垫的周边设置在第一水平面上,其中所述多条引线中的每一条至少包含内引线与外引线;
引线固定胶带,跨粘在所述晶粒接垫的周边的所述多条内引线上;
金属层,设置在所述引线固定胶带上;
接地排,从所述第一水平面下延至第二水平面并经由下延的桥接部连接至所述晶粒接垫;
多条连接杆,从所述晶粒接垫的四个角落向外延伸;
多条第一接线,分别将所述半导体晶粒电连接至所述多条内引线;以及
模塑材料,至少密封住所述半导体晶粒、所述多条第一接线、所述多条内引线、所述引线固定胶带、所述金属层、所述接地排、所述多条连接杆、以及所述晶粒接垫,其中所述晶粒接垫从所述模塑材料的底面中裸露而出。
25.如权利要求24所述的引线架封装,其特征在于,还包含至少一第二接线,所述第二接线将所述金属层电连接至所述半导体晶粒中的接地网络。
26.如权利要求24所述的引线架封装,其特征在于,所述金属层呈扇形且与所述多条引线中的高速或高频内引线重叠。
27.如权利要求26所述的引线架封装,其特征在于,所述金属层至少覆盖住所述内引线三分之一的长度。
28.如权利要求24所述的引线架封装,其特征在于,还包含至少一第三接线,所述将第三接线所述金属层电连接至所述接地排。
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US9269653B2 (en) | 2016-02-23 |
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US20160120034A1 (en) | 2016-04-28 |
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