CN107017203B - 半导体元件的制造方法 - Google Patents
半导体元件的制造方法 Download PDFInfo
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- CN107017203B CN107017203B CN201610993734.3A CN201610993734A CN107017203B CN 107017203 B CN107017203 B CN 107017203B CN 201610993734 A CN201610993734 A CN 201610993734A CN 107017203 B CN107017203 B CN 107017203B
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- dielectric layer
- hardness
- oxidizing agent
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- layer
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Abstract
本揭露是关于制造半导体的方法。方法包含提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。在凸出部上沉积第一介电层并填补沟槽,第一介电层具有第一硬度。使用氧化剂处理第一介电层。对第一介电层执行化学机械研磨制程。
Description
技术领域
本揭露是关于制造半导体元件的方法。
背景技术
半导体集成电路(integrated circuit;IC)工业历经了指数性的成长。集成电路材料及设计的技术发展已创造了数代集成电路,每一代皆有比上一代更小且更复杂的电路。集成电路的演化的过程中,功能密度(如每个晶片内的互连接元件的数量)不断提升,而元件尺寸(如制程所能制造出的最小组件)则不断缩小。尺寸缩小的制程一般提供了生产效率的提升以及减少相关的浪费。尺寸的缩小亦增加了制程及生产的复杂性。因应技术的进步,集成电路制程及制造的相关发展是必须的。
例如,多栅极元件的引入是通过增加栅极通道耦合来改善栅极控制,降低断态电流(OFF-state current),以及降低短通道效应(short-channel effects;SCEs)。多栅极元件的一种形式为鳍式场效晶体管(fin field effect transistor;FinFET),晶体管具有鳍状的半导体通道,且栅电极与鳍的两边或三边结合。典型的鳍式场效晶体管制程中,鳍形成于凸出基板外(例如透过磊晶及/或蚀刻制程)并通过深沟槽隔开。沟槽接着填补间隙填充介电材料以作为隔离结构。随着元件尺寸不断的缩小,沟槽的深宽比(aspect ratio)亦增加。如此一来,间隙填充材料的密度将会降低以适当地填充深沟槽。然而,低密度的间隙填充材料常常在后续的化学机械研磨制程(chemical mechanical planarization;CMP)期间产生刮痕缺陷(scratch defect)的问题。此外,单层的间隙填充材料有些时候并不适用于较低的湿蚀刻速率。在这状况下,沉积二层或多层的间隙填充材料二成为薄膜堆迭。相邻的薄膜之间亦有较差连接的问题。
因此,为解决上述领域的问题,相关的发展是必要的。
发明内容
本揭露的一实施例为制造半导体元件的方法。提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。沉积第一介电层于凸出部上并填补沟槽,第一介电层具有第一硬度。使用氧化剂处理第一介电层。对第一介电层执行化学机械研磨制程。
本揭露的另一实施例为制造半导体元件的方法。提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。沉积第一二氧化硅层于凸出部上并填补沟槽,第一二氧化硅层具有第一硬度。使用氧化剂处理第一二氧化硅层,使得第一二氧化硅层具有处理部分以及未处理部分,其中处理部分位于未处理部分上方,且第一二氧化硅层的处理部分具有大于第一硬度的第二硬度。沉积第二二氧化硅层于第一二氧化硅层的处理部分上,其中第二二氧化硅层具有大于第一硬度的第三硬度。对第二二氧化硅层及第一二氧化硅层执行化学机械研磨制程。
本揭露的又一实施例为制造半导体元件的方法。提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。沉积第一二氧化硅层于凸出部上并填补沟槽,第一二氧化硅层具有第一硬度。在低于摄氏100度下,使用水性氧化剂处理第一二氧化硅层,使得第一二氧化硅层具有处理部分,其中处理部分具有大于第一硬度的第二硬度;沉积第二二氧化硅层于处理部分上,其中第二二氧化硅层具有大于第一硬度的第三硬度。对第二二氧化硅层及第一二氧化硅层执行化学机械研磨制程。
附图说明
阅读以下详细叙述并搭配对应的附图,可了解本揭露的多个态样。应注意,根据业界中的标准做法,多个特征并非按比例绘制。事实上,多个特征的尺寸可任意增加或减少以利于讨论的清晰性。
图1为本揭露的部分实施例的制造半导体元件的方法;
图2A、2B、2C、2D、2E、2F及2G为图1的制造半导体元件的方法在各个制造步骤的局部截面图;
图3为图1的其中一实施例的方法的流程图;
图4A为图3的方法所制造的半导体元件的透视图;
图4B、4C、4D、4E、4F及4G为图3的制造半导体元件的方法在制造图4A的半导体元件的各个步骤的局部截面图。
具体实施方式
以下揭露提供众多不同的实施例或范例,用于实施本案提供的主要内容的不同特征。下文描述一特定范例的组件及配置以简化本揭露。当然,此范例仅为示意性,且并不拟定限制。举例而言,以下描述“第一特征形成在第二特征的上方或之上”,于实施例中可包括第一特征与第二特征直接接触,且亦可包括在第一特征与第二特征之间形成额外特征使得第一特征及第二特征无直接接触。此外,本揭露可在各范例中重复使用元件符号及/或字母。此重复的目的在于简化及厘清,且其自身并不规定所讨论的各实施例及/或配置之间的关系。
此外,空间相对术语,诸如“下方(beneath)”、“以下(below)”、“下部(lower)”、“上方(above)”、“上部(upper)”等等在本文中用于简化描述,以描述如附图中所图示的一个元件或特征结构与另一元件或特征结构的关系。除了描绘图示的方位外,空间相对术语也包含元件在使用中或操作下的不同方位。此设备可以其他方式定向(旋转90度或处于其他方位上),而本案中使用的空间相对描述词可相应地进行解释。
本揭露大致上是关于制造半导体元件的方法,更特别地是关于制造鳍式场效晶体管的方法,以及鳍式场效晶体管的栅极取代制程。典型的鳍式场效晶体管制程中,在基板上形成多个凸出基板的平行的鳍,鳍之间透过深沟槽隔开。接着,沉积介电间隙填充材料至沟槽中以及鳍的上方以作为隔离结构。随着制程的尺寸越来越小,深沟槽的深宽比越来越小。在部分案例中,深宽比可为12或更大。如此一来,适当地在深沟槽内填充高密度的间隙填充材料具有较高难度。为了克服这样的问题,在后续的制程世代(node)中,具有较低密度的材料便广泛用于间隙填充材料。然而,此种较低密度的材料在化学机械研磨制程期间经常产生缺陷,例如刮痕缺陷。在化学机械研磨制程期间所产生的缺陷可能造成漏电、短路、开路,或其他集成电路产品的问题。鳍式场效晶体管在制造上的另外一个问题为,两层或三层的间隙填充材料常具有较差的附着力。虽然低密度的间隙填充材料可以填满深沟槽,然而在部分案例中低密度的间隙填充材料对于湿蚀刻并没有足够的抗性。因此,可以在低密度的间隙填充材料上沉积较高密度的间隙填充材料以作为填补。而低密度间隙填充材料与高密度间隙填充材料之间的交界面具有较差的附着力。
本揭露提供一种强化低密度间隙填充材料的方法,借此降低集成电路产品在化学机械研磨制程所产生的缺陷。本揭露的部分实施例中,低密度间隙填充材料的强化是通过对低密度间隙填充材料的顶部进行热控制水氧化剂处理。此种方法可以直接地与现有的制程结合。此外,低密度间隙填充材料经过处理的部分沉积有高密度的间隙填充材料,故具有较佳的附着力。
本揭露的部分实施例除了在鳍结构的制程之外,亦可在应用于栅极取代制程。本领域的通常知识者应了解本揭露的态样可应用于不同范例的半导体元件以及制程。
图1为本揭露的部分实施例的制造半导体元件100的方法10的流程图。半导体元件100具有鳍式场效晶体管。图3为本揭露的部分实施例的使用栅极取代制程制造半导体元件200的方法50的流程图。方法50可视为方法10的一种实施例。方法10及方法50仅为范例,并不限制本揭露所欲保护的范畴。额外的操作可以在方法10及方法50之前、之间,或之后进行。且部分操作在其他实施例中亦可被取代、省略,或改变位置。方法10在下方搭配图2A至图2G作描述。方法50在下方搭配图4A至图4G作描述。
可以预期的,半导体元件100及200可包含在集成电路中,例如微处理器、记忆体元件,及/或包含在其他具有被动式元件的集成电路,例如电阻、电容,及电感。以及具有主动式元件的集成电路,例如p型场效晶体管(p-type field effect transistors;pFET)、n型场效晶体管(n-type field effect transistors;nFET)、金属氧化物半导体晶体管(metal-oxide semiconductor field effect transistors;MOSFET)、互补式金属氧化物半导体(complementary metal-oxide semiconductor;CMOS)晶体管、双极性晶体管(bipolar transistor)、高电压晶体管、高频率晶体管、具有多栅极的鳍式场效晶体管,以及上述的组合。
请参照图1,方法10的操作12中,提供元件100的前置物。为了方便描述,前置物亦称为元件100。参照图2A,元件100包含基板102以及多个位于基板102上的凸出部104。凸出部104由沟槽110隔开。于部分实施例中,基板102可为半导体基板如硅晶圆。基板102亦可包含其他半导体,例如:锗;化合物半导体,例如:碳化硅(silicon carbide)、砷化镓(galliumarsenide)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indiumarsenide)及/或锑化铟(indium antimonide);合金半导体,例如:磷砷化镓(GaAsP)、砷化铟铝(InAlAs)、铝砷化镓(AlGaAs)、砷化铟镓(InGaAs)、磷化铟镓(GaInP)及/或砷磷化铟镓(GaInAsP),或上述的组合。此外,基板102可选择性地具有磊晶层,磊晶层可受到应力以强化效能,亦可具有绝缘体上硅结构,及/或其他适合的强化特征。
于本实施例中,凸出部104包含半导体鳍106及介电硬质遮罩层108。半导体鳍106可形成于基板102之外。介电硬质遮罩层108可包含氮化硅或其他适合材料。于一实施例中,凸出部104由一个或多个光微影制程及蚀刻制程形成。举例而言,介电硬质遮罩层108沉积在基板102上方作为毯覆层,沉积方法可为化学气相沉积(chemical vapor deposition;CVD)、电浆辅助化学气相沉积(plasma enhanced CVD;PECVD)、物理气相沉积(physicalvapor deposition;PVD)、热氧化(thermal oxidation),或其他技术。接着,透过光微影制程,在介电硬质遮罩层108上方沉积遮罩元件。光微影制程可包含在介电硬质遮罩层108上方形成光阻,并对光阻曝光以界定鳍106(或是沟槽110)的几何图案,执行曝光后烘烤制程,将光阻显影以形成遮罩元件。遮罩元件的开口对应到沟槽110的位置。
接着,介电硬质遮罩层108及基板102在开口处被蚀刻,形成图2A所示的凸出部104。蚀刻技术可为干蚀刻、湿蚀刻,或其他适合的蚀刻技术。例如,干蚀刻制程可以应用含氧气体、含氟气体(如:四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯气体(如:氯气(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)及/或三氯化硼(BCl3))、含溴气体(如:溴化氢(HBr)及/或三溴甲烷(CHBr3))、含碘气体,或其他适合气体及/或电浆,及/或上述的组合。例如,湿蚀刻制程可在以下材料中蚀刻,如:稀释氢氟酸(diluted hydrofluoric acid;DHF)、氢氧化钾(KOH)溶液、氨(ammonia)、氢氟酸溶液、硝酸(HNO3),及/或乙酸(CH3COOH),或其他适合的蚀刻剂。
如图2A所示,凸出部104具有顶表面S104。沟槽110在X方向上有宽度W110,在Z方向上有高度H110。沟槽110的深宽比定义为H110/W110。随着元件尺寸不断的缩小,深宽比将会越来越大。于一实施例中,深宽比为12或更高。
图1的方法10的操作14中,在凸出部104上方沉积介电层114并填补沟槽110。请参照图2B,介电层114将凸出部104埋在下方,使凸出部104与其他部分电性隔离。于本实施例中,在沉积介电层114之前,先在凸出部104上方形成衬垫层112。衬垫层112举例而言可包含二氧化硅,且通过热氧化、化学气相沉积、物理气相沉积,或其他沉积技术形成。衬垫层112可包含其他介电材料,亦可在部分实施例中省略。
于本实施例中,为了适当地把基板102上方的部分填满,且由于沟槽110具有高深宽比,可使用含有硅及氧的低密度介电材料作为介电层114。此外,操作14使用流动式化学气相沉积(flowable CVD;FCVD)来沉积介电层114。例如,操作14可引入一含硅化合物及一含氧化合物作为前驱物。硅化合物及含氧化合物反应形成流动介电材料(如液体化合物),借此填补沟槽110。于替代实施例中,介电层114的沉积可使用其他化学气相沉积或其他沉积技术(如:旋涂)。于部分实施例中,适合介电层114的材料可为四乙氧基硅烷氧化物(tetraethyl orthosilicate oxide)、未掺杂的硅酸盐玻璃(un-doped silicate glass;USG),或经掺杂的氧化硅,如熔融硅玻璃(fused silica glass;FSG)、磷硅酸盐玻璃(phosphosilicate glass;PSG)、掺杂硼的硅玻璃、硼磷硅酸盐玻璃(borophosphosilicateglass;BPSG),其他含氧或含硅的低密度介电材料,及其他适合的介电材料。接着,执行退火制程以将流动介电材料转换成固态材料。例如,退火制程可在摄氏300度至摄氏1200度下执行2至10小时。然而,在某些状况下,元件100并不希望在如此高温下进行退火。例如,退火制程可能降低n通道元件的拉伸应力(tensile strain)并降低元件效能。这种问题一般而言称为应力松弛(strain relaxation)。此外,即便执行退火制程,介电层114在后续制造步骤中对于湿蚀刻可能不具有足够的抗性。
在一个范例中,后续的制造步骤包含对介电层114执行化学机械研磨制程。化学机械研磨制程的用意在于平坦化元件100的上表面并使凸出部104曝露。由于介电层114内具有相对较低的材料密度,化学机械研磨制程在某些时候可能对介电层114造成缺陷。化学机械研磨制程所造成的缺陷可包含有机残留物、水痕、特殊附着物及碰撞(impingement)、斑蚀(corrosion pit)及刮痕。化学机械研磨制程的刮痕缺陷是最为严重的,因为可能使元件产生短路、开路,及/或大面积的图案移除,借此影响良率以及集成电路元件的寿命。本揭露的发明人发现一种有效的方法可以强化介电层114,借此在制程中降低化学机械研磨制程的刮痕缺陷。
图1的方法10的操作16中,使用氧化剂116处理介电层114。参照图2C,于一实施例中,氧化剂116平均地作用在元件100的整个表面。于本实施例中,氧化剂116为水性氧化剂,可使操作16与其他方法10中的制造步骤直接结合,例如操作14及后续讨论的操作18。例如,操作14、16、18可全部在湿制程机台(wet bench)的制造环境下进行,水性氧化剂116为去离子水(deionized water;DIW)。于另一实施例中,水性氧化剂116为稀释氢氟酸。由于稀释氢氟酸在介电层114(如二氧化硅)上可同时具有蚀刻以及氧化的效果,故稀释氢氟酸的浓度要经过调控,使得氢氟酸氧化剂116可以适当地氧化介电层114,但又不会使介电层114通过蚀刻损失太多部分。于一实施例中,稀释氢氟酸氧化剂116内的氢氟酸浓度范围为0.005%至0.1%。水性氧化剂116作用于介电层114上的方法可为喷雾(spray)、旋涂,或其他适合的技术。于一实施例中,操作16可依序应用多于一个氧化剂。例如,操作16可使用去离子水(或稀释氢氟酸)作为第一氧化剂。在处理一些时间后,操作16可使用氢氟酸(或去离子水)作为第二氧化剂,其中第二氧化剂不同于第一氧化剂。相较于操作14的退火制程,操作16在氧化上更有效率。即便退火步骤可使用水蒸气进行湿退火,然而由于在退火步骤中使用了载气(carrier gas),如氮气,故水的含量受到相当程度的稀释。
于本实施例中,操作16在控制温度的条件下执行。特别地,操作16在低于摄氏100度下执行,此温度与某些氧化剂116为水性的湿制程机台制造流程一致。例如,操作16可在温度为摄氏15度至摄氏90度间执行,例如室温摄氏25度。应注意,这些温度远低操作14中退火介电层114的典型的退火温度。因此,操作16并不会造成上述的应力松弛的现象。于不同实施例中,操作16可执行数秒至数分钟,例如3秒至120秒,取决于氧化剂以及处理时的温度。
于替代实施例中,氧化剂116可为去离子水与稀释氢氟酸以外的水溶液。例如,氧化剂116可为稀释过氧化氢(hydrogen peroxide;H2O2)。再又其他实施例中,氧化剂116可为气体氧化剂,例如氧气。
图2D为操作16完成后的元件100。介电层114的上部分114A经氧化剂116处理,而介电层114的下部分114B未经处理或轻微地处理。上部分114A(亦可称为处理部分114A)相对于下部分114B(亦可称为未处理部分114B)具有较高的硬度。于部分实施例中,处理部分114A的硬度约为未处理部分114B的硬度的1.1倍至1.2倍。此外,处理部分114A相较于未处理部分114B具有较高薄膜密度。处理部分114A与未处理部分114B之间有一个虚构的边界S114A。实际上,介电层114的硬度(或薄膜密度)是从顶表面往基板102的方向逐渐改变的。因此,硬度在边界S114A之间并没有突然地改变。在一范例中,介电层114含有硅及氧,处理部分114A相较于未处理部分114B具有较高成分的硅氧键结。于本实施例中,操作16的温度、氧化剂浓度、处理时间经调控,使得边界S114A低于凸出部104的顶表面S104。处理部分114A提供了充足的薄膜硬度,以减少化学机械研磨的刮痕缺陷。
图1的方法10的操作18,在处理部分114A上沉积另一介电层118。请参照图2E,介电层118相较于未经操作16处理的介电层114具有较高的硬度。例如,介电层118的硬度为未经处理的介电层114的硬度的1.1倍至1.5倍。这样的配置可以满足两层薄膜厚度的需求,以及后续化学机械研磨制程的低蚀刻抗性。于一实施例中,介电层118的硬度甚至可高于处理部分114A。应了解,处理部分114A与介电层118之间的附着力优于原本未经处理的介电层114与介电层118之间的附着力。
于一实施例中,介电层118适合的材料包含四乙氧基硅烷氧化物(tetraethylorthosilicate oxide)、未掺杂的硅酸盐玻璃(un-doped silicate glass;USG),或经掺杂的二氧化硅,如熔融硅玻璃(fused silica glass;FSG)、磷硅酸盐玻璃(phosphosilicateglass;PSG)、掺杂硼的硅玻璃、硼磷硅酸盐玻璃(borophosphosilicate glass;BPSG),其他含氧或含硅的低密度介电材料,及其他适合的介电材料。于一实施例中,介电层118的沉积可使用流动式化学气相沉积。或者,介电层118的沉积可使用化学气相沉积、物理气相沉积、旋涂,或其他适合的沉积技术。
图1的方法10的操作20,执行化学机械研磨制程120以开槽介电层118及介电层114,如图2F所示。化学机械研磨制程使用适合的化学机械研磨制程消耗品,例如研磨片(polishing pad)、研磨液(slurry)、调节器(conditioner),调控于开槽介电层118及介电层114的材料。例如,研磨片可为硬质研磨片或软质研磨片,且可具有孔隙或凹槽。研磨液可包含硝酸铁(ferric nitrate)、过氧化物(peroxide)、碘酸钾(potassium iodate)、氨、二氧化硅(silica)、氧化铝(alumina),或其他研磨液材料。研磨液可进一步含有研磨剂(abrasive)、酸碱调节剂(pH adjustor),及一个或多个添加物,如氧化剂(oxidizingagent)、错合剂(complexing agent)、腐蚀抑制剂(corrosion inhibitor),及分散剂(dispersion agent)。于一实施例中,介电层118及介电层114含有二氧化硅,且化学机械研磨制程120使用二氧化铈(CeO2)基的研磨液。化学机械研磨制程120完全移除介电层118并部分移除介电层114借此曝露下方部分,以用于后续的制程,如图2G所示。于一实施例中,化学机械研磨制程120包含第一阶段及第二阶段。在第一阶段中,应用较高的下压力(down-force)以完全移除介电层118并部分移除介电层114。在第二阶段中,应用较弱的下压力以精确地控制介电层114剩余部分的厚度。由于经过氧化处理,化学机械研磨制程的在介电层114中所造成的刮痕缺陷大幅降低。于部分范例中,化学机械研磨制程的刮痕缺陷的降低幅度为50%至75%。
图1的方法10的操作22,执行更多步骤以完成最终的鳍式场效晶体管元件。于一案例中,操作22将半导体鳍106取代为一个或多个磊晶生长的半导体层。此案例进一步而言,操作22透过一个或多个蚀刻制程,移除了介电硬质遮罩层108并部分移除半导体鳍106,借此形成开口。接着,操作22在开口内磊晶生长半导体层。于另一范例中,操作22开槽介电层114以暴露部分半导体鳍106。接着,操作22在半导体鳍106上形成栅电极、源/漏极特征、接触点等等,以形成鳍式场效晶体管。
图3为本揭露的部分实施例的使用栅极取代制程制造半导体元件200的方法50的流程图。方法50可视为方法10的一种实施例。方法50在下方搭配图4A至图4G作详细的描述。图4A为半导体元件200的局部透视图,而第4B至4G图为沿着图4A的1-1线所截取的局部截面图。
图3的方法50的操作12A,提供一前置物,其中前置物亦可称为元件200,包含基板202以及多个位于基板202上的凸出部208。参照图4A,凸出部208为虚设栅极结构(dummygate structure),用于栅极取代制程。因此在后续讨论中,凸出部208亦称为虚设栅极208。虚设栅极208由沟槽230分隔。元件200还包含位于基板202上方的鳍204,以及位于基板202上方以及鳍204之间的隔离结构206。于一实施例中,基板202、鳍204,及隔离结构206分别类似于图2G的基板102、鳍106,以及介电层114。为了简化的目的,这些特征的细节将不再赘述。
参照图4B,虚设栅极208分别包含氧化层222、栅电极层224、硬质遮罩层226,及封端层228。氧化层222可包含介电材料如二氧化硅。栅电极层224可为单层或多层结构。于一实施例中,栅电极层224包含多晶硅。于一实施例中,硬质遮罩层226包含氮化硅,而封端层228包含二氧化硅。氧化层222、栅电极层224、硬质遮罩层226,及封端层228皆可由化学氧化、热氧化、原子层沉积、化学气相沉积、低压化学气相沉积、电浆辅助化学气相沉积,及/或其他适合的方法形成。于部分实施例中,虚设栅极208被栅极间隔层(未图示)包围。虚设栅极208与下方的鳍204的接合处为通道区212。于本实施例中,两个虚设栅极208共用一个源/漏极区210。于替代实施例中,两个虚设栅极208并不共用源/漏极区210。沟槽230在Y方向(亦为鳍式场效晶体管通道长度的方向)具有宽度W230,在Z方向具有高度H230。于一实施例中,沟槽230的深宽比(H230/W230)较大。
图3的方法50的操作14A,在虚设栅极208上方沉积介电层234并填补沟槽230。请参照图4C,于本实施例中,在沉积介电层234之前,先在鳍204以及虚设栅极208上方形成蚀刻停止层232(etch stop layer;ESL)。蚀刻停止层232可包含氮化硅(SiN)、氮碳化硅(SiCN)、碳氮氧化硅(SiCON),或其他适合的材料,且可使用化学气相沉积、物理气相沉积、原子层沉积,或其他适合的方法形成。于本实施例中,介电层234使用包含有硅及氧的低密度介电材料以适当地填补沟槽230。此外,介电层234使用流式化学气相沉积形成。介电层234的材料以及沉积方法皆与图1的操作14所述的介电层114类似。于部分范例中,介电层234的硬度无法满足后续的制程。于本实施例中,介电层234使用氧化剂进行处理,以增加硬度,详细内容将在后续讨论。
图3的方法50的操作16,使用氧化剂236处理介电层234。如图4D所示,氧化剂236在许多方面皆与氧化剂116类似。为了简化的目的,氧化剂236的部分细节将省略。于部分实施例中,氧化剂236为水性氧化剂,如去离子水或稀释氢氟酸。操作16在控制温度的条件下执行。特别地,操作16在低于摄氏100度下执行,如摄氏15度至摄氏90度间。如此一来,介电层234的上部分234经氧化,使得介电层234的上部分234A(亦可称为处理部分234A)相对于未经氧化的下部分234B(亦可称为未处理部分234B)具有较高的硬度。于部分实施例中,处理部分234A的硬度约为未处理部分234B的硬度的1.1倍至1.2倍。此外,处理部分234A相较于未处理部分234B具有较高薄膜密度。于本实施例中,上部分234A延伸至虚设栅极208的顶表面的下方。
图3的方法50的操作18,在处理部分234A上沉积另一介电层238。介电层238相较于未经处理的介电层234具有较高的硬度。例如,介电层238度为未经处理的介电层234硬度的1.1倍至1.5倍。介电层238的材料以及沉积方法皆与图2E的介电层118类似。由于经过处理,介电层238与介电层234之间的附着力增加。
图3的方法50的操作20,执行化学机械研磨制程240以开槽介电层238及234,如图4F所示。化学机械研磨制程240在许多方面实质上相同于化学机械研磨制程120(图2F所示)。由于在操作16中执行的处理,介电层234(特别是处理部分234A)有助于降低化学机械研磨制程240所造成的刮痕缺陷。
图3的方法50的操作22A,执行更多步骤以完成最终的鳍式场效晶体管元件。于本实施例中,操作22A执行不同蚀刻、沉积,以及平坦化制程以取代虚设栅极208成为最终栅极242,如图4G所示。例如,操作22A可通过多个蚀刻步骤移除氧化层222、栅电极层224、硬质遮罩层226,及封端层228,并形成开口。接着,操作22A在开口内沉积最终栅极242并执行化学机械研磨制程以平坦化元件200的顶表面。最终栅极242可包含内介面层、栅极介电层(如高介电常数栅极介电层)、功函数金属层,及金属填充层。最终栅极242的各层可透过化学氧化、热氧化、原子层沉积、化学气相沉积、电镀,及/或其他适合的方法形成。
虽不欲进行限制,然本揭露的一个或多实施例对半导体元件及其制造方法提供了诸多优点。例如,本揭露的部分实施例提供强化介电层的方法,借以降低化学机械研磨制程所产生的刮痕缺陷。经强化的介电层亦与其他层之间提供了较佳附着力。
本揭露的一实施例为半导体元件的制造方法。提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。在凸出部上沉积第一介电层并填补沟槽,第一介电层具有第一硬度。使用氧化剂处理第一介电层。对第一介电层执行化学机械研磨制程。
依据本揭露的部分实施例,其中第一介电层的处理部分延伸至所述多个凸出部的顶表面下方。
依据本揭露的部分实施例,其中处理第一介电层是在低于摄氏100度的温度下执行。
依据本揭露的部分实施例,其中氧化剂为水溶液。
依据本揭露的部分实施例,其中处理第一介电层是在摄氏15度至摄氏90度的温度下执行。
依据本揭露的部分实施例,其中氧化剂为去离子水。
依据本揭露的部分实施例,其中氧化剂为稀释氢氟酸。
依据本揭露的部分实施例,其中氧化剂内氢氟酸的浓度范围为0.005%至0.1%。
依据本揭露的部分实施例,其中沟槽的高度与宽度的深宽比大于12。
依据本揭露的部分实施例,此方法还包含在处理第一介电层之后及执行化学机械研磨制程之前:沉积第二介电层于第一介电层上,其中第二介电层具有高于第一硬度的第二硬度,其中化学机械研磨制程亦对第二介电层执行。
依据本揭露的部分实施例,其中第一介电层及第二介电层包括二氧化硅。
依据本揭露的部分实施例,其中凸出部包含多个半导体鳍。
依据本揭露的部分实施例,其中凸出部包含多个栅极结构。
本揭露的另一实施例为半导体元件的制造方法。提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。在凸出部上沉积第一二氧化硅层并填补沟槽,第一二氧化硅层具有第一硬度。使用氧化剂处理第一二氧化硅层,使得第一二氧化硅层具有处理部分以及未处理部分,其中处理部分位于未处理部分上方,且第一二氧化硅层的处理部分具有大于第一硬度的第二硬度。沉积第二二氧化硅层于第一二氧化硅层的处理部分上,其中第二二氧化硅层具有大于第一硬度的第三硬度。对第二二氧化硅层及第一二氧化硅层执行化学机械研磨制程。
依据本揭露的部分实施例,其中氧化剂为去离子水。
依据本揭露的部分实施例,其中氧化剂为稀释氢氟酸。
依据本揭露的部分实施例,其中氧化剂内氢氟酸的浓度范围为0.005%至0.1%。
依据本揭露的部分实施例,其中处理第一二氧化硅层是在摄氏15度至摄氏90度的温度下执行。
本揭露的又一实施例为半导体元件的制造方法。提供一前置物,具有基板以及位于基板上的多个凸出部,凸出部之间安插有多个沟槽。在凸出部上沉积第一二氧化硅层并填补沟槽,第一二氧化硅层具有第一硬度。在低于摄氏100度下,使用水性氧化剂处理第一二氧化硅层,使得第一二氧化硅层具有处理部分,其中处理部分具有大于第一硬度的第二硬度;沉积第二二氧化硅层于处理部分上,其中第二二氧化硅层具有大于第一硬度的第三硬度。对第二二氧化硅层及第一二氧化硅层执行化学机械研磨制程。
依据本揭露的部分实施例,其中氧化剂为去离子水及氢氟酸的其中一者。
上文概述了若干实施例的特征,以便本领域熟悉此项技艺者可更好地理解本揭示案的态样。本领域熟悉此项技艺者应当了解到他们可容易地使用本揭示案作为基础来设计或者修改其他制程及结构,以实行相同目的及/或实现相同优势的。本领域熟悉此项技艺者亦应当了解到,此类等效构造不脱离本揭示案的精神及范畴,以及在不脱离本揭示案的精神及范畴的情况下,其可对本文进行各种改变、取代及变更。
Claims (14)
1.一种半导体元件的制造方法,其特征在于,包含:
提供一前置物,具有一基板以及位于该基板上的多个凸出部,所述多个凸出部之间安插有多个沟槽;
沉积一第一介电层于在所述多个凸出部上并填补所述多个沟槽,该第一介电层具有一第一硬度;
使用一氧化剂处理该第一介电层;
在处理该第一介电层后,在该第一介电层上沉积一第二介电层,其中该第二介电层具有高于该第一硬度的一第二硬度;以及
对该第一介电层和该第二介电层执行化学机械研磨制程,其中处理该第一介电层的一温度范围为摄氏15度至摄氏90度,该氧化剂为一氢氟酸,且该氢氟酸的浓度范围为0.005%至0.1%。
2.根据权利要求1所述的半导体元件的制造方法,其特征在于,该第一介电层的一处理部分延伸至所述多个凸出部的一顶表面下方。
3.根据权利要求1所述的半导体元件的制造方法,其特征在于,该氧化剂为水性。
4.根据权利要求1所述的半导体元件的制造方法,其特征在于,在用一氧化剂处理该第一介电层后,还包含用一去离子水处理该第一介电层。
5.根据权利要求1所述的半导体元件的制造方法,其特征在于,所述多个沟槽的一高度与一宽度之间的一深宽比大于12。
6.根据权利要求1所述的半导体元件的制造方法,其特征在于,该第一介电层与该第二介电层包含二氧化硅。
7.根据权利要求1所述的半导体元件的制造方法,其特征在于,所述多个凸出部包含多个半导体鳍。
8.根据权利要求1所述的半导体元件的制造方法,其特征在于,所述多个凸出部包含多个栅极结构。
9.一种半导体元件的制造方法,其特征在于,包含:
提供一前置物,具有一基板以及位于该基板上的多个凸出部,所述多个凸出部之间安插有多个沟槽;
沉积一第一介电层于所述多个凸出部上并填补所述多个沟槽,该第一介电层包含氧和硅且具有一第一硬度;
使用一水性氧化剂处理该第一介电层,使得该第一介电层具有一处理部分以及一未处理部分,其中该处理部分位于该未处理部分上方,且该第一介电层的该处理部分具有大于该第一硬度的一第二硬度;
沉积一第二介电层于该第一介电层的该处理部分上,其中该第二介电层包含氧和硅且具有大于该第一硬度的一第三硬度;以及
执行化学机械研磨制程以完全移除该第二介电层并部分移除该第一介电层,其中处理该第一介电层的一温度范围为摄氏15度至摄氏90度。
10.根据权利要求9所述的半导体元件的制造方法,其特征在于,该水性氧化剂为去离子水。
11.根据权利要求9所述的半导体元件的制造方法,其特征在于,该水性氧化剂为氢氟酸。
12.根据权利要求9所述的半导体元件的制造方法,其特征在于,该水性氧化剂内的一氢氟酸的浓度范围0.005%至0.1%。
13.一种半导体元件的制造方法,其特征在于,包含:
提供一前置物,具有一基板以及位于该基板上的多个凸出部,所述多个凸出部之间安插有多个沟槽;
沉积一第一介电层于所述多个凸出部上并填补所述多个沟槽,该第一介电层包含氧和硅且具有一第一硬度;
在低于摄氏100度下,使用水性的一氧化剂处理该第一介电层,使得该第一介电层具有一处理部分;
沉积一第二介电层于该处理部分上,其中该第二介电层包含氧和硅;以及
执行化学机械研磨制程以完全移除该第二介电层并部分移除该第一介电层。
14.根据权利要求13所述的半导体元件的制造方法,其特征在于,该氧化剂为去离子水及稀释氢氟酸的其中一者。
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