CN106935588B - 半导体存储器装置 - Google Patents
半导体存储器装置 Download PDFInfo
- Publication number
- CN106935588B CN106935588B CN201611235726.9A CN201611235726A CN106935588B CN 106935588 B CN106935588 B CN 106935588B CN 201611235726 A CN201611235726 A CN 201611235726A CN 106935588 B CN106935588 B CN 106935588B
- Authority
- CN
- China
- Prior art keywords
- film
- memory device
- semiconductor memory
- columnar structures
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000003860 storage Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 18
- 230000000903 blocking effect Effects 0.000 claims description 7
- 238000005192 partition Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 229910052710 silicon Inorganic materials 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 25
- 238000000034 method Methods 0.000 description 23
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005405 multipole Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims (13)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562272733P | 2015-12-30 | 2015-12-30 | |
US62/272,733 | 2015-12-30 | ||
US15/200,254 US9780105B2 (en) | 2015-12-30 | 2016-07-01 | Semiconductor memory device including a plurality of columnar structures and a plurality of electrode films |
US15/200,254 | 2016-07-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106935588A CN106935588A (zh) | 2017-07-07 |
CN106935588B true CN106935588B (zh) | 2020-12-11 |
Family
ID=59226835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201611235726.9A Active CN106935588B (zh) | 2015-12-30 | 2016-12-28 | 半导体存储器装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9780105B2 (zh) |
CN (1) | CN106935588B (zh) |
TW (1) | TWI625841B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013012553A (ja) * | 2011-06-28 | 2013-01-17 | Toshiba Corp | 半導体記憶装置 |
US9842651B2 (en) | 2015-11-25 | 2017-12-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin film transistor strings |
US11120884B2 (en) | 2015-09-30 | 2021-09-14 | Sunrise Memory Corporation | Implementing logic function and generating analog signals using NOR memory strings |
US9972640B1 (en) * | 2016-11-17 | 2018-05-15 | Sandisk Technologies Llc | Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof |
US10475812B2 (en) | 2018-02-02 | 2019-11-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin-film transistor strings |
JP2019161010A (ja) | 2018-03-13 | 2019-09-19 | 東芝メモリ株式会社 | 半導体装置 |
US10504918B2 (en) | 2018-03-16 | 2019-12-10 | Toshiba Memory Corporation | Memory device |
JP2020038900A (ja) * | 2018-09-04 | 2020-03-12 | キオクシア株式会社 | 半導体装置 |
US11282855B2 (en) * | 2018-12-07 | 2022-03-22 | Sunrise Memory Corporation | Methods for forming multi-layer vertical NOR-type memory string arrays |
JP2021048353A (ja) * | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置 |
WO2021127218A1 (en) | 2019-12-19 | 2021-06-24 | Sunrise Memory Corporation | Process for preparing a channel region of a thin-film transistor |
WO2022108848A1 (en) | 2020-11-17 | 2022-05-27 | Sunrise Memory Corporation | Methods for reducing disturb errors by refreshing data alongside programming or erase operations |
TW202310429A (zh) | 2021-07-16 | 2023-03-01 | 美商日升存儲公司 | 薄膜鐵電電晶體的三維記憶體串陣列 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105027285A (zh) * | 2013-01-24 | 2015-11-04 | 美光科技公司 | 三维存储器 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4772656B2 (ja) * | 2006-12-21 | 2011-09-14 | 株式会社東芝 | 不揮発性半導体メモリ |
JP5142692B2 (ja) * | 2007-12-11 | 2013-02-13 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2010161132A (ja) | 2009-01-07 | 2010-07-22 | Toshiba Corp | 不揮発性半導体記憶装置、及びその製造方法 |
JP2010219409A (ja) | 2009-03-18 | 2010-09-30 | Toshiba Corp | 不揮発性半導体記憶装置 |
CN102484114B (zh) | 2010-07-08 | 2014-10-15 | 松下电器产业株式会社 | 非易失性半导体存储装置及其制造方法 |
DE102011084603A1 (de) * | 2010-10-25 | 2012-05-16 | Samsung Electronics Co., Ltd. | Dreidimensionales Halbleiterbauelement |
KR101826221B1 (ko) * | 2011-05-24 | 2018-02-06 | 삼성전자주식회사 | 반도체 메모리 소자 및 그의 제조 방법 |
JP2013004778A (ja) | 2011-06-17 | 2013-01-07 | Toshiba Corp | 半導体記憶装置 |
US8987805B2 (en) | 2012-08-27 | 2015-03-24 | Samsung Electronics Co., Ltd. | Vertical type semiconductor devices including oxidation target layers |
KR102002802B1 (ko) | 2012-09-05 | 2019-07-23 | 삼성전자주식회사 | 반도체 장치 |
KR102078597B1 (ko) | 2013-06-27 | 2020-04-08 | 삼성전자주식회사 | 반도체 장치 |
US20160268299A1 (en) * | 2015-03-13 | 2016-09-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
-
2016
- 2016-07-01 US US15/200,254 patent/US9780105B2/en active Active
- 2016-12-16 TW TW105141703A patent/TWI625841B/zh active
- 2016-12-28 CN CN201611235726.9A patent/CN106935588B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105027285A (zh) * | 2013-01-24 | 2015-11-04 | 美光科技公司 | 三维存储器 |
Also Published As
Publication number | Publication date |
---|---|
US9780105B2 (en) | 2017-10-03 |
CN106935588A (zh) | 2017-07-07 |
TWI625841B (zh) | 2018-06-01 |
US20170194341A1 (en) | 2017-07-06 |
TW201735327A (zh) | 2017-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106935588B (zh) | 半导体存储器装置 | |
US20200176469A1 (en) | Method for manufacturing semiconductor memory device and semiconductor memory device | |
US10096613B2 (en) | Semiconductor device and method for manufacturing same | |
US10103155B2 (en) | Semiconductor memory device | |
US8912592B2 (en) | Non-volatile memory device including etch stop layer pattern | |
US9929041B1 (en) | Semiconductor device and method for manufacturing same | |
US20140264549A1 (en) | Vertical memory devices with vertical isolation structures and methods of fabricating the same | |
US8643081B2 (en) | Semiconductor memory device | |
WO2017099220A1 (ja) | 半導体装置及びその製造方法 | |
US20130032874A1 (en) | Method for manufacturing nonvolatile semiconductor memory device and nonvolatile semiconductor memory device | |
US20120117316A1 (en) | Semiconductor device having stacked array structure, nand flash memory array using the same and fabrication thereof | |
JP2020145387A (ja) | 半導体記憶装置 | |
US9871054B2 (en) | Semiconductor device and method for manufacturing same | |
CN111048520B (zh) | 半导体装置和制造半导体装置的方法 | |
US10622303B2 (en) | Semiconductor device having a stacked body including a first stacked portion and a second stacked portion | |
US20150263035A1 (en) | Method for manufacturing semiconductor memory device | |
US9761605B1 (en) | Semiconductor memory device | |
CN110391174B (zh) | 制造具有含有多个沟槽的结构图案的半导体器件的方法 | |
JP2021048372A (ja) | 半導体記憶装置及び半導体記憶装置の製造方法 | |
US9502470B2 (en) | Semiconductor memory device and method for manufacturing same | |
US9570461B2 (en) | Method for manufacturing semiconductor memory device | |
US20180277563A1 (en) | Semiconductor memory device and method for manufacturing the same | |
TWI821718B (zh) | 半導體記憶裝置 | |
US10026748B2 (en) | Stacked type semiconductor memory device and method for manufacturing same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20170808 Address after: Tokyo, Japan Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Applicant before: Toshiba Corp. |
|
TA01 | Transfer of patent application right | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220129 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right |