CN106847778A - 半导体封装载板及其制造方法 - Google Patents

半导体封装载板及其制造方法 Download PDF

Info

Publication number
CN106847778A
CN106847778A CN201510884611.1A CN201510884611A CN106847778A CN 106847778 A CN106847778 A CN 106847778A CN 201510884611 A CN201510884611 A CN 201510884611A CN 106847778 A CN106847778 A CN 106847778A
Authority
CN
China
Prior art keywords
layer
carrier plate
packaging semiconductor
conductor layer
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510884611.1A
Other languages
English (en)
Other versions
CN106847778B (zh
Inventor
许诗滨
曾昭崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Persistent Strength Or Power Science And Technology Co Ltd
Phoenix Pioneer Technology Co Ltd
Original Assignee
Persistent Strength Or Power Science And Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Persistent Strength Or Power Science And Technology Co Ltd filed Critical Persistent Strength Or Power Science And Technology Co Ltd
Priority to CN201510884611.1A priority Critical patent/CN106847778B/zh
Priority to US15/206,471 priority patent/US9806012B2/en
Priority to JP2016143293A priority patent/JP6290987B2/ja
Publication of CN106847778A publication Critical patent/CN106847778A/zh
Application granted granted Critical
Publication of CN106847778B publication Critical patent/CN106847778B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/8149—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/8549—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明是关于一种半导体封装载板及其制造方法。本发明的半导体封装载板主要包括一模铸介电层与一图案化导体层。模铸介电层具有至少一开口槽。而图案化导体层是埋设于此模铸介电层内，其中部分图案化导体层自开口槽显露出是作为导电柱，另一部分该图案化导体层作为导线。

Description

半导体封装载板及其制造方法
技术领域
本发明是关于一种载板及其制造方法，特别关于一种适用于中低脚数的集成电路封装领域的半导体封装载板及其制造方法。
背景技术
随着人类对提高生活便利性的需求下，各种电子化产品爆炸性的急速扩张，而在电子产品组件制程上占据举足轻重地位的集成电路封装技术也因应此需求所寄予的高速处理化、多功能化、积集化（Integrated）以及小型轻量化等多方面渴望，朝向微型化与高密度化发展。
目前半导体封装技术在中低脚数的封装上主要是以引线框架（Lead frame）、四方扁平无脚封装（Quad Flat No-lead Package, QFN）或晶圆级晶片封装方式（WB CSP）为主，但若要应用于智能手机或穿戴式装置所需求的小型、轻薄、低成本以及细间距等功能需求下，上述封装用的载板或引线框架已面临技术瓶颈。
举例来说，在引线框架上的封装制程架构上，其所使用的导线架厚度往往较大，再者，因为其无法形成较为精细的线路与现率间距，以及线路布局（un-routable），因此导线架无法对设置于其上的晶片具有电磁波防护效果。此外，现有的载板的介电材料是采用有玻璃纤维的核心层（CCL）或树脂胶片（PP：Prepreg），并用雷射钻孔（laser via）作为电性连接，但雷射对玻璃纤维材进行钻孔的加工产出慢，成本高，且孔径不易微小化。再者，当介电材采用玻纤的BT、FR4、FR5或ABF等材料和防焊材料时，在薄型化的情况下，非常容易产生板翘，导致薄型化困难。更者，由玻璃纤维组构成的介电材料也增加了细线路加工的难度与成本。
因此，各家封装业者无不汲汲营营研究可符合目前中低脚数封装结构市场所需的导线架。本发明是针对此一需求，提出一种崭新的载板及其制造方法，以符合此需。
发明内容
本发明的主要目的在于提供一种半导体封装载板及其制造方法，其兼具有可绕线，细线路间距与厚度薄的优点。
本发明的另一目的在于提供一种半导体封装载板及其制造方法，其可符合中低脚数的集成电路封装领域的体积轻薄与成本低廉的需求。
为达上述目的，本发明提供一种半导体封装载板的制造方法，其包含：
于一暂时性载板的一表面形成一图案化导体层；
于该暂时性载板的该表面上形成一模铸介电层，该模铸介电层覆盖该图案化导体层；
于该模铸介电层上形成至少一开口槽，该开口槽显露出部分该图案化导体层；以及
移除该暂时性载板，以显露出该图案化导体层的一侧及部分的该介电材料层，
其中部分该图案化导体层自该开口槽显露出，形成该图案化导体层上下两端是开放端的是作为导电柱，而形成该图案化导体层仅一端是开放端的是作为导线。
本发明的一个实施例中，其中该暂时性载板为铁、镍、铜金属或与介电材料复合而制成。
本发明的一个实施例中，其中形成该图案化导体层的步骤系包含：
于该暂时性载板的该表面形成一图案化光阻层，该图案化光阻层具有复数开孔；
于该开孔中形成一导体材料；以及
移除该图案化光阻层，以形成该图案化导体层。
本发明的一个实施例中，其中该导体材料通过电镀技术、无电镀技术、溅镀技术或蒸镀技术所形成。
本发明的一个实施例中，其中该模铸介电层通过真空压模技术或铸模技术所形成。
本发明的一个实施例中，其中在形成该开口槽后，更包含填设一导电层于该开口槽内。
本发明的一个实施例中，更包含：
形成一保护层于该导电层表面及显露于该模铸介电层外的该图案化导体层表面。
本发明的一个实施例中，更包含：
形成一保护层于显露于该模铸介电层外的该图案化导体层表面。
本发明还提供一种半导体封装载板，其包含：
一模铸介电层，其具有至少一开口槽；以及
至少一图案化导体层，其埋设于该模铸介电层内，其中部分该图案化导体层自该开口槽显露出，形成该图案化导体层上下两端是开放端的是作为导电柱，而形成该图案化导体层仅一端是开放端的是作为导线。
本发明的一个实施例中，其中该模铸介电层是一利用真空压模技术或铸模技术所形成模铸介电层。
本发明的一个实施例中，更包含有一导电层，其填设于该开口槽内。
本发明的一个实施例中，其中该导电层表面与显露于该模铸介电层外的该图案化导体层表面上形成有一保护层。
本发明的一个实施例中，其中显露于该模铸介电层外的该图案化导体层表面上形成有一保护层。
本发明还提供一种使用上述所述的半导体封装载板所形成的封装结构，其包含：
一晶片，其设置于该载板表面；以及
一封胶层，其封围该晶片。
本发明的一个实施例中，更包含至少一锡球，其设置于该开口槽内并与该导电柱电性连接。
本发明的有益效果如下：
本发明的崭新的半导体封装载板与其制作方法，其导电柱和导线是由图案化导体层所同时形成，并利用一高度约略相近的模铸介电层封围，能够减少载板整体厚度，并且因导电层的图案化过程已经是一相当成熟的技术，因此线路间距也可以大幅缩小，并可以形成环绕式的导线布局，进而提供晶片电磁上的防护。
附图说明
图1所示为本发明第一实施例的半导体封装载板的一示意图。
图2为图1的半导体封装载板应用于球栅阵列封装的一实施例示意图。
图3为图1的半导体封装载板应用于球栅阵列封装的另一实施例示意图。
图4A至图4F为图1所示的半导体封装载板的制作步骤示意图。
图4G为具有保护层的半导体封装载板的一示意图。
图5为本发明第二实施例的半导体封装载板的一示意图。
图6为图5的半导体封装载板应用于平面网格阵列封装的一实施例示意图。
图7为图5的半导体封装载板应用于平面网格阵列封装的另一实施例示意图。
图8A至图8F为图5所示的半导体封装载板的制作步骤示意图。
附图标记
10、50 半导体封装载板
12 模铸介电层
14 图案化导体层
14a 导电柱
14b 导线
16 保护层
18 开口槽
20、60 封装结构
22 晶片
23 连接凸块
24 封胶层
25 固定胶
26 锡球
32 金属线材
40 暂时性载板
42 图案化光阻层
422 开孔
44 导体材料
52 导电层。
具体实施方式
以下将通过实施例来解释本发明内容，本发明的实施例并非用以限制本发明须在如实施例所述的任何特定的环境、应用或特殊方式方能实施。因此，关于实施例的说明仅为阐释本发明的目的，而非用以限制本发明。须说明者，以下实施例及图式中，与本发明非直接相关的元件已省略而未绘示；且图式中各元件间的尺寸关系仅为求容易了解，非用以限制实际比例。另外，以下实施例中，相同的元件将以相同的元件符号加以说明。
本发明是一种兼具有体积小、厚度薄，成本低，且导线间距可以细微化等特性的载板，其可应用于中低脚数的集成电路封装领域。请参照图1所示，本发明的半导体封装载板的第一实施例的示意图。如图1所示，半导体封装载板10主要包括一模铸介电层12以及至少一图案化导体层14。图案化导体层14埋设于模铸介电层12内，且图案化导体层14包含有至少一第一导体部与至少一第二导体部。其中，第一导体部与第二导体部之间由模铸介电层12隔离。模铸介电层12具有至少一开口槽18，以显露出第一导体部，使第一导体部呈现上下两端皆为开放式，也就是第一导体部具有上下两端显露于模铸介电层12外的开放端，使第一导体部可作为上下层电性传递的导电柱14a。而第二导体部仅一端开放式显露于模铸介电层12外，是作为导线14b，可做同一层的线路布局（绕线）之用。另外，部分的导线14b亦可作为电性连接垫，以作为与电子元件连接的用途。
于此，要说明的是，所谓的开放式是指图案化导体层14未被模铸介电层12覆盖的部分。换言之，即显露于模铸介电层12的部分图案化导体层14，不论是否再被其他元件覆盖，皆称之为开放式。
上述的界定方式是意味着导电柱14a与导线14b实由单一图案化导体层14所同步形成的，差异仅在于开口槽18的有无，来界定出此部分的图案化导体层14是作为上下层电性传递的导电柱14a或是做为单一平面的电性传递的导线14b。此外，图案化导体层14是埋设于模铸介电层12内，所以模铸介电层12的高度可以与图案化导体层14极为近似，因为其仅需些许增加覆盖住图案化导体层14单一侧的高度仅可。如此一来，整体载板的厚度将可以大幅缩小。
再者，图案化导体层14自模铸介电层12显露于外的部分更形成有一保护层16，以避免显露出的图案化导体层14在常态环境下产生氧化反应。
上述的半导体封装载板10可应用于球栅阵列（BGA）封装。举例来说，如图2所示，封装结构20包含有一晶片22、一封胶层24以及至少一锡球26。晶片22是借助至少一连接凸块（Bump）23采覆晶接合（Flip-Chip）方式通过保护层16而与半导体封装载板10中的导线14b电性连接。封胶层24将晶片22与位于晶片22侧的显露于模铸介电层12外的导电柱14a、导线14b及保护层16同时封围，以防止湿气由外部进入。锡球26设置于导电柱14a未被封胶层24封围的开口槽18，以作为电性接脚，来与后续之电路板（图中未示）之电性接点连接。
当然，如图3所示，晶片22也可利用固定胶25暂时固定于半导体封装载板10，再藉借助金属线材32采打线接合（wire bonding）方式通过保护层16而与半导体封装载板10上的导电柱14a电性连接。因封装过程为一现有技术，于此将不再赘述。
再如图1所示，半导体封装载板10使用模铸介电层12作为基材，以承载图案化导体层14，并借以绝缘隔离以及保护图案化导体层14。模铸介电层12的材质是可选用晶片封装用的铸模化合物（Molding Compound），其例如但不限于具有酚醛基树脂（Novolac-Based Resin）、环氧基树脂（Epoxy-Based Resin）、硅基树脂（Silicone-Based Resin）或其他适当的铸模化合物，且铸模化合物亦可包含适当的填充剂，例如是粉状二氧化硅。
于本实施例中，图案化导体层14的材质为金属，例如但不限于选自铜、铁、银、镍及其组合。
请参阅图4A至图4F，其系图1的半导体封装载板10的制作步骤示意图。首先如图4A所示，提供一可分离式的暂时性载板40，并于此暂时性载板40表面上形成一图案化光阻层42，其具有复数开孔422。图案化光阻层42应用曝光显影技术所形成。在本实施例中，暂时性载板40的材质可以为铁、镍、铜金属或与介电材料复合而制成，当然也可依据不同的技术需求进行任意变化。
随后，如图4B所示，于图案化光阻层42的该等开孔422中形成一导体材料44。于本实施例中，导体材料44的材质为金属，例如但不限于选自铜、铁、银、镍及其组合，且依据不同的材质可应用电镀技术、无电镀（Electroless Plating）技术、溅镀（Sputtering Coating）技术或蒸镀（Thermal Coating）技术所形成。
接续，如图4C所示，移除图案化光阻层42即获得先前所述的具有至少一第一导体部与至少一第二导体部的图案化导体层14。随后，如图4D所示，利用铸模技术形成一覆盖图案化导体层14的一模铸介电层12。于本实施例中，模铸介电层12可应用真空压模技术或是铸模技术所形成。当应用铸模技术时，模铸介电层12的材质可选用晶片封装用的铸模化合物，其例如但不限于具有酚醛基树脂、环氧基树脂、硅基树脂或其他适当的铸模化合物，且铸模化合物亦可包含适当的填充剂，例如是粉状二氧化硅。
另外，当应用铸模技术时，形成模铸介电层12之步骤还可包括：提供一铸模化合物，其中铸模化合物具有树脂及粉状的二氧化硅；加热铸模化合物至液体状态；注入呈液态之铸模化合物于第三开孔中，并使铸模化合物在高温和高压下包覆图案化导体层；固化铸模化合物，使铸模化合物形成模铸介电层12。
随后，如图4E所示，移除部分位于图案化导体层14上的模铸介电层12，形成数个开口槽18，以显露出部分图案化导体层14。此处所指的移除步骤，可选用磨削（grinding）、电浆（plasma）或反应离子式蚀刻（RIE）的方式来移除部分模铸介电层12。
最后，搭配图4F所示，移除暂时性载板40，即获得半导体封装载板10。如该图所示，移除暂时性载板40后，图案化导体层14的另一侧将显露出来，以作为后续的电性连接用途，此时，部分图案化导体层14的上下两端显露于模铸介电层12，以作为导电柱14a，而另一部分图案化导体层14仅一端显露于模铸介电层12外者作为导线14b。
此外，再如图4G所示，为避免显露出在常态环境下产生氧化反应，更可于显露于模铸介电层12外的图案化导体层14表面上形成一保护层16。此保护层16可以是有机保焊膜（OSP）、Ni/Pd/Au镀膜或Ni/Ag镀膜。
请参阅图5，其为本发明第二实施例的半导体封装载板50的示意图。此实施例与第一实施例的差异在于半导体封装载板50的模铸介电层12的开口槽18内更填设有一导电层52，以使导电柱14a加上导电层52的高度与模铸介电层12的高度约略一致。
此时为避免显露出在常态环境下产生氧化反应，同样也可于显露于模铸介电层12外的导电柱14a、导线14b或导电层52表面上形成一保护层16。
请图6所示，其为图5所示的半导体封装载板50应用于平面网格阵列封装的一实施例示意图。如图6所示，封装结构60包含有一晶片22及一封胶层24。晶片22是借助连接凸块23采覆晶接合方式通过保护层16而与半导体封装载板50中显露于外的导线14b电性连接。封胶层24是将晶片22与位于晶片侧自该模铸介电层12显露外的导线14b封围，以防止湿气由外部进入。因封装过程为一现有技术，于此将不再赘述。当然，如图7所示，晶片22也可藉借助固定胶25暂时固定于半导体封装载板50，再利用金属线材32采打线接合方式通过保护层16来与半导体封装载板50上的导电柱14a电性连接。
请参阅图8A至图8F，其为本发明第二实施例的半导体封装载板50的制作步骤示意图。首先如图8A所示，提供一可分离式的暂时性载板40，并于此暂时性载板40表面上形成一图案化光阻层42，其具有复数开孔422。
随后，如图8B所示，于图案化光阻层42的开孔422形成一导体层，接续，移除图案化光阻层42，以获得一图案化导体层14。随后，如图8C所示，形成一覆盖图案化导体层14的模铸介电层12。
随后，如图8D所示，利用磨削（grinding）、电浆（plasma）或反应离子式蚀刻（RIE）的方式于模铸介电层12上形成至少一开口槽18，以显露出部分图案化导体层14的表面。
接续，如图8E所示，于开口槽18内填入一导电层52，以使自开口槽18所露出的该部分图案化导体层14的高度加上导电层52的高度后能够与模铸介电层12的高度约略一致。
最后，搭配图8F所示，移除暂时性载板40，以形成半导体封装载板50。如该图所示，移除暂时性载板40后，图案化导体层14的另一侧将显露出来，以作为后续的电性连接用途。此时为避免显露出在常态环境下产生氧化反应，更可于显露于模铸介电层12外的图案化导体层14以及导电层52表面上形成一保护层16。
在上述图8A至图8F中制程步骤的细节，如暂时性载板的材料，图案化光阻层的形成方法等可承袭图4A至图4F所教示的内容，因此不再进行赘述。
综上所述，本发明提供一种崭新的半导体封装载板与其制作方法，其导电柱和导线是由图案化导体层所同时形成，并利用一高度约略相近的模铸介电层封围，因为模铸介电层的高度与导电柱或导线的高度相当近似，因此能够减少载板整体厚度，并且因导电层的图案化过程已经是一相当成熟的技术，因此线路间距也可以大幅缩小，并可以形成环绕式的导线布局（routable），进而提供晶片电磁上的防护。
以上所述者仅为本发明的较佳实施例，自不能以此限制本案的申请专利范围。举凡熟悉本案技艺的人士，爰依本案发明精神所作的等效修饰或变化，皆应包括于申请专利范围内。

Claims (15)

1.一种半导体封装载板的制造方法，其特征在于包含：
于一暂时性载板的一表面形成一图案化导体层；
于该暂时性载板的该表面上形成一模铸介电层，该模铸介电层覆盖该图案化导体层；
于该模铸介电层上形成至少一开口槽，该开口槽显露出部分该图案化导体层；以及
移除该暂时性载板，以显露出该图案化导体层的一侧及部分的该介电材料层，
其中部分该图案化导体层自该开口槽显露出，形成该图案化导体层上下两端是开放端的是作为导电柱，而形成该图案化导体层仅一端是开放端的是作为导线。
2.如权利要求1所述的半导体封装载板的制造方法，其特征在于，其中该暂时性载板为铁、镍、铜金属或与介电材料复合而制成。
3.如权利要求1所述的半导体封装载板的制造方法，其特征在于，其中形成该图案化导体层的步骤包含：
于该暂时性载板的该表面形成一图案化光阻层，该图案化光阻层具有复数开孔；
于该开孔中形成一导体材料；以及
移除该图案化光阻层，以形成该图案化导体层。
4.如权利要求3所述的半导体封装载板的制造方法，其特征在于，其中该导体材料通过电镀技术、无电镀技术、溅镀技术或蒸镀技术所形成。
5.如权利要求1所述的半导体封装载板的制造方法，其特征在于，其中该模铸介电层通过真空压模技术或铸模技术所形成。
6.如权利要求1所述的半导体封装载板的制造方法，其特征在于，其中在形成该开口槽后，更包含填设一导电层于该开口槽内。
7.如权利要求6所述的半导体封装载板的制作方法，其特征在于，更包含：
形成一保护层于该导电层表面及显露于该模铸介电层外的该图案化导体层表面。
8.如权利要求1所述的半导体封装载板的制作方法，其特征在于，更包含：
形成一保护层于显露于该模铸介电层外的该图案化导体层表面。
9.一种半导体封装载板，其特征在于包含：
一模铸介电层，其具有至少一开口槽；以及
至少一图案化导体层，其埋设于该模铸介电层内，其中部分该图案化导体层自该开口槽显露出，形成上下两端是开放端作为导电柱，于该图案化导体层仅一端是开放端作为导线。
10.如权利要求9所述的半导体封装载板，其特征在于，其中该模铸介电层是一利用真空压模技术或铸模技术所形成模铸介电层。
11.如权利要求9所述的半导体封装载板，其特征在于，更包含有一导电层，其填设于该开口槽内。
12.如权利要求11所述的半导体封装载板，其特征在于，其中该导电层表面与显露于该模铸介电层外的该图案化导体层表面上形成有一保护层。
13.如权利要求9所述的半导体封装载板，其特征在于，其中显露于该模铸介电层外的该图案化导体层表面上形成有一保护层。
14.一种使用如权利要求9所述的半导体封装载板所形成的封装结构，其特征在于，包含：
一晶片，其设置于该载板表面；以及
一封胶层，其封围该晶片。
15.如权利要求14所述的封装结构，其特征在于，更包含至少一锡球，其设置于该开口槽内并与该导电柱电性连接。
CN201510884611.1A 2015-12-04 2015-12-04 半导体封装载板及其制造方法 Active CN106847778B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510884611.1A CN106847778B (zh) 2015-12-04 2015-12-04 半导体封装载板及其制造方法
US15/206,471 US9806012B2 (en) 2015-12-04 2016-07-11 IC carrier of semiconductor package and manufacturing method thereof
JP2016143293A JP6290987B2 (ja) 2015-12-04 2016-07-21 半導体パッケージ基板及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510884611.1A CN106847778B (zh) 2015-12-04 2015-12-04 半导体封装载板及其制造方法

Publications (2)

Publication Number Publication Date
CN106847778A true CN106847778A (zh) 2017-06-13
CN106847778B CN106847778B (zh) 2021-06-29

Family

ID=58798565

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510884611.1A Active CN106847778B (zh) 2015-12-04 2015-12-04 半导体封装载板及其制造方法

Country Status (3)

Country Link
US (1) US9806012B2 (zh)
JP (1) JP6290987B2 (zh)
CN (1) CN106847778B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10037897B2 (en) * 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging
WO2023037799A1 (ja) * 2021-09-08 2023-03-16 株式会社村田製作所 高周波モジュール

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200948232A (en) * 2008-05-06 2009-11-16 Kinsus Interconnect Tech Corp Manufacturing method of leadless packaging substrate
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
CN103632980A (zh) * 2012-08-22 2014-03-12 矽品精密工业股份有限公司 封装基板的制法
CN104851869A (zh) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 封装装置及其制作方法
CN105097759A (zh) * 2014-05-09 2015-11-25 矽品精密工业股份有限公司 封装堆栈结构及其制法暨无核心层式封装基板及其制法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI442530B (zh) 2009-10-14 2014-06-21 Advanced Semiconductor Eng 封裝載板、封裝結構以及封裝載板製程
KR102003279B1 (ko) * 2012-07-17 2019-07-25 삼성전자 주식회사 반도체 몰딩 하부 금형, 반도체 패키지 및 반도체 패키지 제조 방법
CN105097757B (zh) 2014-04-21 2018-01-16 碁鼎科技秦皇岛有限公司 芯片封装基板、芯片封装结构及制作方法
JP2016039290A (ja) * 2014-08-08 2016-03-22 イビデン株式会社 プリント配線板および半導体パッケージ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200948232A (en) * 2008-05-06 2009-11-16 Kinsus Interconnect Tech Corp Manufacturing method of leadless packaging substrate
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
CN103632980A (zh) * 2012-08-22 2014-03-12 矽品精密工业股份有限公司 封装基板的制法
CN104851869A (zh) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 封装装置及其制作方法
CN105097759A (zh) * 2014-05-09 2015-11-25 矽品精密工业股份有限公司 封装堆栈结构及其制法暨无核心层式封装基板及其制法

Also Published As

Publication number Publication date
JP2017103447A (ja) 2017-06-08
US20170162492A1 (en) 2017-06-08
CN106847778B (zh) 2021-06-29
US9806012B2 (en) 2017-10-31
JP6290987B2 (ja) 2018-03-07

Similar Documents

Publication Publication Date Title
US7934313B1 (en) Package structure fabrication method
US10276553B2 (en) Chip package structure and manufacturing method thereof
US8354746B2 (en) Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
CN102446882B (zh) 一种半导体封装中封装系统结构及制造方法
US10141233B2 (en) Electronic package and fabrication method thereof
US9190387B2 (en) Method for fabricating quad flat non-leaded package structure with electromagnetic interference shielding function
JP2002057241A (ja) 移植性導電パターンを含む半導体パッケージ及びその製造方法
US9418922B2 (en) Semiconductor device with reduced thickness
CN102543937A (zh) 一种芯片上倒装芯片封装及制造方法
KR101374145B1 (ko) 반도체 패키지 및 그 제조 방법
CN110444517A (zh) 集成电路封装
CN108695269A (zh) 半导体装置封装及其制造方法
US9202712B2 (en) Lead frame and a method of manufacturing thereof
CN106847778A (zh) 半导体封装载板及其制造方法
CN108538794A (zh) 表面贴装型封装结构及其制作方法
CN102522394A (zh) 一种芯片上芯片封装及制造方法
CN112750804A (zh) 半导体设备封装和其制造方法
KR20180029822A (ko) 반도체 패키지 및 이의 제조방법, 전자소자 모듈
CN202384324U (zh) 一种半导体封装中封装系统结构
CN106803487B (zh) 封装装置及其导线架及导线架的制作方法
TWI594349B (zh) 半導體封裝載板及其製造方法
KR102531701B1 (ko) 프리 몰드 기판 및 프리 몰드 기판의 제조 방법
TWI839931B (zh) 內埋感測晶片之封裝結構及其製法
WO2021174395A1 (zh) 封装结构及封装结构的制作方法
CN101840866A (zh) 芯片级尺寸封装结构及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant