CN106673641A - 一种低压压敏陶瓷片及其制备方法 - Google Patents

一种低压压敏陶瓷片及其制备方法 Download PDF

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CN106673641A
CN106673641A CN201710000618.1A CN201710000618A CN106673641A CN 106673641 A CN106673641 A CN 106673641A CN 201710000618 A CN201710000618 A CN 201710000618A CN 106673641 A CN106673641 A CN 106673641A
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CN106673641B (zh
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卢振亚
颜健
钟财富
陈志武
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South China University of Technology SCUT
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Abstract

本发明公开了一种低压压敏陶瓷片，由电压非线性陶瓷层和低电阻率导电陶瓷层层叠构成，所述电压非线性陶瓷层和低电阻率导电陶瓷层之间设有金属隔离层；低压压敏陶瓷片的上、下底面分别设有上、下电极。本发明还公开了上述低压压敏陶瓷片的制备方法。本发明的低压压敏陶瓷片，具有低压敏电压、高非线性特性，又具有优良脉冲电流耐受能力。

Description

一种低压压敏陶瓷片及其制备方法
技术领域
本发明涉及压敏陶瓷片及其制备方法，特别涉及一种低压压敏陶瓷片及其制备方法。
背景技术
ZnO压敏元件已大量用于电力电子线路中吸收或抑制异常过电压，保护电力电子设备免遭破坏。
现有ZnO压敏陶瓷材料有三类材料组成系统，一类是中高电压梯度ZnO压敏材料组成系统，其主要成分包括ZnO，Bi2O3，Co2O3，MnO2，Sb2O3，Cr2O3，Ni2O3，该材料组成系统制作的压敏陶瓷材料压敏电压梯度介于150～300V/mm之间；另一类是高电压梯度ZnO压敏材料组成系统，其主要成分除了上述中高压材料所有成分外还添加稀土材料(如La2O3，Er2O3，Y2O3，Ho2O3等稀土材料中的一种或多种)，添加稀土材料的目的是抑制产品烧结过程中ZnO晶体颗粒长大，使材料形成细晶结构，从而提高压敏电压梯度，该材料组成系统制作的压敏陶瓷材料压敏电压梯度大于300V/mm；还有一类是低电压梯度ZnO压敏材料组成系统，该类材料系统在前述中高电压梯度ZnO压敏材料组成基础上，增加引入TiO2，以促进烧结时ZnO晶粒长大，同时去除或保留微量的Sb2O3，Cr2O3，该类材料组成系统制作的压敏陶瓷材料压敏电压梯度介于15～150V/mm之间。
以上三类材料吸收脉冲电流的能力按单位体积吸收脉冲能量计，中高电压梯度ZnO压敏材料最好，高电压梯度ZnO压敏材料次之，低电压梯度ZnO压敏材料最差。
现有产业化技术制造低压压敏电阻(按国内外压敏电阻产品标准，低压压敏电阻压敏电压范围介于18V～68V之间)，都是采用上述低电压梯度ZnO压敏材料，与中高电压梯度压敏陶瓷材料相比，其脉冲电流承受能力小得多，现有国内外产品标准和各压敏电阻生产厂商的产品目录都可反映该事实，例如日本松下公司产品目录中规定同尺寸规格的18～68V压敏电阻产品的脉冲电流测试要求值仅为中高压82～470V压敏电阻产品的脉冲电流要求值的1/3～1/5。
总之，现有产业化技术制备低压ZnO压敏电阻产品的脉冲电流吸收能力远低于中高压ZnO压敏电阻，而脉冲电流吸收能力好得多的中高电压梯度ZnO压敏陶瓷材料又不能用于制造低压ZnO压敏电阻产品。
发明内容
为了克服现有技术的上述缺点与不足，本发明的目的在于提供一种具有低压敏电压、高非线性特性，又具有优良脉冲电流耐受能力的低压压敏陶瓷片。
本发明的另一目的在于提供上述低压压敏陶瓷片的制备方法。
本发明的目的通过以下技术方案实现：
一种低压压敏陶瓷片，由电压非线性陶瓷层和低电阻率导电陶瓷层层叠构成，所述电压非线性陶瓷层和低电阻率导电陶瓷层之间设有金属隔离层；低压压敏陶瓷片的上、下底面分别设有上、下电极。
所述电压非线性陶瓷层由多层电压非线性陶瓷膜层叠而成。
所述低电阻率导电陶瓷层由多层低电阻率导电陶瓷膜层叠而成。
所述电压非线性陶瓷层的材料组成包括ZnO、Bi2O3、Co2O3、MnO2、Sb2O3、Ni2O3、和Al(NO3)3·9H2O；其中Bi2O3、Co2O3、MnO2、Sb2O3、Ni2O3的加入量均为ZnO的0.3～0.6mol％；Al(NO3)3·9H2O的加入量为ZnO的0.04～0.06mol％。
所述低电阻率导电陶瓷层的材料组成包括ZnO、Co2O3、MnO2、Sb2O3、Ni2O3、Al(NO3)3·9H2O和H3BO3；其中，Co2O3、MnO2、Sb2O3、Ni2O3的加入量均为ZnO的0.3～0.6mol％；Al(NO3)3·9H2O加入量为ZnO的0.1～0.2mol％；H3BO3加入量为ZnO的0.04～0.06mol％。
所述金属隔离层由银钯电极浆料制成。
所述的低压压敏陶瓷片的制备方法，包括以下步骤：
(1)分别制备电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜；
(2)在电压非线性陶瓷的生料膜或低电阻率导电陶瓷层的生料膜上印刷金属隔离层；
(3)将电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜层叠，并使金属隔离层位于电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜之间，得到叠层膜；
(4)将叠层膜抽真空密封，放入等静压工作缸在不低于80Mpa压力下保压，使膜层粘结，获得等静压生料膜带；
(5)将等静压生料膜带冲压生坯片；
(6)将生坯片排胶、烧结，获得压敏陶瓷黑片；
(7)在压敏陶瓷黑片的上、下底面分别印刷电极浆料，烧结后制得低压氧化锌压敏陶瓷片。
步骤(1)所述电压非线性陶瓷的生料膜采用挤膜法、流延法或轧膜法。
步骤(1)所述低电阻率导电陶瓷层的生料膜采用挤膜法、流延法或轧膜法。
步骤(7)所述电极浆料为银电极浆料。
与现有技术相比，本发明具有以下优点和有益效果：
本发明通过将电压非线性陶瓷层和低电阻率导电陶瓷层交替层叠，并在电压非线性陶瓷层和低电阻率导电陶瓷层之间设置金属隔离层，以防止电压非线性陶瓷层和低电阻率导电陶瓷层在烧结时相扩散，得到低压压敏陶瓷片；本发明的低压压敏陶瓷片整体厚度可调节，其脉冲电流吸收能力远高于现有技术制造的低压压敏陶瓷材料。
附图说明
图1为本发明的实施例的低压压敏陶瓷片的截面示意图。
图2为本发明的实施例的多层叠膜的截面示意图。
具体实施方式
下面结合实施例，对本发明作进一步地详细说明，但本发明的实施方式不限于此。
实施例1～4
如图1所示，低压压敏陶瓷片，由电压非线性陶瓷层4和低电阻率导电陶瓷层2层叠构成，所述电压非线性陶瓷层4和低电阻率导电陶瓷层2之间设有金属隔离层3；所述低压压敏陶瓷片的上底面、下底面分别设有上电极5、下电极1。
制备电压非线性层和低电阻率导电层都采用市售纯度为99.7％的间接法ZnO为主成分，其平均粒径小于1微米；以及采用市售化学纯Bi2O3、Co3O4、MnO2、Sb2O3、Ni2O3、Al(NO3)3·9H2O、H3BO3试剂作为副成分。
各实施例中ZnO及Al(NO3)3·9H2O、H3BO3含量固定：其中电压非线性陶瓷层的中：ZnO：100mol％，Al(NO3)3·9H2O加入量0.05mol％；低电阻率导电陶瓷层中：ZnO：100mol％，Al(NO3)3·9H2O加入量0.15mol％；H3BO3加入量为0.05mol％。
各实施例中变量添加物的含量按表1所示。
具体制作步骤如下：
1)制备电压非线性陶瓷粉料和低电阻率导电陶瓷粉料：按上述组成比例称量各种原料，加入适量纯水，混合球磨至平均粒径小于1μm，烤干，制成两种组成粉料备用。
2)采用挤膜法(也可以采用流延法或轧膜法)制备电压非线性陶瓷生料膜和低电阻率导电陶瓷生料膜：分别将电压非线性陶瓷粉料和低电阻率导电陶瓷粉料与羟丙基甲基纤维素(HPMC)胶水搅拌混合、冷冻、混炼挤出成膜，挤出的生坯膜厚0.14～0.16mm，得到电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜；
3)在制成的部分电压非线性陶瓷生料膜上印刷金属隔离层材料(Ag-Pd电极浆料，其银钯金属比例：Ag/Pd＝90/10)。
4)叠膜：如图2所示，先将八层低电阻率导电陶瓷生料膜层21层叠成低电阻率导电陶瓷层(注：叠几层生料膜视生料膜厚度及所需最终产品厚度需要而定)，在之上叠一层印刷有金属隔离层3的电压非线性陶瓷生料膜41，并且使印刷的金属隔离层3与最上一层的低电阻率导电陶瓷生料膜21接触，再在之上叠一层没有印刷金属隔离层的电压非线性陶瓷生料膜41，获得多层叠膜。
5)将上述多层叠膜抽真空密封，放入等静压工作缸，液压压强调至100Mpa，保压5分钟，泄压后取出，获得等静压生料膜带。
6)将上述等静压生料膜带冲压成直径为16.5mm的生坯片。
7)将上述生坯片排胶(以1℃/分钟速率升温至500℃，保温30分钟)、烧结(以3℃/分钟速率升温至1150℃，保温120分钟)，烧结样品随炉冷却后获得压敏陶瓷黑片。
8)在上述压敏陶瓷黑片两面印刷银电极浆料，550℃还原制备银电极，即可制得如图1所示的低压压敏电阻片。
9)将上述低压压敏电阻片焊接引线、采用环氧树脂包封、固化，制成低压ZnO压敏元件。
10)测试电性能结果见表2。
为了说明本发明的效果，对比测试三组样品：对比样1、对比样2和对比样3。
其中制作测试对比样1为了说明本发明的金属隔离层的作用，对比样1的制作方法与实施例1～4类似，但是没有采用金属隔离层材料，其余制作方法按上述制作步骤。
对比样2和对比样3采用市售氧化锌压敏电阻，对比样品2为14D330(芯片直径14mm,压敏电压标称值为33V)，对比样品3为14D470(芯片直径14mm,压敏电压标称值为47V)。
电性能测试方法如下：
采用恒流源法测试样品压敏电压(V1mA)及V0.1mA，采用恒压源(电压调整为75％V1mA)测试样品漏电流，根据下列式(1)计算样品的非线性系数α值。
承受脉冲电流承受能力是压敏元件能够获得实际应用的关键。本发明样品脉冲冲击试验波形为8/20μs模拟雷电波，峰值电流目标值为3000A，脉冲冲击测试前后测试样品的压敏电压，计算压敏电压变化率，并且观察判断样品承受脉冲冲击后的外观结构，若压敏电压V1mA变化率在±10％以内，且样品承受脉冲冲击后外观结构未见破坏，则判断该样品承受脉冲冲击性能合格，否则判断该样品为失效。
表2列出对应表1各实施例样品及对比样1、对比样2和对比样3的电性能测试结果。表2中列出的“小电流特性”为脉冲冲击试验前测得的每组数据的平均值，“脉冲冲击失效率”数据为每组冲击总数中失效数。
从表2所列测试数据可知，采用本发明方法制作的低压压敏电阻元件电性能优于现有技术产品(市售产品)，并且，采用印刷金属隔离层的方法是本发明顺利实施的关键。
表1
表2
实施例5
本实施例除以下步骤外，制备方法与实施例1～4相同。
在制成的部分电压非线性陶瓷生坯膜上印刷金属隔离层材料(Ag-Pd电极浆料，其银钯金属比例：Ag/Pd＝90/10)。
叠膜：先将七层低电阻率导电陶瓷生料膜层叠低电阻率导电陶瓷层，在之上再叠一层印刷有金属隔离层材料的低电阻率导电陶瓷生料膜，并且使印刷的金属隔离层材料朝上，再在之上叠三层电压非线性陶瓷生料膜，获得多层叠膜。
测试电性能结果见表3。
表3
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

1.一种低压压敏陶瓷片，其特征在于，由电压非线性陶瓷层和低电阻率导电陶瓷层层叠构成，所述电压非线性陶瓷层和低电阻率导电陶瓷层之间设有金属隔离层；低压压敏陶瓷片的上、下底面分别设有上、下电极。
2.根据权利要求1所述的低压压敏陶瓷片，其特征在于，所述电压非线性陶瓷层由多层电压非线性陶瓷膜层叠而成。
3.根据权利要求1所述的低压压敏陶瓷片，其特征在于，所述低电阻率导电陶瓷层由多层低电阻率导电陶瓷膜层叠而成。
4.根据权利要求1或2所述的低压压敏陶瓷片，其特征在于，所述电压非线性陶瓷层的材料组成包括ZnO、Bi2O3、Co2O3、MnO2、Sb2O3、Ni2O3、和Al(NO3)3·9H2O；其中Bi2O3、Co2O3、MnO2、Sb2O3、Ni2O3的加入量均为ZnO的0.3～0.6mol％；Al(NO3)3·9H2O的加入量为ZnO的0.04～0.06mol％。
5.根据权利要求1或3所述的低压压敏陶瓷片，其特征在于，所述低电阻率导电陶瓷层的材料组成包括ZnO、Co2O3、MnO2、Sb2O3、Ni2O3、Al(NO3)3·9H2O和H3BO3；其中，Co2O3、MnO2、Sb2O3、Ni2O3的加入量均为ZnO的0.3～0.6mol％；Al(NO3)3·9H2O加入量为ZnO的0.1～0.2mol％；H3BO3加入量为ZnO的0.04～0.06mol％。
6.根据权利要求1所述的低压压敏陶瓷片，其特征在于，所述金属隔离层由银钯电极浆料制成。
7.权利要求1～6任一项所述的低压压敏陶瓷片的制备方法，其特征在于，包括以下步骤：
(1)分别制备电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜；
(2)在电压非线性陶瓷的生料膜或低电阻率导电陶瓷层的生料膜上印刷金属隔离层；
(3)将电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜层叠，并使金属隔离层位于电压非线性陶瓷的生料膜和低电阻率导电陶瓷层的生料膜之间，得到叠层膜；
(4)将叠层膜抽真空密封，放入等静压工作缸在不低于80Mpa压力下保压，使膜层粘结，获得等静压生料膜带；
(5)将等静压生料膜带冲压生坯片；
(6)将生坯片排胶、烧结，获得压敏陶瓷黑片；
(7)在压敏陶瓷黑片的上、下底面分别印刷电极浆料，烧结后制得低压氧化锌压敏陶瓷片。
8.根据权利要求7所述的低压压敏陶瓷片的制备方法，其特征在于，步骤(1)所述电压非线性陶瓷的生料膜采用挤膜法、流延法或轧膜法。
9.根据权利要求7所述的低压压敏陶瓷片的制备方法，其特征在于，步骤(1)所述低电阻率导电陶瓷层的生料膜采用挤膜法、流延法或轧膜法。
10.根据权利要求7所述的低压压敏陶瓷片的制备方法，其特征在于，步骤(7)所述电极浆料为银电极浆料。
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