CN106531799B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN106531799B
CN106531799B CN201610064394.6A CN201610064394A CN106531799B CN 106531799 B CN106531799 B CN 106531799B CN 201610064394 A CN201610064394 A CN 201610064394A CN 106531799 B CN106531799 B CN 106531799B
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insulating film
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铃木拓马
河野洋志
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Toshiba Corp
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Abstract

实施方式的半导体装置包括：SiC层，具有第1面及第2面；栅极绝缘膜，设置于第1面上；栅极电极，设置于栅极绝缘膜上；第1导电型的第1SiC区域，设置于SiC层内，且一部分设置于第1面；第2导电型的第2SiC区域，设置于第1SiC区域内，且一部分设置于第1面；第1导电型的第3SiC区域，设置于第2SiC区域内，且一部分设置于第1面；及第1导电型的第4SiC区域，设置于第2SiC区域与栅极绝缘膜之间，在第1面由第2SiC区域夹着，且在第1面设置于第1SiC区域与第3SiC区域之间。

Description

半导体装置
相关申请案
本申请案享有以日本专利申请案2015-179328号(申请日：2015年9月11日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式主要涉及一种半导体装置。
背景技术
作为下一代的半导体器件用的材料，期待SiC(碳化硅)。SiC与Si(硅)相比，具有带隙为3倍、击穿电场强度为约10倍、导热率为约3倍的优异物性。如果有效利用该特性则能够实现低损耗且能够进行高温动作的半导体器件。
使用了SiC的MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)与使用了Si的MOSFET相比，存在通道的载子迁移率低的问题。
发明内容
本发明的实施方式提供一种通道的载子迁移率高的半导体装置。
实施方式的半导体装置SiC层包括：SiC层，具有第1面及第2面；栅极绝缘膜，设置于所述第1面上；栅极电极，设置于所述栅极绝缘膜上；第1导电型的第1SiC区域，设置于所述SiC层内，且一部分设置于所述第1面；第2导电型的第2SiC区域，设置于所述第1SiC区域内，且一部分设置于所述第1面；第1导电型的第3SiC区域，设置于所述第2SiC区域内，且一部分设置于所述第1面；及第1导电型的第4SiC区域，设置于所述第2SiC区域与所述栅极绝缘膜之间，在所述第1面由所述第2SiC区域夹着，且在所述第1面设置于第1SiC区域与第3SiC区域之间。
附图说明
图1是表示第1实施方式的半导体装置的示意剖视图。
图2是表示第1实施方式的半导体装置的示意俯视图。
图3是表示第1实施方式的半导体装置的示意剖视图。
图4是表示第1实施方式的半导体装置的示意剖视图。
图5是表示第1实施方式的半导体装置的制造方法中制造途中的半导体装置的示意剖视图。
图6是表示第1实施方式的半导体装置的制造方法中制造途中的半导体装置的示意剖视图。
图7是表示第2实施方式的半导体装置的示意剖视图。
图8是表示第2实施方式的半导体装置的示意俯视图。
具体实施方式
以下，一边参照附图，一边对本发明的实施方式进行说明。此外，在以下说明中，对相同或类似的部件等标注相同的符号，对于已进行过一次说明的部件等适当地省略其说明。
而且，以下的说明中，n++、n+、n、n-及p++、p+、p、p-的记述表示各导电型的杂质浓度的相对性的高低。也就是说，表示如下情况：n++的n型的杂质浓度相对高于n+，n+的n型的杂质浓度相对高于n，n-的n型的杂质浓度相对低于n。而且，p++的p型的杂质浓度相对高于p+、p+的p型的杂质浓度相对高于p，p-的p型的杂质浓度相对低于p。另外，存在将n++、n+型、n-型简单地记载为n型、p++、p+型、p-型的情况。
(第1实施方式)
本实施方式的半导体装置包括：SiC层，具有第1面及第2面；栅极绝缘膜，设置于第1面上；栅极电极，设置于栅极绝缘膜上；第1导电型的第1SiC区域，设置于SiC层内，且一部分设置于第1面；第2导电型的第2SiC区域，设置于第1SiC区域内，且一部分设置于第1面；第1导电型的第3SiC区域，设置于第2SiC区域内，且一部分设置于第1面；第1导电型的第4SiC区域，设置于第2SiC区域与栅极绝缘膜之间，在第1面由第2SiC区域夹着，且在第1面设置于第1SiC区域与第3SiC区域之间。
图1、图3、及图4是表示作为本实施方式的半导体装置的MOSFET的构成的示意剖视图。图2是表示作为本实施方式的半导体装置的MOSFET的构成的示意俯视图。图1是图2的A-A'剖面。图3是图2的B-B'剖面。图4是图2的C-C'剖面。
本实施方式的MOSFET100例如利用离子注入形成基底区域(主体区域)及源极区域，为Double Implantation MOSFET(DIMOSFET，双植入型金属氧化物半导体场效应晶体管)。MOSFET100为以电子为载子的垂直型n通道型MOSFET。
MOSFET100具备SiC层10、源极电极12、漏极电极14、栅极绝缘膜16、栅极电极18、层间绝缘膜20。SiC层10内设置着n+型漏极区域22、n-型漂移区域(第1SiC区域)24、p型基底区域(第2SiC区域)26、n+型源极区域(第3SiC区域)28、p+型基底接触区域30、及n-型表面区域(第4SiC区域)32。
SiC层10为单晶SiC。SiC层10例如为4H-SiC。
SiC层10具备第1面与第2面。以下，将第1面称作表面，将第2面称作背面。
第1面例如为相对于(0001)面倾斜0度以上且8度以下的面。而且，第2面例如为相对于(000-1)面倾斜0度以上且8度以下的面。(0001)面被称作硅面。(000-1)面被称作碳面。
n+型漏极区域22设置于SiC层10的背面。漏极区域22例如包含氮(N)作为n型杂质。漏极区域22的n型杂质的杂质浓度例如为1×1018cm-3以上且1×1021cm-3以下。
n-型漂移区域24设置于漏极区域22上。漂移区域24的至少一部分设置于SiC层10的表面。
漂移区域24例如包含氮(N)作为n型杂质。漂移区域24的n型杂质的杂质浓度例如为5×1015cm-3以上且5×1016cm-3以下。漂移区域24的厚度例如为4μm以上且150μm以下。
p型的基底区域26设置于漂移区域24内。基底区域26的至少一部分设置于SiC层10的表面。
基底区域26例如包含铝(Al)作为p型杂质。基底区域26的p型杂质的杂质浓度例如为5×1015cm-3以上且1×1019cm-3以下。基底区域26的深度例如为0.4μm以上且0.8μm以下。
n+型源极区域28设置于基底区域26内。源极区域28的至少一部分设置于SiC层10的表面。
源极区域28例如包含磷(P)作为n型杂质。源极区域28的n型杂质的杂质浓度例如为1×1018cm-3以上且1×1021cm-3以下。源极区域28的深度比基底区域26的深度浅，例如为0.2μm以上且0.4μm以下。
p+型基底接触区域30设置于基底区域26内。基底接触区域30与源极区域28相接而设置。
基底接触区域30例如包含铝(Al)作为p型杂质。基底接触区域30的p型杂质的杂质浓度例如为1×1018cm-3以上且1×1021cm-3以下。
基底接触区域30的深度比基底区域26的深度浅，例如为0.2μm以上且0.4μm以下。
n-型的表面区域32设置于基底区域26与栅极绝缘膜16之间。表面区域32在SiC层10的表面夹在基底区域26之间。在SiC层10的表面交替地形成着表面区域32与基底区域26。
而且，表面区域32在SiC层10的表面，夹在漂移区域24与源极区域28之间。在SiC层10的表面，表面区域32与源极区域28相接。基底区域26也在SiC层10的表面，夹在漂移区域24与源极区域28之间。
表面区域32例如包含氮(N)作为n型杂质。表面区域32的n型杂质的杂质浓度比源极区域28的n型杂质的杂质浓度低。表面区域32的n型杂质的杂质浓度例如为5×1015cm-3以上且5×1016cm-3以下。
表面区域32的SiC层10的表面的宽度(图2、图3中的“w”)例如为0.05μm以上且2.0μm以下。
表面区域32的深度比源极区域28的深度浅，例如为0.05μm以上且0.15μm以下。
栅极绝缘膜16设置于SiC层10的表面上。栅极绝缘膜16设置于漂移区域24上、基底区域26上、源极区域28上及表面区域32上。栅极绝缘膜16例如为氧化硅膜。栅极绝缘膜16例如能够应用High-k绝缘膜(高介电常数绝缘膜)。
栅极电极18设置于栅极绝缘膜16上。栅极电极18为导电层。栅极电极18例如为包含p型杂质或n型杂质的多晶质硅。
层间绝缘膜20设置于栅极电极18上。层间绝缘膜20例如为氧化硅膜。
夹在栅极电极18下的源极区域28与漂移区域24的表面区域32作为MOSFET100的通道区域发挥功能。
源极电极12设置于SiC层10的表面。源极电极12与源极区域28及基底接触区域30电连接。源极电极12与源极区域28及基底接触区域30相接。源极电极12也具备对基底区域26提供电位的功能。
源极电极12含有金属。形成源极电极12的金属例如为钛(Ti)与铝(Al)的积层构造。源极电极12也可含有与SiC层10相接的金属硅化物或金属碳化物。
漏极电极14设置于SiC层10的背面。漏极电极14与漏极区域22电连接。
漏极电极14例如为金属。形成漏极电极14的金属例如为镍(Ni)与金(Au)的积层构造。漏极电极14也可含有与SiC层10的背面相接的金属硅化物或金属碳化物。
接下来，对本实施方式的MOSFET100的制造方法进行说明。尤其对表面区域32的形成方法进行说明。
图5、图6是表示本实施方式的半导体装置的制造方法中制造途中的半导体装置的示意剖视图。
在漏极区域22上利用外延生长形成漂移区域24(图5)。
接下来，在漂移区域24的表面上形成掩模材50。掩模材50例如为利用CVD(Chemical Vapor Deposition，化学气相沉积)法形成的氧化硅膜。
接下来，以掩模材50为掩模，将作为p型杂质的铝(Al)离子注入到漂移区域24(图6)。利用该离子注入形成基底区域26。
铝的离子注入例如利用倾斜离子注入来进行。掩模材50的成为阴的区域未导入铝，从而未形成基底区域26。换句话说，掩模材50的成为阴的区域保留漂移区域24，形成着表面区域32。结果，表面区域32的n型杂质的杂质浓度与漂移区域24的n型杂质的杂质浓度大致相同。
然后，将掩模材50剥离，利用公知的程序形成n+型源极区域28、p+型基底接触区域30、栅极绝缘膜16、栅极电极18、层间绝缘膜20、源极电极12及漏极电极14，从而制造出MOSFET100。
以下，对实施方式的半导体装置的作用及效果进行说明。
使用了SiC的MOSFET与使用了Si的MOSFET相比，存在载子的迁移率低的问题。作为其原因之一，认为在形成于SiC层中的杂质区域中形成了通道。
例如，因离子注入而打乱了SiC结晶性(并进对称性)，载子的迁移率下降。而且，因库仑散射，载子的迁移率下降，所述库仑散射是由因离子注入而在SiC层中产生的结晶缺陷中被捕获的电荷所引起。而且，因粗糙度散射，载子的迁移率下降，所述粗糙度散射是由离子注入而产生的SiC层表面的凹凸所引起。
本实施方式的MOSFET100在未被离子注入杂质的表面区域32形成通道。因此，不会产生由离子注入而引起的结晶性的混乱、库仑散射或粗糙度散射。由此，载子的迁移率提高。
于本实施方式的MOSFET100的断开动作时，因表面区域32完全空乏化，而MOSFET100切断。
从使表面区域32完全空乏化的观点考虑，在将由基底区域26夹着的部分的表面区域32的SiC层10的表面的宽度(图2/图3中的“w”)设为w[μm]，基底区域26的p型杂质的杂质浓度设为NA[cm-3]，表面区域32的n型杂质的杂质浓度设为ND[cm-3]，Vbi(内建电位)＝3.2[V]，q(基本电荷)＝1.602×10-19[C]，ε0(真空的比介电常数)＝8.854×10-14[F/cm]，ε(SiC的比介电常数)＝9.7的情况下，理想的是满足下述不等式。
Figure GDA0002055730170000061
因满足所述不等式，表面区域32利用从两侧延伸的空乏层而完全空乏化。
例如，在使NA在5×1015～5×1016[cm-3]，ND在5×1015～5×1016[cm-3]的范围内变化的情况下，w的最大值为1.6μm。此时，NA为5×1016[cm-3]，ND为5×1015[cm-3]。因此，有基底区域26夹着的部分的表面区域32的SiC层10的表面的宽度理想的是1.6μm以下。
而且，在MOSFET100的断开动作时，从使表面区域32完全空乏化的观点考虑，由基底区域26夹着的部分的表面区域32的宽度理想的是在从SiC层10的表面朝向背面的方向上变窄。例如，如图3所示，理想的是表面区域32具备倒三角形的形状。因表面区域32的宽度在深度方向上变窄，所以从表面区域32的两侧延伸的空乏层容易闭合。
而且，从使表面区域32完全空乏化的观点考虑，由基底区域26夹着的部分的表面区域32的SiC层10的表面的宽度(图3中的“w”)理想的是小于由基底区域26夹着的部分的表面区域32的以SiC层10的表面为基准的深度(图3中的“d”)。因表面区域32的SiC层10的表面的宽度相对于深度较窄，由此因从表面区域32的两侧延伸的空乏层，表面区域32容易闭合。
而且，表面区域32的结晶缺陷密度理想的是低于基底区域26的结晶缺陷密度。结晶缺陷引起的载子的库仑散射得到抑制，载子的迁移率提高。根据本实施方式的制造方法，能够降低表面区域32的结晶缺陷密度。
另外，表面区域32及基底区域26的杂质浓度例如能够利用次级离子质谱法(Secondary Ion Mass Spectrometry：SIMS)进行测定。而且，表面区域32的宽度或深度例如能够使用扫描电容显微术(Scanning Capacitance Microscopy：SCM)进行测定。而且，表面区域32与漂移区域24的杂质浓度的大小例如能够利用SCM进行判定。
而且，表面区域32及基底区域26的结晶缺陷密度的大小例如能够利用穿透式电子显微镜法(Transmission Electron Microscope：TEM)进行判定。
本实施方式的MOSFET100能够使载子迁移率高的表面区域32与基底区域26的形成同时地形成。因此，本实施方式的MOSFET100能够容易地制造。
以上，根据本实施方式的MOSFET100，能够提高通道的载子迁移率。
(第2实施方式)
本实施方式的半导体装置在第1面，在第4SiC区域与第3SiC区域之间设置第2SiC区域，除该点以外与第1实施方式相同。因此，关于与第1实施方式重复的内容省略记述。
图7是表示作为本实施方式的半导体装置的MOSFET的构成的示意剖视图。图8是表示作为本实施方式的半导体装置的MOSFET的构成的示意俯视图。图7是图8的D-D'剖面。
本实施方式的MOSFET200为DIMOSFET。MOSFET200为以电子为载子的垂直型n通道型MOSFET。
MOSFET200在SiC层10的表面，在表面区域32与源极区域28之间设置着基底区域26。通过设置着p型基底区域26，与无p型基底区域26的情况相比，MOSFET200的断开动作时的切断特性提高。
根据本实施方式的MOSFET200，利用与第1实施方式相同的作用，能够提高通道的载子迁移率。而且，断开动作时的切断特性提高。
第1及第2实施方式中，例示了4H-SiC作为SiC衬底的情况，还能够使用3C-SiC、6H-SiC等其他结晶形。
第1及第2实施方式中，例示了氮(N)及磷(P)作为n型杂质，但也能够应用砷(As)、锑(Sb)等。而且，例示了铝(Al)作为p型杂质，但也能够使用硼(B)。
第1及第2实施方式中，以垂直型MOSFET为半导体装置为例进行了说明，但只要为具有MIS(Metal Insulator Semiconductor，金属绝缘体半导体)构造的晶体管的半导体装置，则不限于垂直型MOSFET，均能够应用本发明。例如，也能够应用于横置式MOSFET。而且，例如，垂直型IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极晶体管)中也能够应用本发明。
第1及第2实施方式中，以n型为第1导电型、p型为第2导电型为例进行了说明，但也能够将第1导电型设为p型，将第2导电型设为n型。该情况下，晶体管为以电洞为载子的p通道型晶体管。
对本发明的几个实施方式进行了说明，但这些实施方式是作为示例而提示，并不欲意限定发明的范围。这些新颖的实施方式能够以其他各种方式实施，能够在不脱离发明的主旨的范围内进行各种省略、置换、变更。这些实施方式及其变化包含在发明的范围或主旨内，并且包含在权利要求书中所记载的发明及其均等的范围内。

Claims (9)

1.一种半导体装置，其特征在于包括：
SiC层，具有第1面及第2面；
栅极绝缘膜，设置于所述第1面上；
栅极电极，设置于所述栅极绝缘膜上；
第1导电型的第1SiC区域，设置于所述SiC层内，且一部分设置于所述第1面；
第2导电型的第2SiC区域，设置于所述第1SiC区域内，且一部分设置于所述第1面；
第1导电型的第3SiC区域，设置于所述第2SiC区域内，且一部分设置于所述第1面；及
第1导电型的第4SiC区域，设置于所述第2SiC区域与所述栅极绝缘膜之间，在所述第1面由所述第2SiC区域夹着，且在所述第1面设置于所述第1SiC区域与所述第3SiC区域之间；
由所述第2SiC区域夹着的部分的所述第4SiC区域的宽度在从所述第1面朝向所述第2面的方向上变窄。
2.根据权利要求1所述的半导体装置，其特征在于：
在所述第1面，所述第4SiC区域与所述第3SiC区域相接。
3.一种半导体装置，其特征在于包括：
SiC层，具有第1面及第2面；
栅极绝缘膜，设置于所述第1面上；
栅极电极，设置于所述栅极绝缘膜上；
第1导电型的第1SiC区域，设置于所述SiC层内，且一部分设置于所述第1面；
第2导电型的第2SiC区域，设置于所述第1SiC区域内，且一部分设置于所述第1面；
第1导电型的第3SiC区域，设置于所述第2SiC区域内，且一部分设置于所述第1面；及
第1导电型的第4SiC区域，设置于所述第2SiC区域与所述栅极绝缘膜之间，在所述第1面由所述第2SiC区域夹着，且在所述第1面设置于所述第1SiC区域与所述第3SiC区域之间；
在所述第1面，所述第4SiC区域与所述第3SiC区域之间设置着所述第2SiC区域。
4.一种半导体装置，其特征在于包括：
SiC层，具有第1面及第2面；
栅极绝缘膜，设置于所述第1面上；
栅极电极，设置于所述栅极绝缘膜上；
第1导电型的第1SiC区域，设置于所述SiC层内，且一部分设置于所述第1面；
第2导电型的第2SiC区域，设置于所述第1SiC区域内，且一部分设置于所述第1面；
第1导电型的第3SiC区域，设置于所述第2SiC区域内，且一部分设置于所述第1面；及
第1导电型的第4SiC区域，设置于所述第2SiC区域与所述栅极绝缘膜之间，在所述第1面由所述第2SiC区域夹着，且在所述第1面设置于所述第1SiC区域与所述第3SiC区域之间；
在将由所述第2SiC区域夹着的部分的所述第4SiC区域的所述第1面的宽度设为w[μm]，所述第2SiC区域的第2导电型杂质的杂质浓度设为NA[cm-3]，所述第4SiC区域的第1导电型杂质的杂质浓度设为ND[cm-3]，Vbi＝3.2[V]，q＝1.602×10-19[C]，ε0＝8.854×10-14[F/cm]，ε＝9.7的情况下，满足下述不等式：
Figure FDA0002364251480000021
5.一种半导体装置，其特征在于包括：
SiC层，具有第1面及第2面；
栅极绝缘膜，设置于所述第1面上；
栅极电极，设置于所述栅极绝缘膜上；
第1导电型的第1SiC区域，设置于所述SiC层内，且一部分设置于所述第1面；
第2导电型的第2SiC区域，设置于所述第1SiC区域内，且一部分设置于所述第1面；
第1导电型的第3SiC区域，设置于所述第2SiC区域内，且一部分设置于所述第1面；及
第1导电型的第4SiC区域，设置于所述第2SiC区域与所述栅极绝缘膜之间，在所述第1面由所述第2SiC区域夹着，且在所述第1面设置于所述第1SiC区域与所述第3SiC区域之间；
由所述第2SiC区域夹着的部分的所述第4SiC区域的所述第1面的宽度为1.6μm以下。
6.根据权利要求1、3、4、5中任一项所述的半导体装置，其特征在于：
所述第4SiC区域的结晶缺陷密度低于所述第2SiC区域的结晶缺陷密度。
7.一种半导体装置，其特征在于包括：
SiC层，具有第1面及第2面；
栅极绝缘膜，设置于所述第1面上；
栅极电极，设置于所述栅极绝缘膜上；
第1导电型的第1SiC区域，设置于所述SiC层内，且一部分设置于所述第1面；
第2导电型的第2SiC区域，设置于所述第1SiC区域内，且一部分设置于所述第1面；
第1导电型的第3SiC区域，设置于所述第2SiC区域内，且一部分设置于所述第1面；及
第1导电型的第4SiC区域，设置于所述第2SiC区域与所述栅极绝缘膜之间，在所述第1面由所述第2SiC区域夹着，且在所述第1面设置于所述第1SiC区域与所述第3SiC区域之间；
由所述第2SiC区域夹着的部分的所述第4SiC区域的宽度小于由所述第2SiC区域夹着的部分的所述第4SiC区域的以所述第1面为基准的深度。
8.根据权利要求1、3、4、5、7中任一项所述的半导体装置，其特征在于：
所述第4SiC区域的第1导电型杂质的杂质浓度与所述第1SiC区域的第1导电型杂质的杂质浓度大致相同。
9.根据权利要求1、3、4、5、7中任一项所述的半导体装置，其特征在于：
所述栅极绝缘膜为氧化硅膜。
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