US9786742B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US9786742B2
US9786742B2 US15/067,438 US201615067438A US9786742B2 US 9786742 B2 US9786742 B2 US 9786742B2 US 201615067438 A US201615067438 A US 201615067438A US 9786742 B2 US9786742 B2 US 9786742B2
Authority
US
United States
Prior art keywords
sic region
region
sic
plane
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/067,438
Other versions
US20170077237A1 (en
Inventor
Takuma Suzuki
Hiroshi Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KONO, HIROSHI, SUZUKI, TAKUMA
Publication of US20170077237A1 publication Critical patent/US20170077237A1/en
Application granted granted Critical
Publication of US9786742B2 publication Critical patent/US9786742B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • Embodiments described herein relate generally to semiconductor devices.
  • SiC Silicon carbide
  • SiC has the following excellent physical properties: a band gap is three times wider than that of silicon (Si); breakdown field strength is about ten times more than that of Si; and thermal conductivity is about three times more than that of Si. The use of these characteristics makes it possible to achieve a semiconductor device which has low power consumption and can operate at a high temperature.
  • a metal oxide semiconductor field effect transistor (MOSFET) using SiC has a problem that the carrier mobility of a channel is lower than that in a MOSFET using Si.
  • FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device according to a first embodiment.
  • FIG. 2 is a plan view schematically illustrating the semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view schematically illustrating the semiconductor device according to the first embodiment.
  • FIG. 4 is a cross-sectional view schematically illustrating the semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view schematically illustrating the semiconductor device which is being manufactured in a semiconductor device manufacturing method according to the first embodiment.
  • FIG. 6 is a cross-sectional view schematically illustrating the semiconductor device which is being manufactured in the semiconductor device manufacturing method according to the first embodiment.
  • FIG. 7 is a cross-sectional view schematically illustrating a semiconductor device according to a second embodiment.
  • FIG. 8 is a plan view schematically illustrating the semiconductor device according to the second embodiment.
  • a semiconductor device includes: a SiC layer having a first plane and a second plane; a gate insulating film provided on the first plane; a gate electrode provided on the gate insulating film; a first SiC region of a first conductivity type provided in the SiC layer, and the first SiC region having a portion in contact with the first plane; a second SiC region of a second conductivity type provided in the SiC layer, a part of the second SiC region provided between the first SiC region and the first plane, and a part of the second SiC region being in contact with the first plane; a third SiC region of the first conductivity type provided in the SiC layer, apart of the third SiC region provided between the second SiC region and the first plane, and a part of the third SiC region being in contact with the first plane; and a fourth SiC region of the first conductivity type provided in the SiC layer, the fourth SiC region provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC
  • n ++ , n + , n + , n ⁇ , p ++ , p + , p, and p ⁇ indicate the relative impurity concentrations of each conductivity type. That is, n ++ indicates n-type impurity concentration that is relatively higher than that of n + , n + indicates n-type impurity concentration that is relatively higher than that of n, and n ⁇ indicates n-type impurity concentration that is relatively lower than that of n.
  • p ++ indicates p-type impurity concentration that is relatively higher than that of p +
  • p + indicates p-type impurity concentration that is relatively higher than that of p
  • p ⁇ indicates p-type impurity concentration that is relatively lower than that of p.
  • an n ++ type, an n + type, and an n ⁇ type are simply referred to as an n type
  • a p ++ type, a p + type, and a p ⁇ type are simply referred to as a p type.
  • a semiconductor device includes: a SiC layer having a first plane and a second plane; a gate insulating film provided on the first plane; a gate electrode provided on the gate insulating film; a first SiC region of a first conductivity type which is provided in the SiC layer and has a portion provided in the first plane; a second SiC region of a second conductivity type which is provided in the first SiC region and has a portion provided in the first plane; a third SiC region of the first conductivity type which is provided in the second SiC region and has a portion provided in the first plane; and a fourth SiC region of the first conductivity type which is provided between the second SiC region and the gate insulating film, is interposed between the second SiC regions in the first plane, and is provided between the first SiC region and the third SiC region in the first plane.
  • FIGS. 1, 3, and 4 are cross-sectional views schematically illustrating the structure of a MOSFET which is the semiconductor device according to this embodiment.
  • FIG. 2 is a plan view schematically illustrating the structure of the MOSFET which is the semiconductor device according to this embodiment.
  • FIG. 1 is a cross-sectional view taken along the line A-A′ of FIG. 2 .
  • FIG. 3 is a cross-sectional view taken along the line B-B′ of FIG. 2 .
  • FIG. 4 is a cross-sectional view taken along the line C-C′ of FIG. 2 .
  • a MOSFET 100 according to this embodiment is, for example, a double implantation MOSFET (DIMOSFET) in which a base region (body region) and a source region are formed by ion implantation.
  • the MOSFET 100 is a vertical n-channel MOSFET having electrons as carriers.
  • the MOSFET 100 includes a SiC layer 10 , a source electrode 12 , a drain electrode 14 , a gate insulating film 16 , a gate electrode 18 , and an interlayer insulating film 20 .
  • the SiC layer 10 includes an n + -type drain region 22 , an n ⁇ -type drift region (first SiC region) 24 , a p-type base region (second SiC region) 26 , an n + -type source region (third SiC region) 28 , a p ⁇ -type base contact region 30 , and an n ⁇ -type front surface region (fourth SiC region) 32 .
  • the SiC layer 10 is a single crystal SiC layer.
  • the SiC layer 10 is, for example, a 4 H-SiC layer.
  • the SiC layer 10 has a first plane and a second plane.
  • the first plane is also referred to as a front surface and the second plane is also referred to as a rear surface.
  • the first plane is inclined at an angle that is equal to or greater than 0° and equal to or less than 8° with respect to the (0001) face.
  • the second plane is inclined at an angle that is equal to or greater than 0° and equal to or less than 8° with respect to the (000-1) face.
  • the (0001) face is referred to as a silicon face.
  • the (000-1) face is referred to as a carbon face.
  • the n + -type drain region 22 is provided on the rear surface of the SiC layer 10 .
  • the drain region 22 includes, for example, nitrogen (N) as n-type impurities.
  • the n-type impurity concentration of the drain region 22 is, for example, equal to or greater than 1 ⁇ 10 18 cm ⁇ 3 and equal to or less than 1 ⁇ 10 21 cm ⁇ 3 .
  • the n ⁇ -type drift region 24 is provided on the drain region 22 .
  • at least a portion of the drift region 24 is provided in the front surface of the SiC layer 10 .
  • other SiC regions may be provided between the drift region 24 and the front surface of the SiC layer 10 .
  • the drift region 24 includes, for example, nitrogen (N) as n-type impurities.
  • the n-type impurity concentration of the drift region 24 is, for example, equal to or greater than 5 ⁇ 10 15 cm ⁇ 3 and equal to or less than 5 ⁇ 10 16 cm ⁇ 3 .
  • the thickness of the drift region 24 is, for example, equal to or greater than 4 ⁇ m and equal to or less than 150 ⁇ m.
  • the p-type base region 26 is provided in the drift region 24 .
  • at least a portion of the base region 26 is provided in the front surface of the SiC layer 10 .
  • other SiC regions may be provided between the base region 26 and the front surface of the SiC layer 10 .
  • the base region 26 includes, for example, aluminum (Al) as p-type impurities.
  • the p-type impurity concentration of the base region 26 is, for example, equal to or greater than 5 ⁇ 10 15 cm ⁇ 3 and equal to or less than 1 ⁇ 10 19 cm ⁇ 3 .
  • the depth of the base region 26 is, for example, equal to or greater than 0.4 ⁇ m and equal to or less than 0.8 ⁇ m.
  • the n + -type source region 28 is provided in the base region 26 .
  • at least a portion of the source region 28 is provided in the front surface of the SiC layer 10 .
  • other SiC regions may be provided between the source region 28 and the front surface of the SiC layer 10 .
  • the source region 28 includes, for example, phosphor (P) as n-type impurities.
  • the n-type impurity concentration of the source region 28 is, for example, equal to or greater than 1 ⁇ 10 18 cm ⁇ 3 and equal to or less than 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of the source region 28 is less than the depth of the base region 26 and is, for example, equal to or greater than 0.2 ⁇ m and equal to or less than 0.4 ⁇ m.
  • the p + -type base contact region 30 is provided in the base region 26 .
  • the base contact region 30 is provided so as to come into contact with the source region 28 .
  • the base contact region 30 includes, for example, aluminum (Al) as p-type impurities.
  • the p-type impurity concentration of the base contact region 30 is, for example, equal to or greater than 1 ⁇ 10 18 cm ⁇ 3 and equal to or less than 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of the base contact region 30 is less than the depth of the base region 26 and is, for example, equal to or greater than 0.2 ⁇ m and equal to or less than 0.4 ⁇ m.
  • the n ⁇ -type front surface region 32 is provided between the base region 26 and the gate insulating film 16 .
  • the front surface region 32 is interposed between the base regions 26 in the front surface of the SiC layer 10 .
  • the front surface region 32 and the base region 26 are alternately formed in the front surface of the SiC layer 10 .
  • other SiC regions may be provided between the n ⁇ -type front surface region 32 and the front surface of the SiC layer 10 .
  • the front surface region 32 is interposed between the drift region 24 and the source region 28 in the front surface of the SiC layer 10 .
  • the front surface region 32 comes into contact with the source region 28 in the front surface of the SiC layer 10 .
  • the base region 26 is also interposed between the drift region 24 and the source region 28 in the front surface of the SiC layer 10 .
  • the front surface region 32 includes, for example, nitrogen (N) as n-type impurities.
  • the n-type impurity concentration of the front surface region 32 is lower than the n-type impurity concentration of the source region 28 .
  • the n-type impurity concentration of the front surface region 32 is, for example, equal to or greater than 5 ⁇ 10 15 cm ⁇ 3 and equal to or less than 5 ⁇ 10 16 cm ⁇ 3 .
  • the width (“w” in FIGS. 2 and 3 ) of the front surface region 32 in the front surface of the SiC layer 10 is, for example, equal to or greater than 0.05 ⁇ m and equal to or less than 2.0 ⁇ m.
  • the depth of the front surface region 32 is less than the depth of the source region 28 and is, for example, equal to or greater than 0.05 ⁇ m and equal to or less than 0.15 ⁇ m.
  • the gate insulating film 16 is provided on the front surface of the SiC layer 10 .
  • the gate insulating film 16 is provided on the drift region 24 , the base region 26 , the source region 28 , and the front surface region 32 .
  • the gate insulating film 16 is, for example, a silicon oxide film.
  • a high-k insulating film high-permittivity insulating film
  • the gate electrode 18 is provided on the gate insulating film 16 .
  • the gate electrode 18 is a conductive layer.
  • the gate electrode 18 is, for example, a polysilicon film including p-type impurities or n-type impurities.
  • the interlayer insulating film 20 is provided on the gate electrode 18 .
  • the interlayer insulating film 20 is, for example, a silicon oxide film.
  • the front surface region 32 which is interposed between the source region 28 and the drift region 24 below the gate electrode 18 functions as a channel region of the MOSFET 100 .
  • the source electrode 12 is provided on the front surface of the SiC layer 10 .
  • the source electrode 12 is electrically connected to the source region 28 and the base contact region 30 .
  • the source electrode 12 comes into contact with the source region 28 and the base contact region 30 .
  • the source electrode 12 also has a function of applying potential to the base region 26 .
  • the source electrode 12 includes metal.
  • Metal forming the source electrode 12 has, for example, a stacked structure of titanium (Ti) and aluminum (Al).
  • the source electrode 12 may include metal silicide or metal carbide which comes into contact with the SiC layer 10 .
  • the drain electrode 14 is provided on the rear surface of the SiC layer 10 .
  • the drain electrode 14 is electrically connected to the drain region 22 .
  • the drain electrode 14 is made of, for example, metal.
  • the metal forming the drain electrode 14 has, for example, a stacked structure of nickel (Ni) and gold (Au).
  • the drain electrode 14 may include metal silicide or metal carbide which comes into contact with the rear surface of the SiC layer 10 .
  • FIGS. 5 and 6 are cross-sectional views schematically illustrating the semiconductor device which is being manufactured in the semiconductor device manufacturing method according to this embodiment.
  • the drift region 24 is formed on the drain region 22 by epitaxial growth ( FIG. 5 ).
  • the mask member 50 is a silicon oxide film which is formed by, for example, a chemical vapor deposition (CVD) method.
  • Al ions which are p-type impurity ions, are implanted into the drift region 24 , using the mask member 50 as a mask ( FIG. 6 ).
  • the base region 26 is formed by the ion implantation.
  • the aluminum ions are implanted by, for example, oblique ion implantation. No aluminum is introduced into a region covered with the mask member 50 and the base region 26 is not formed in the region. In other words, a portion of the drift region 24 which is covered with the mask member 50 remains, without being removed, and the front surface region 32 is formed in the remaining portion. As a result, the n-type impurity concentration of the front surface region 32 is substantially equal to the n-type impurity concentration of the drift region 24 .
  • the mask member 50 is removed. Then, the n + -type source region 28 , the p + -type base contact region 30 , the gate insulating film 16 , the gate electrode 18 , the interlayer insulating film 20 , the source electrode 12 , and the drain electrode 14 are formed by a known process. In this way, the MOSFET 100 is manufactured.
  • the MOSFET using SiC has a problem that the mobility of carriers is lower than that in a MOSFET using Si. It is considered that one of the causes of the problem is the formation of a channel in the impurity region formed in the SiC layer.
  • the crystallinity (translation symmetry) of SiC is disrupted by ion implantation and the mobility of carriers is reduced.
  • the mobility of carriers is reduced by Coulomb scattering caused by charge which is trapped in crystal defects that generated in the SiC layer due to ion implantation.
  • the mobility of carriers is reduced by roughness scattering caused by the unevenness of the front surface of the SiC layer which occurs due to ion implantation.
  • a channel is formed in the front surface region 32 into which no impurity ions are implanted. Therefore, the disruption of crystallinity, Coulomb scattering, or roughness scattering caused by ion implantation does not occur. As a result, the mobility of carriers is improved.
  • the front surface region 32 is completely depleted and the MOSFET 100 is turned off.
  • the width (“w” in FIGS. 2 and 3 ) of the front surface region 32 interposed between the base regions 26 in the front surface of the SiC layer 10 is w [ ⁇ m]
  • the p-type impurity concentration of the base region 26 is N A [cm ⁇ 3 ]
  • the n-type impurity concentration of the front surface region 32 is N D [cm ⁇ 3 ]
  • built-in potential (Vbi) is 3.2 [V]
  • an elementary charge (q) is 1.602 ⁇ 10 ⁇ 19 [C]
  • the specific permittivity of vacuum ( ⁇ 0 ) is 8.854 ⁇ 10 ⁇ 14 [F/cm]
  • the specific permittivity of SiC ( ⁇ ) is 9.7
  • w is the width of a portion of the n ⁇ -type front surface region 32 which is close to the front surface of the SiC layer 10 .
  • the front surface region 32 is completely depleted by depletion layers which are spread from both sides of the front surface region 32 .
  • the width of the front surface region 32 interposed between the base regions 26 in the front surface of the SiC layer 10 be equal to or less than 1.6 ⁇ m.
  • the width of the front surface region 32 interposed between the base regions 26 be gradually reduced in a direction from the front surface to the rear surface of the SiC layer 10 in order to completely deplete the front surface region 32 during the turn-off operation of the MOSFET 100 .
  • the front surface region 32 have an inverted triangle shape. Since the width of the front surface region 32 is gradually reduced in the depth direction, the depletion layers which are spread from both sides of the front surface region 32 are likely to be blocked.
  • the width (“w” in FIG. 3 ) of the front surface region 32 interposed between the base regions 26 in the front surface of the SiC layer 10 be less than the depth (“d” in FIG. 3 ) of the front surface region 32 interposed between the base regions 26 from the front surface of the SiC layer 10 , in order to completely deplete the front surface region 32 . Since the width of the front surface region 32 in the front surface of the SiC layer 10 is less than the depth thereof, the front surface region 32 is likely to be blocked by the depletion layers which are spread from both sides of the front surface region 32 .
  • the density of crystal defects in the front surface region 32 be lower than the density of crystal defects in the base region 26 .
  • the Coulomb scattering of carriers due to crystal defects is suppressed and the mobility of carriers is improved. According to the manufacturing method of this embodiment, it is possible to reduce the density of crystal defects in the front surface region 32 .
  • the impurity concentration of the front surface region 32 and the base region 26 can be measured by, for example, secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • the width or depth of the front surface region 32 can be measured by, for example, scanning capacitance microscopy (SCM).
  • SCM scanning capacitance microscopy
  • the magnitude relationship between the impurity concentrations of the front surface region 32 and the drift region 24 can be determined by, for example, SCM.
  • the magnitude relationship between the densities of crystal defects in the front surface region 32 and the base region 26 can be determined by, for example, a transmission electron microscope (TEM) method.
  • TEM transmission electron microscope
  • the front surface region 32 with high carrier mobility can be formed at the same time as the base region 26 . Therefore, it is possible to easily manufacture the MOSFET 100 according to this embodiment.
  • the MOSFET 100 of this embodiment it is possible to improve the carrier mobility of a channel.
  • a semiconductor device according to a second embodiment is similar to the semiconductor device according to the first embodiment except that the second SiC region is provided between the fourth SiC region and the third SiC region in the first plane. Therefore, the description of the same content as that in the first embodiment will not be repeated.
  • FIG. 7 is a cross-sectional view schematically illustrating the structure of a MOSFET which is the semiconductor device according to this embodiment.
  • FIG. 8 is a plan view schematically illustrating the structure of the MOSFET which is the semiconductor device according to this embodiment.
  • FIG. 7 is a cross-sectional view taken along the line D-D′ of FIG. 8 .
  • a MOSFET 200 according to this embodiment is a DIMOSFET.
  • the MOSFET 200 is a vertical n-channel MOSFET having electrons as carriers.
  • a base region 26 is provided between a front surface region 32 and a source region 28 in the front surface of a SiC layer 10 .
  • cutoff characteristics during the turn-off operation of the MOSFET 200 are improved, as compared to a case in which the p-type base region 26 is not provided.
  • the carrier mobility of a channel can be improved by the same function as that in the first embodiment.
  • the cutoff characteristics during the turn-off operation of the MOSFET 200 are improved.
  • the 4 H-SiC substrate is used as the SiC substrate.
  • other crystal forms such as 3C-SiC and 6H-SiC, may be used.
  • nitrogen (N) and phosphor (P) are given as examples of the n-type impurities.
  • arsenic (As) and antimony (Sb) may be used as the n-type impurities.
  • aluminum (Al) is given as an example of the p-type impurities.
  • boron (B) may be used.
  • the vertical MOSFET is given as an example of the semiconductor device.
  • the invention is not limited to the vertical MOSFET.
  • the invention can be applied to other semiconductor devices including transistors having a metal insulator semiconductor (MIS) structure.
  • MIS metal insulator semiconductor
  • the invention can also be applied to a horizontal MOSFET.
  • the invention can be applied to a vertical insulated gate bipolar transistor (IGBT).
  • IGBT vertical insulated gate bipolar transistor
  • the first conductivity type is an n type and the second conductivity type is a p type.
  • the first conductivity type may be a p type and the second conductivity type may be an n type.
  • the transistor is a p-channel transistor having holes as carriers.

Abstract

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-179328, filed on Sep. 11, 2015, the entire contents of which are incorporated herein by reference.
FIELD
Embodiments described herein relate generally to semiconductor devices.
BACKGROUND
Silicon carbide (SiC) is expected to be used as a material for a next-generation semiconductor device. SiC has the following excellent physical properties: a band gap is three times wider than that of silicon (Si); breakdown field strength is about ten times more than that of Si; and thermal conductivity is about three times more than that of Si. The use of these characteristics makes it possible to achieve a semiconductor device which has low power consumption and can operate at a high temperature.
A metal oxide semiconductor field effect transistor (MOSFET) using SiC has a problem that the carrier mobility of a channel is lower than that in a MOSFET using Si.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device according to a first embodiment.
FIG. 2 is a plan view schematically illustrating the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view schematically illustrating the semiconductor device according to the first embodiment.
FIG. 4 is a cross-sectional view schematically illustrating the semiconductor device according to the first embodiment.
FIG. 5 is a cross-sectional view schematically illustrating the semiconductor device which is being manufactured in a semiconductor device manufacturing method according to the first embodiment.
FIG. 6 is a cross-sectional view schematically illustrating the semiconductor device which is being manufactured in the semiconductor device manufacturing method according to the first embodiment.
FIG. 7 is a cross-sectional view schematically illustrating a semiconductor device according to a second embodiment.
FIG. 8 is a plan view schematically illustrating the semiconductor device according to the second embodiment.
 DETAILED DESCRIPTION
A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane; a gate insulating film provided on the first plane; a gate electrode provided on the gate insulating film; a first SiC region of a first conductivity type provided in the SiC layer, and the first SiC region having a portion in contact with the first plane; a second SiC region of a second conductivity type provided in the SiC layer, a part of the second SiC region provided between the first SiC region and the first plane, and a part of the second SiC region being in contact with the first plane; a third SiC region of the first conductivity type provided in the SiC layer, apart of the third SiC region provided between the second SiC region and the first plane, and a part of the third SiC region being in contact with the first plane; and a fourth SiC region of the first conductivity type provided in the SiC layer, the fourth SiC region provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions in the first plane, and the fourth SiC region provided between the first SiC region and the third SiC region in the first plane.
Hereinafter, embodiments of the invention will be described with reference to the drawings. In the following description, for example, the same or similar members are denoted by the same reference numerals and the description thereof will not be repeated.
In the following description, n++, n+, n+, n−, p++, p+, p, and p− indicate the relative impurity concentrations of each conductivity type. That is, n++ indicates n-type impurity concentration that is relatively higher than that of n+, n+ indicates n-type impurity concentration that is relatively higher than that of n, and n− indicates n-type impurity concentration that is relatively lower than that of n. In addition, p++ indicates p-type impurity concentration that is relatively higher than that of p+, p+ indicates p-type impurity concentration that is relatively higher than that of p, and p− indicates p-type impurity concentration that is relatively lower than that of p. In some cases, an n++ type, an n+ type, and an n− type are simply referred to as an n type, and a p++ type, a p+ type, and a p− type are simply referred to as a p type.
First Embodiment
A semiconductor device according to a first embodiment includes: a SiC layer having a first plane and a second plane; a gate insulating film provided on the first plane; a gate electrode provided on the gate insulating film; a first SiC region of a first conductivity type which is provided in the SiC layer and has a portion provided in the first plane; a second SiC region of a second conductivity type which is provided in the first SiC region and has a portion provided in the first plane; a third SiC region of the first conductivity type which is provided in the second SiC region and has a portion provided in the first plane; and a fourth SiC region of the first conductivity type which is provided between the second SiC region and the gate insulating film, is interposed between the second SiC regions in the first plane, and is provided between the first SiC region and the third SiC region in the first plane.
FIGS. 1, 3, and 4 are cross-sectional views schematically illustrating the structure of a MOSFET which is the semiconductor device according to this embodiment. FIG. 2 is a plan view schematically illustrating the structure of the MOSFET which is the semiconductor device according to this embodiment. FIG. 1 is a cross-sectional view taken along the line A-A′ of FIG. 2. FIG. 3 is a cross-sectional view taken along the line B-B′ of FIG. 2. FIG. 4 is a cross-sectional view taken along the line C-C′ of FIG. 2.
A MOSFET 100 according to this embodiment is, for example, a double implantation MOSFET (DIMOSFET) in which a base region (body region) and a source region are formed by ion implantation. The MOSFET 100 is a vertical n-channel MOSFET having electrons as carriers.
The MOSFET 100 includes a SiC layer 10, a source electrode 12, a drain electrode 14, a gate insulating film 16, a gate electrode 18, and an interlayer insulating film 20. The SiC layer 10 includes an n+-type drain region 22, an n−-type drift region (first SiC region) 24, a p-type base region (second SiC region) 26, an n+-type source region (third SiC region) 28, a p−-type base contact region 30, and an n−-type front surface region (fourth SiC region) 32.
The SiC layer 10 is a single crystal SiC layer. The SiC layer 10 is, for example, a 4H-SiC layer.
The SiC layer 10 has a first plane and a second plane. Hereinafter, the first plane is also referred to as a front surface and the second plane is also referred to as a rear surface.
For example, the first plane is inclined at an angle that is equal to or greater than 0° and equal to or less than 8° with respect to the (0001) face. For example, the second plane is inclined at an angle that is equal to or greater than 0° and equal to or less than 8° with respect to the (000-1) face. The (0001) face is referred to as a silicon face. The (000-1) face is referred to as a carbon face.
The n+-type drain region 22 is provided on the rear surface of the SiC layer 10. The drain region 22 includes, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drain region 22 is, for example, equal to or greater than 1×1018 cm−3 and equal to or less than 1×1021 cm−3.
The n−-type drift region 24 is provided on the drain region 22. For example, at least a portion of the drift region 24 is provided in the front surface of the SiC layer 10. For example, other SiC regions may be provided between the drift region 24 and the front surface of the SiC layer 10.
The drift region 24 includes, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the drift region 24 is, for example, equal to or greater than 5×1015 cm−3 and equal to or less than 5×1016 cm−3. The thickness of the drift region 24 is, for example, equal to or greater than 4 μm and equal to or less than 150 μm.
The p-type base region 26 is provided in the drift region 24. For example, at least a portion of the base region 26 is provided in the front surface of the SiC layer 10. For example, other SiC regions may be provided between the base region 26 and the front surface of the SiC layer 10.
The base region 26 includes, for example, aluminum (Al) as p-type impurities. The p-type impurity concentration of the base region 26 is, for example, equal to or greater than 5×1015 cm−3 and equal to or less than 1×1019 cm−3. The depth of the base region 26 is, for example, equal to or greater than 0.4 μm and equal to or less than 0.8 μm.
The n+-type source region 28 is provided in the base region 26. For example, at least a portion of the source region 28 is provided in the front surface of the SiC layer 10. For example, other SiC regions may be provided between the source region 28 and the front surface of the SiC layer 10.
The source region 28 includes, for example, phosphor (P) as n-type impurities. The n-type impurity concentration of the source region 28 is, for example, equal to or greater than 1×1018 cm−3 and equal to or less than 1×1021 cm−3. The depth of the source region 28 is less than the depth of the base region 26 and is, for example, equal to or greater than 0.2 μm and equal to or less than 0.4 μm.
The p+-type base contact region 30 is provided in the base region 26. The base contact region 30 is provided so as to come into contact with the source region 28.
The base contact region 30 includes, for example, aluminum (Al) as p-type impurities. The p-type impurity concentration of the base contact region 30 is, for example, equal to or greater than 1×1018 cm−3 and equal to or less than 1×1021 cm−3.
The depth of the base contact region 30 is less than the depth of the base region 26 and is, for example, equal to or greater than 0.2 μm and equal to or less than 0.4 μm.
The n−-type front surface region 32 is provided between the base region 26 and the gate insulating film 16. For example, the front surface region 32 is interposed between the base regions 26 in the front surface of the SiC layer 10. The front surface region 32 and the base region 26 are alternately formed in the front surface of the SiC layer 10. For example, other SiC regions may be provided between the n−-type front surface region 32 and the front surface of the SiC layer 10.
In addition, the front surface region 32 is interposed between the drift region 24 and the source region 28 in the front surface of the SiC layer 10. The front surface region 32 comes into contact with the source region 28 in the front surface of the SiC layer 10. The base region 26 is also interposed between the drift region 24 and the source region 28 in the front surface of the SiC layer 10.
The front surface region 32 includes, for example, nitrogen (N) as n-type impurities. The n-type impurity concentration of the front surface region 32 is lower than the n-type impurity concentration of the source region 28. The n-type impurity concentration of the front surface region 32 is, for example, equal to or greater than 5×1015 cm−3 and equal to or less than 5×1016 cm−3.
The width (“w” in FIGS. 2 and 3) of the front surface region 32 in the front surface of the SiC layer 10 is, for example, equal to or greater than 0.05 μm and equal to or less than 2.0 μm.
The depth of the front surface region 32 is less than the depth of the source region 28 and is, for example, equal to or greater than 0.05 μm and equal to or less than 0.15 μm.
The gate insulating film 16 is provided on the front surface of the SiC layer 10. The gate insulating film 16 is provided on the drift region 24, the base region 26, the source region 28, and the front surface region 32. The gate insulating film 16 is, for example, a silicon oxide film. For example, a high-k insulating film (high-permittivity insulating film) can be applied as the gate insulating film 16.
The gate electrode 18 is provided on the gate insulating film 16. The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, a polysilicon film including p-type impurities or n-type impurities.
The interlayer insulating film 20 is provided on the gate electrode 18. The interlayer insulating film 20 is, for example, a silicon oxide film.
The front surface region 32 which is interposed between the source region 28 and the drift region 24 below the gate electrode 18 functions as a channel region of the MOSFET 100.
The source electrode 12 is provided on the front surface of the SiC layer 10. The source electrode 12 is electrically connected to the source region 28 and the base contact region 30. The source electrode 12 comes into contact with the source region 28 and the base contact region 30. The source electrode 12 also has a function of applying potential to the base region 26.
The source electrode 12 includes metal. Metal forming the source electrode 12 has, for example, a stacked structure of titanium (Ti) and aluminum (Al). The source electrode 12 may include metal silicide or metal carbide which comes into contact with the SiC layer 10.
The drain electrode 14 is provided on the rear surface of the SiC layer 10. The drain electrode 14 is electrically connected to the drain region 22.
The drain electrode 14 is made of, for example, metal. The metal forming the drain electrode 14 has, for example, a stacked structure of nickel (Ni) and gold (Au). The drain electrode 14 may include metal silicide or metal carbide which comes into contact with the rear surface of the SiC layer 10.
Next, a method for manufacturing the MOSFET 100 according to this embodiment will be described. In particular, a method for forming the front surface region 32 will be described.
FIGS. 5 and 6 are cross-sectional views schematically illustrating the semiconductor device which is being manufactured in the semiconductor device manufacturing method according to this embodiment.
The drift region 24 is formed on the drain region 22 by epitaxial growth (FIG. 5).
Then, a mask member 50 is formed on the front surface of the drift region 24. The mask member 50 is a silicon oxide film which is formed by, for example, a chemical vapor deposition (CVD) method.
Then, aluminum (Al) ions, which are p-type impurity ions, are implanted into the drift region 24, using the mask member 50 as a mask (FIG. 6). The base region 26 is formed by the ion implantation.
The aluminum ions are implanted by, for example, oblique ion implantation. No aluminum is introduced into a region covered with the mask member 50 and the base region 26 is not formed in the region. In other words, a portion of the drift region 24 which is covered with the mask member 50 remains, without being removed, and the front surface region 32 is formed in the remaining portion. As a result, the n-type impurity concentration of the front surface region 32 is substantially equal to the n-type impurity concentration of the drift region 24.
Then, the mask member 50 is removed. Then, the n+-type source region 28, the p+-type base contact region 30, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 12, and the drain electrode 14 are formed by a known process. In this way, the MOSFET 100 is manufactured.
Next, the function and effect of the semiconductor device according to the embodiment will be described.
The MOSFET using SiC has a problem that the mobility of carriers is lower than that in a MOSFET using Si. It is considered that one of the causes of the problem is the formation of a channel in the impurity region formed in the SiC layer.
For example, the crystallinity (translation symmetry) of SiC is disrupted by ion implantation and the mobility of carriers is reduced. In addition, the mobility of carriers is reduced by Coulomb scattering caused by charge which is trapped in crystal defects that generated in the SiC layer due to ion implantation. Furthermore, the mobility of carriers is reduced by roughness scattering caused by the unevenness of the front surface of the SiC layer which occurs due to ion implantation.
In the MOSFET 100 according to this embodiment, a channel is formed in the front surface region 32 into which no impurity ions are implanted. Therefore, the disruption of crystallinity, Coulomb scattering, or roughness scattering caused by ion implantation does not occur. As a result, the mobility of carriers is improved.
During the turn-off operation of the MOSFET 100 according to this embodiment, the front surface region 32 is completely depleted and the MOSFET 100 is turned off.
When the width (“w” in FIGS. 2 and 3) of the front surface region 32 interposed between the base regions 26 in the front surface of the SiC layer 10 is w [μm], the p-type impurity concentration of the base region 26 is NA [cm−3], the n-type impurity concentration of the front surface region 32 is ND [cm−3], built-in potential (Vbi) is 3.2 [V], an elementary charge (q) is 1.602×10−19 [C], the specific permittivity of vacuum (ε0) is 8.854×10−14 [F/cm], and the specific permittivity of SiC (ε) is 9.7, it is preferable that the following inequality be satisfied in order to completely deplete the front surface region 32:
w ≦ 2 × 10000 × 2 ⁢ ɛ 0 ⁢ ɛ · V bi q ⁢ N A + N D N A ⁢ N D .
For example, when other SiC regions are provided between the n−-type front surface region 32 and the SiC layer 10, w is the width of a portion of the n−-type front surface region 32 which is close to the front surface of the SiC layer 10.
When the above-mentioned inequality is satisfied, the front surface region 32 is completely depleted by depletion layers which are spread from both sides of the front surface region 32.
For example, when NA is changed in the range of 5×1015 [cm−3] to 5×106 [cm−3] and ND is changed in the range of 5×1015 [cm−3] to 5×1016 [cm−3], the maximum value of w is 1.6 μm. At that time, NA is 5×1016 [cm−3] and ND is 5×1015 [cm−3]. Therefore, it is preferable that the width of the front surface region 32 interposed between the base regions 26 in the front surface of the SiC layer 10 be equal to or less than 1.6 μm.
In addition, it is preferable that the width of the front surface region 32 interposed between the base regions 26 be gradually reduced in a direction from the front surface to the rear surface of the SiC layer 10 in order to completely deplete the front surface region 32 during the turn-off operation of the MOSFET 100. For example, as illustrated in FIG. 3, it is preferable that the front surface region 32 have an inverted triangle shape. Since the width of the front surface region 32 is gradually reduced in the depth direction, the depletion layers which are spread from both sides of the front surface region 32 are likely to be blocked.
It is preferable that the width (“w” in FIG. 3) of the front surface region 32 interposed between the base regions 26 in the front surface of the SiC layer 10 be less than the depth (“d” in FIG. 3) of the front surface region 32 interposed between the base regions 26 from the front surface of the SiC layer 10, in order to completely deplete the front surface region 32. Since the width of the front surface region 32 in the front surface of the SiC layer 10 is less than the depth thereof, the front surface region 32 is likely to be blocked by the depletion layers which are spread from both sides of the front surface region 32.
It is preferable that the density of crystal defects in the front surface region 32 be lower than the density of crystal defects in the base region 26. The Coulomb scattering of carriers due to crystal defects is suppressed and the mobility of carriers is improved. According to the manufacturing method of this embodiment, it is possible to reduce the density of crystal defects in the front surface region 32.
The impurity concentration of the front surface region 32 and the base region 26 can be measured by, for example, secondary ion mass spectrometry (SIMS). In addition, the width or depth of the front surface region 32 can be measured by, for example, scanning capacitance microscopy (SCM). The magnitude relationship between the impurity concentrations of the front surface region 32 and the drift region 24 can be determined by, for example, SCM.
The magnitude relationship between the densities of crystal defects in the front surface region 32 and the base region 26 can be determined by, for example, a transmission electron microscope (TEM) method.
In the MOSFET 100 according to this embodiment, the front surface region 32 with high carrier mobility can be formed at the same time as the base region 26. Therefore, it is possible to easily manufacture the MOSFET 100 according to this embodiment.
As described above, according to the MOSFET 100 of this embodiment, it is possible to improve the carrier mobility of a channel.
Second Embodiment
A semiconductor device according to a second embodiment is similar to the semiconductor device according to the first embodiment except that the second SiC region is provided between the fourth SiC region and the third SiC region in the first plane. Therefore, the description of the same content as that in the first embodiment will not be repeated.
FIG. 7 is a cross-sectional view schematically illustrating the structure of a MOSFET which is the semiconductor device according to this embodiment. FIG. 8 is a plan view schematically illustrating the structure of the MOSFET which is the semiconductor device according to this embodiment. FIG. 7 is a cross-sectional view taken along the line D-D′ of FIG. 8.
A MOSFET 200 according to this embodiment is a DIMOSFET. The MOSFET 200 is a vertical n-channel MOSFET having electrons as carriers.
In the MOSFET 200, a base region 26 is provided between a front surface region 32 and a source region 28 in the front surface of a SiC layer 10. When the p-type base region 26 is provided, cutoff characteristics during the turn-off operation of the MOSFET 200 are improved, as compared to a case in which the p-type base region 26 is not provided.
According to the MOSFET 200 of this embodiment, the carrier mobility of a channel can be improved by the same function as that in the first embodiment. In addition, the cutoff characteristics during the turn-off operation of the MOSFET 200 are improved.
In the first and second embodiments, the 4H-SiC substrate is used as the SiC substrate. However, other crystal forms, such as 3C-SiC and 6H-SiC, may be used.
In the first and second embodiments, nitrogen (N) and phosphor (P) are given as examples of the n-type impurities. However, for example, arsenic (As) and antimony (Sb) may be used as the n-type impurities. In addition, aluminum (Al) is given as an example of the p-type impurities. However, boron (B) may be used.
In the first and second embodiments, the vertical MOSFET is given as an example of the semiconductor device. However, the invention is not limited to the vertical MOSFET. The invention can be applied to other semiconductor devices including transistors having a metal insulator semiconductor (MIS) structure. For example, the invention can also be applied to a horizontal MOSFET. In addition, for example, the invention can be applied to a vertical insulated gate bipolar transistor (IGBT).
In the first and second embodiments, the first conductivity type is an n type and the second conductivity type is a p type. However, the first conductivity type may be a p type and the second conductivity type may be an n type. In this case, the transistor is a p-channel transistor having holes as carriers.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, semiconductor devices described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (20)

What is claimed is:
1. A semiconductor device comprising:
a SiC layer having a first plane and a second plane;
a gate insulating film provided on the first plane;
a gate electrode provided on the gate insulating film;
a first SiC region of a first conductivity type provided in the SiC layer, and the first SiC region having a portion in contact with the first plane;
a second SiC region of a second conductivity type provided in the SiC layer, the second SiC region provided between the first plane and the first SiC region, the second SiC region having a first part and a second part, the second part being in contact with the first plane, the first part being adjacent to the second part in a first direction, the first direction being parallel to the first plane;
a third SiC region of the first conductivity type provided in the SiC layer, the third SiC region provided between the second SiC region and the first plane, and a part of the third SiC region being in contact with the first plane; and
a fourth SiC region of the first conductivity type provided in the SiC layer, the fourth SiC region provided between the first part of the second SiC region and the gate insulating film, the fourth SiC region being adjacent to the second part of the second SiC region in the first direction in the first plane, the fourth SiC region provided between the first SiC region and the third SiC region in a second direction in the first plane, the second direction being perpendicular to the first direction and being parallel to the first plane, and first-conductivity-type impurity concentration of the fourth SiC region is lower than first-conductivity-type impurity concentration of the third SiC region.
2. The semiconductor device according to claim 1,
wherein the fourth SiC region and the third SiC region are in contact with each other in the first plane.
3. The semiconductor device according to claim 1,
wherein width of the fourth SiC region interposed between the second SiC regions is gradually reduced in a direction from the first plane to the second plane.
4. The semiconductor device according to claim 1,
wherein the second SiC region is provided between the fourth SiC region and the third SiC region in the first plane.
5. The semiconductor device according to claim 1,
wherein, when width of the fourth SiC region interposed between the second SiC regions in the first plane is w [μm], the second-conductivity-type impurity concentration of the second SiC region is NA [cm3], the first-conductivity-type impurity concentration of the fourth SiC region is ND [cm−3], Vbi is 3.2 [V], q is 1.602×10−19 [C], ε0 is 8.854×10−14 [F/cm], and ε is 9.7, the following inequality is satisfied:
w ≦ 2 × 10000 × 2 ⁢ ɛ 0 ⁢ ɛ · V bi q ⁢ N A + N D N A ⁢ N D .
6. The semiconductor device according to claim 1,
wherein the width of the fourth SiC region in the first direction is equal to or less than 1.6 μm.
7. The semiconductor device according to claim 1,
wherein density of crystal defects in the fourth SiC region is lower than density of crystal defects in the second SiC region.
8. The semiconductor device according to claim 1,
wherein width of the fourth SiC region in the first direction is less than depth of the fourth SiC.
9. The semiconductor device according to claim 1,
wherein the first-conductivity-type impurity concentration of the fourth SiC region is substantially equal to the first-conductivity-type impurity concentration of the first SiC region.
10. The semiconductor device according to claim 1,
wherein the gate insulating film is a silicon oxide film.
11. A semiconductor device comprising:
a SiC layer having a first plane and a second plane;
a gate insulating film provided on the first plane;
a gate electrode provided on the gate insulating film;
a first SiC region of a first conductivity type provided in the SiC layer;
a second SiC region of a second conductivity type provided in the first SiC region, the second SiC region provided between the first plane and the first SiC region, the second SiC region having a first part and a second part, the second part being in contact with the first plane, the first part being adjacent to the second part in a first direction, the first direction being parallel to the first plane;
a third SiC region of the first conductivity type provided in the second SiC region; and
a fourth SiC region of the first conductivity type provided between the first part of the second SiC region and the gate insulating film, the fourth SiC region being adjacent to the second part of the second SiC region in the first direction, the fourth SiC region provided between the first SiC region and the third SiC region in a second direction, the second direction being perpendicular to the first direction and being parallel to the first plane, and first-conductivity-type impurity concentration of the fourth SiC region is lower than first-conductivity-type impurity concentration of the third SiC region.
12. The semiconductor device according to claim 11,
wherein the fourth SiC region and the third SiC region are in contact with each other.
13. The semiconductor device according to claim 11,
wherein width of the fourth SiC region interposed between the second SiC regions is gradually reduced in a direction from the first plane to the second plane.
14. The semiconductor device according to claim 11,
wherein the second SiC region is provided between the fourth SiC region and the third SiC region.
15. The semiconductor device according to claim 11,
wherein, when width of a portion close to the first plane in the fourth SiC region interposed between the second SiC regions is w [μm], the second-conductivity-type impurity concentration of the second SiC region is NA [cm3], the first-conductivity-type impurity concentration of the fourth SiC region is ND [cm−3], Vbi is 3.2 [V], q is 1.602×10−19 [C], ε0 is 8.854×10−14 [F/cm], and ε is 9.7, the following inequality is satisfied:
w ≦ 2 × 10000 × 2 ⁢ ɛ 0 ⁢ ɛ · V bi q ⁢ N A + N D N A ⁢ N D .
16. The semiconductor device according to claim 11,
wherein width of the fourth SiC region in the first direction is equal to or less than 1.6 μm.
17. The semiconductor device according to claim 11,
wherein density of crystal defects in the fourth SiC region is lower than density of crystal defects in the second SiC region.
18. The semiconductor device according to claim 11,
wherein width of the fourth SiC region in the first direction is less than depth of the fourth SiC region.
19. The semiconductor device according to claim 11,
wherein the first-conductivity-type impurity concentration of the fourth SiC region is substantially equal to the first-conductivity-type impurity concentration of the first SiC region.
20. The semiconductor device according to claim 11,
wherein the gate insulating film is a silicon oxide film.
US15/067,438 2015-09-11 2016-03-11 Semiconductor device Active US9786742B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015179328A JP6523887B2 (en) 2015-09-11 2015-09-11 Semiconductor device
JP2015-179328 2015-09-11

Publications (2)

Publication Number Publication Date
US20170077237A1 US20170077237A1 (en) 2017-03-16
US9786742B2 true US9786742B2 (en) 2017-10-10

Family

ID=58257585

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/067,438 Active US9786742B2 (en) 2015-09-11 2016-03-11 Semiconductor device

Country Status (4)

Country Link
US (1) US9786742B2 (en)
JP (1) JP6523887B2 (en)
CN (1) CN106531799B (en)
TW (1) TW201711197A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180025910A1 (en) * 2016-07-22 2018-01-25 Kabushiki Kaisha Toshiba Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator
US20220020853A1 (en) * 2020-07-17 2022-01-20 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6702244B2 (en) 2017-03-21 2020-05-27 日本電気株式会社 Supply control device, supply device, supply control method, program
CN108231898B (en) * 2017-12-14 2021-07-13 东南大学 Silicon carbide power semiconductor device with low on-resistance
EP4310888A1 (en) * 2022-07-22 2024-01-24 Nexperia B.V. A method of manufacturing a vertical oriented semiconductor device as well as a corresponding vertical oriented semiconductor device obtained by such a method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079079A1 (en) * 2006-09-28 2008-04-03 Sanyo Electric Co., Ltd. Insulated-gate semiconductor device
US20090085111A1 (en) * 2007-09-27 2009-04-02 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US20100081243A1 (en) 2008-09-26 2010-04-01 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device
US20110012132A1 (en) * 2008-02-06 2011-01-20 Rohm Co., Ltd. Semiconductor Device
US20110198616A1 (en) * 2008-10-17 2011-08-18 Kenya Yamashita Semiconductor device and method for manufacturing same
JP2013093440A (en) 2011-10-26 2013-05-16 Kansai Electric Power Co Inc:The Manufacturing method of field effect transistor and field effect transistor
US20130234161A1 (en) 2012-03-07 2013-09-12 Nat'I Inst. of Advanced Industrial Sci. and Tech. Sic semiconductor device and manufacturing method thereof
US8835934B2 (en) 2009-09-15 2014-09-16 Kabushiki Kaishia Toshiba Semiconductor device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02192767A (en) * 1989-01-21 1990-07-30 Matsushita Electric Works Ltd Field effect semiconductor device
JP3385938B2 (en) * 1997-03-05 2003-03-10 株式会社デンソー Silicon carbide semiconductor device and method of manufacturing the same
JP3180895B2 (en) * 1997-08-18 2001-06-25 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device
JP4595144B2 (en) * 1999-09-21 2010-12-08 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
US6956238B2 (en) * 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
JP4029595B2 (en) * 2001-10-15 2008-01-09 株式会社デンソー Method for manufacturing SiC semiconductor device
JP3985727B2 (en) * 2003-05-12 2007-10-03 日産自動車株式会社 Semiconductor device and manufacturing method thereof
WO2005083796A1 (en) * 2004-02-27 2005-09-09 Rohm Co., Ltd. Semiconductor device and method for manufacturing same
JP5029042B2 (en) * 2007-02-01 2012-09-19 株式会社デンソー Silicon carbide semiconductor device
CN102194885B (en) * 2011-05-12 2013-06-26 西安电子科技大学 N-type buried-channel silicon carbide metal oxide semiconductor field effect transistor (DEMOSFET) device and preparation method thereof
CN102244099B (en) * 2011-06-23 2013-04-17 西安电子科技大学 SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide -Semiconductor Field Effect Transistor) device with epitaxy channel and manufacturing method of SiC IEMOSFET device
JP5916792B2 (en) * 2014-05-07 2016-05-11 ローム株式会社 Semiconductor device and manufacturing method thereof
CN106663693B (en) * 2014-06-27 2019-11-01 三菱电机株式会社 Manufacturing silicon carbide semiconductor device
CN104538450A (en) * 2014-12-29 2015-04-22 中国科学院半导体研究所 SiC VDMOSFET structure with low specific on-resistance and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080079079A1 (en) * 2006-09-28 2008-04-03 Sanyo Electric Co., Ltd. Insulated-gate semiconductor device
US20090085111A1 (en) * 2007-09-27 2009-04-02 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US20110012132A1 (en) * 2008-02-06 2011-01-20 Rohm Co., Ltd. Semiconductor Device
US20100081243A1 (en) 2008-09-26 2010-04-01 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device
US20110198616A1 (en) * 2008-10-17 2011-08-18 Kenya Yamashita Semiconductor device and method for manufacturing same
US8835934B2 (en) 2009-09-15 2014-09-16 Kabushiki Kaishia Toshiba Semiconductor device
JP2013093440A (en) 2011-10-26 2013-05-16 Kansai Electric Power Co Inc:The Manufacturing method of field effect transistor and field effect transistor
US20130234161A1 (en) 2012-03-07 2013-09-12 Nat'I Inst. of Advanced Industrial Sci. and Tech. Sic semiconductor device and manufacturing method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
J.Y. Chen, "CMOS Devices and Technology for FLSI" (1990).
Taiwanese Office Action dated Oct. 11, 2016 in corresponding Taiwanese Application No. 105102381, along with English translation thereof.

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180025910A1 (en) * 2016-07-22 2018-01-25 Kabushiki Kaisha Toshiba Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator
US9916981B2 (en) * 2016-07-22 2018-03-13 Kabushiki Kaisha Toshiba Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator
US10074539B2 (en) * 2016-07-22 2018-09-11 Kabushiki Kaisha Toshiba Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator
US20220020853A1 (en) * 2020-07-17 2022-01-20 Kabushiki Kaisha Toshiba Semiconductor device
US11749722B2 (en) * 2020-07-17 2023-09-05 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
CN106531799B (en) 2020-07-03
TW201711197A (en) 2017-03-16
JP6523887B2 (en) 2019-06-05
JP2017055027A (en) 2017-03-16
CN106531799A (en) 2017-03-22
US20170077237A1 (en) 2017-03-16

Similar Documents

Publication Publication Date Title
JP7132207B2 (en) SiC semiconductor device with offset below trench
US9812529B2 (en) Semiconductor device and method for manufacturing the same
US9786742B2 (en) Semiconductor device
US8354715B2 (en) Semiconductor device and method of fabricating the same
US9893176B2 (en) Silicon-carbide trench gate MOSFETs
US20170271442A1 (en) Semiconductor device
JP6526591B2 (en) Semiconductor device
US20120193643A1 (en) Semiconductor device
WO2013001677A1 (en) Semiconductor device and method for manufacturing same
US20140209999A1 (en) Semiconductor device
US9443937B2 (en) Semiconductor device
US9748343B2 (en) Semiconductor device
US20200144412A1 (en) Semiconductor device
US8941120B2 (en) Semiconductor device and method for manufacturing the same
US10741686B2 (en) Method for manufacturing semiconductor device and semiconductor device
CN108604600B (en) Silicon carbide semiconductor device and method for manufacturing same
US20170271437A1 (en) Semiconductor device
US20180366549A1 (en) Semiconductor device and method of manufacturing a semiconductor device
TW201711186A (en) Semiconductor device
US9634136B2 (en) Semiconductor device
US10468488B2 (en) Semiconductor device
US20240088258A1 (en) Method of manufacturing semiconductor device and semiconductor device
JP6808766B2 (en) Semiconductor device
US20220085159A1 (en) Semiconductor device and method for manufacturing the same
JP2020127022A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, TAKUMA;KONO, HIROSHI;REEL/FRAME:038335/0345

Effective date: 20160404

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4