JP2020127022A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device where short-circuit resistance is improved.SOLUTION: A MOSFET 100 comprises a silicon carbide layer 10, a source electrode (first electrode) 12, a drain electrode (second electrode) 14, a gate insulation layer 16, a gate electrode 18 and an interlayer insulation layer 20. The silicon carbide layer 10 comprises an ntype drain region 22, an ntype drift region (first silicon carbide region) 24, a p type first body region 26a (second silicon carbide region), a p type second body region 26b (third silicon carbide region), an ntype first source region 28a (fourth silicon carbide region), an ntype second source region 28b (fifth silicon carbide region), a ptype first body contact region 30a, a ptype second body contact region 30b and a first p type region 32a (sixth silicon carbide region).SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to a semiconductor device.

Silicon carbide is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as a band gap three times, a breakdown electric field strength about ten times, and a thermal conductivity about three times that of silicon. By utilizing this characteristic, it is possible to realize a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and the like, which can operate at high temperature with high breakdown voltage and low loss.

For example, when the MOSFET is short-circuited due to a circuit failure or the like, a high voltage is applied between the source and the drain, and a large current flows. Similarly, when the IGBT is short-circuited, a high voltage is applied between the emitter and collector and a large current flows. The time from when the MOSFET or the IGBT is short-circuited until it is destroyed is called the short-circuit withstand capability. In order to prevent the destruction of the MOSFET or the IGBT when a short circuit occurs, it is desired to improve the short circuit withstand capability.

JP, 2005-119157, A

An object of the present invention is to provide a semiconductor device capable of improving the short circuit withstand capability.

The semiconductor device of the embodiment is provided with a first electrode, a second electrode, a gate electrode, at least a part of which is provided between the first electrode and the second electrode, and at least a part of which is A first conductivity type first silicon carbide region provided between a gate electrode and the second electrode, and a second silicon carbide region provided between the first electrode and the first silicon carbide region. A second silicon carbide region of conductivity type is provided between the first electrode and the first silicon carbide region, and the first silicon carbide region is provided between the second silicon carbide region and the second silicon carbide region. It is provided between the third silicon carbide region of the second conductivity type in which the first portion is located, and the first electrode and the second silicon carbide region, and is separated from the first silicon carbide region. A fourth silicon carbide region of the first conductivity type, which is provided between the fourth silicon carbide region of the first conductivity type and the first electrode and the third silicon carbide region and is separated from the first silicon carbide region of the first conductivity type. A silicon carbide region, a gate insulating layer provided between the gate electrode and the second silicon carbide region, and between the gate electrode and the third silicon carbide region; The first portion of the first silicon carbide region is in contact with the silicon carbide region and the third silicon carbide region, is between the gate electrode, and the first portion is in contact with the second electrode. Between the second conductive type sixth silicon carbide region where the second portion of the silicon carbide region is located, the second silicon carbide region and the third silicon carbide region, and the gate electrode. The first portion of the first silicon carbide region is located, the second portion of the first silicon carbide region is located between the second electrode and the sixth electrode, and the second portion of the first silicon carbide region is located between the second electrode and the second electrode. A second conductivity type seventh silicon carbide region in which the first silicon carbide region is located between the first silicon carbide region and the third silicon carbide region, and the first silicon carbide region is sandwiched between the first silicon carbide region and the third silicon carbide region. The first silicon carbide region is interposed between a portion of the sixth silicon carbide region and a portion of the seventh silicon carbide region sandwiched between the first silicon carbide region and the third silicon carbide region. A silicon carbide region is located.

FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic top view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. The schematic cross section of the semiconductor device of 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members and the like will be denoted by the same reference numerals, and the description of the members and the like once described will be appropriately omitted.

Further, in the following description, the notation of n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represents the relative level of the impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ⁻ indicates that the n-type impurity concentration is relatively lower than n. Further, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ⁻ indicates that the p-type impurity concentration is relatively lower than p. In some cases, n ⁺ type and n ⁻ type are simply referred to as n type, and p ⁺ type and p ⁻ type are simply referred to as p type.

The impurity concentration can be measured by SIMS (Secondary Ion Mass Spectrometry), for example. Further, the relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by SCM (Scanning Capacitance Microscopy), for example. The distance such as the depth and thickness of the impurity region can be obtained by SIMS, for example. Also. The depths, thicknesses, widths, distances, and the like of the impurity regions can be obtained from, for example, a composite image of an SCM image and an AFM (Atomic Force Microscope) image.

(First embodiment)
The semiconductor device of this embodiment has a first electrode, a second electrode, a gate electrode, at least a portion of which is provided between the first electrode and the second electrode, and at least a portion of which is the gate electrode. A first conductivity type first silicon carbide region provided between the first electrode and the second electrode, and a second conductivity type second silicon carbide region provided between the first electrode and the first silicon carbide region. Second silicon carbide region, the first electrode and the first silicon carbide region are provided between the first silicon carbide region and the second silicon carbide region, and the first portion of the first silicon carbide region is located between the second silicon carbide region and the second silicon carbide region. A third silicon carbide region of conductivity type and a fourth silicon carbide region of first conductivity type provided between the first electrode and the second silicon carbide region and separated from the first silicon carbide region. A fifth silicon carbide region of the first conductivity type provided between the first electrode and the third silicon carbide region and separated from the first silicon carbide region, and a gate electrode and a second silicon carbide region. And a gate insulating layer provided between the gate electrode and the third silicon carbide region, and in contact with the second silicon carbide region and the third silicon carbide region, and between the gate electrode and the gate electrode. A first conductive portion of the first silicon carbide region, and a second conductive type sixth silicon carbide region in which the second portion of the first silicon carbide region is positioned between the first electrode and the second electrode. Prepare

FIG. 1 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 2 is a schematic top view of the semiconductor device of this embodiment. FIG. 2 is a diagram showing patterns of the surface of the silicon carbide layer and the impurity regions inside. 3, 4, and 5 are schematic cross-sectional views of the semiconductor device of this embodiment. FIG. 1 is a sectional view taken along line AA′ of FIG. FIG. 3 is a sectional view taken along line BB′ of FIG. FIG. 4 is a sectional view taken along the line CC′ of FIG. FIG. 5 is a sectional view taken along line DD′ of FIG.

The semiconductor device of this embodiment is a planar gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the present embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation.

Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

MOSFET 100 includes silicon carbide layer 10, source electrode (first electrode) 12, drain electrode (second electrode) 14, gate insulating layer 16, gate electrode 18, and interlayer insulating layer 20.

In the silicon carbide layer 10, an n ⁺ -type drain region 22, an n ⁻ -type drift region (first silicon carbide region) 24, a p-type first body region 26a (second silicon carbide region), p-type second body region 26b (third silicon carbide region), n ⁺ -type first source region 28a (fourth silicon carbide region), n ⁺ -type second source region 28b (fifth) Silicon carbide region), the p ⁺ -type first body contact region 30a, the p ⁺ -type second body contact region 30b, the first p-type region 32a (sixth silicon carbide region), and the second p-type region. The mold region 32b (seventh silicon carbide region) and the third p-type region 32c are provided.

At least a part of silicon carbide layer 10 is provided between source electrode 12 and drain electrode 14. At least a part of silicon carbide layer 10 is provided between gate electrode 18 and drain electrode 14. Silicon carbide layer 10 is single crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC.

Silicon carbide layer 10 has a first surface (“P1” in FIG. 1) and a second surface (“P2” in FIG. 1). Hereinafter, the first surface is also referred to as the front surface and the second surface is also referred to as the back surface. Note that, hereinafter, the “depth” means the depth based on the first surface.

The first surface is, for example, a surface inclined from 0 degree to 8 degrees with respect to the (0001) plane. Further, the second surface is, for example, a surface inclined from 0 degree to 8 degrees with respect to the (000-1) plane. The (0001) plane is called a silicon plane. The (000-1) plane is called a carbon plane.

N ⁺ type drain region 22 is provided on the back surface side of silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurity in the drain region 22 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

The n ⁻ type drift region 24 is provided on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurities in the drift region 24 is lower than the impurity concentration of the n-type impurities in the drain region 22. The impurity concentration of the n-type impurity in the drift region 24 is, for example, 4×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less. The thickness of the drift region 24 is, for example, 5 μm or more and 150 μm or less.

The drift region 24 includes a first portion 24a located between the gate electrode 18 and the first p-type region 32a and a second portion 24b located between the first p-type region 32a and the drain electrode 14. Equipped with. The drift region 24 includes a third portion 24c located between the gate electrode 18 and the drain electrode 14.

The first portion 24a and the third portion 24c are located between the first body region 26a and the second body region 26b. The first portion 24a is sandwiched by the third portion 24c. The third portion 24c is located between the gate electrode 18 and the second portion 24b.

The impurity concentration of the n-type impurity in the first portion 24a and the third portion 24c is higher than the impurity concentration of the n-type impurity in the second portion 24b, for example. The impurity concentration of the n-type impurities in the first portion 24a and the third portion 24c is, for example, higher than that of the n-type impurity in the second portion 24b by one digit or more. The impurity concentration of the n-type impurities in the first portion 24a and the third portion 24c is, for example, 1×10 ¹⁶ cm ⁻³ or more.

Depletion extending from the first body region 26a, the second body region 26b, and the first p-type region 32a by increasing the impurity concentration of the n-type impurity in the first portion 24a and the third portion 24c. It is possible to suppress the width of the layer and reduce the on-resistance of the MOSFET 100.

Further, for example, the impurity concentration of the n-type impurities in the first portion 24a is higher than the impurity concentration of the n-type impurities in the third portion 24c. By increasing the impurity concentration of the n-type impurity in the first portion 24a, it is possible to particularly suppress the width of the depletion layer extending upward from the first p-type region 32a and further reduce the on-resistance of the MOSFET 100. Is.

The first body region 26a and the second body region 26b are provided between the source electrode 12 and the second portion 24b of the drift region 24. The surfaces of the first body region 26a and the second body region 26b in contact with the gate insulating layer 16 function as the channel region of the MOSFET 100.

The first body region 26a and the second body region 26b include, for example, aluminum (Al) as a p-type impurity. The peak value of the impurity concentration of the p-type impurity in the first body region 26a and the second body region 26b is, for example, 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less.

The depth of the first body region 26a and the second body region 26b is, for example, 0.3 μm or more and 0.8 μm or less.

The first source region 28a is provided between the source electrode 12 and the first body region 26a. The first source region 28a is separated from the drift region 24.

The second source region 28b is provided between the source electrode 12 and the second body region 26b. The second source region 28b is separated from the drift region 24.

The first source region 28a and the second source region 28b include, for example, phosphorus (P) as an n-type impurity. The impurity concentration of the n-type impurity in the first source region 28a and the second source region 28b is higher than the impurity concentration of the n-type impurity in the drift region 24.

The impurity concentration of the n-type impurity in the first source region 28a and the second source region 28b is, for example, 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The depths of the first source region 28a and the second source region 28b are shallower than the depths of the first body region 26a and the second body region 26b, for example, 0.1 μm or more and 0.3 μm or less. Is.

The first source region 28a and the second source region 28b are fixed to the potential of the source electrode 12.

The p ⁺ -type first body contact region 30a is provided between the source electrode 12 and the first body region 26a. The impurity concentration of the p-type impurity in the first body contact region 30a is higher than the impurity concentration of the p-type impurity in the first body region 26a.

The p ⁺ -type second body contact region 30b is provided between the source electrode 12 and the second body region 26b. The impurity concentration of the p-type impurity in the second body contact region 30b is higher than the impurity concentration of the p-type impurity in the second body region 26b.

The first body contact region 30a and the second body contact region 30b include, for example, aluminum (Al) as a p-type impurity. The impurity concentration of the p-type impurity in the first body contact region 30a and the second body contact region 30b is, for example, 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

The depth of the first body contact region 30a and the second body contact region 30b is, for example, 0.3 μm or more and 0.6 μm or less.

The first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are in contact with the first body region 26a and the second body region 26b. Since the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are in contact with the first body region 26a and the second body region 26b, The p-type region 32a, the second p-type region 32b, and the third p-type region 32c are fixed to the same potential as the first body region 26a and the second body region 26b. For example, the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are fixed to the potential of the source electrode 12.

The first portion 24a of the drift region 24 is located between the gate electrode 18 and the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c. The second portion 24b of the drift region 24 is located between the drain electrode 14 and the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c.

The first p-type region 32a, the second p-type region 32b, and the third p-type region 32c include, for example, aluminum (Al) as a p-type impurity. The impurity concentrations of the p-type impurities in the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are, for example, 1×10 ¹⁷ cm ⁻³ or more and 1×10 ¹⁹ cm ^−. It is ³ or less.

The depths of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are, for example, 0.3 μm or more and 1.2 μm or less. The thickness (t in FIG. 4) of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is, for example, 0.2 μm or more and 0.5 μm or less.

The depths of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are, for example, smaller than the depths of the first body region 26a and the second body region 26b. Too deep. In other words, the distance (d1 in FIG. 5) between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c and the drain electrode 14 is equal to the first body region 26a. , And the distance between the second body region 26b and the drain electrode 14 (d2 in FIG. 5).

The width (w in FIG. 4) of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is, for example, 1.0 μm or more and 3.0 μm or less. The interval (s in FIG. 4) between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is, for example, 2.0 μm or more and 6.0 μm or less.

The intervals between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are, for example, the first p-type region 32a, the second p-type region 32b, and the 3 is larger than the width of the p-type region 32c. The intervals between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are, for example, the first p-type region 32a, the second p-type region 32b, and the The width is at least twice the width of the p-type region 32c.

The first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are formed by, for example, selectively implanting p-type impurities from the surface side of the silicon carbide layer 10. It is possible to form.

The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

The gate insulating layer 16 is provided between the gate electrode 18 and the first body region 26a. The gate insulating layer 16 is provided between the gate electrode 18 and the second body region 26b. The gate insulating layer 16 is provided between the gate electrode 18 and the first portion 24 a of the drift region 24.

The gate insulating layer 16 is, for example, silicon oxide. For the gate insulating layer 16, for example, a High-k insulating material (high dielectric constant insulating material) can be applied.

The interlayer insulating layer 20 is provided on the gate electrode 18. The interlayer insulating layer 20 is, for example, silicon oxide.

The source electrode 12 is in contact with the first source region 28a and the second source region 28b. The source electrode 12 contacts the first body contact region 30a and the second body contact region 30b.

The source electrode 12 contains a metal. The metal forming the source electrode 12 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The region of the source electrode 12 in contact with the silicon carbide layer 10 is, for example, metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

Drain electrode 14 is provided on the back surface of silicon carbide layer 10. The drain electrode 14 contacts the drain region 22.

The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 includes, for example, a material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

Next, the operation and effect of MOSFET 100 of the present embodiment will be described.

For example, when the MOSFET is short-circuited due to a circuit failure or the like, a high voltage is applied between the source and the drain, and a large current flows. If a large current continues to flow in the MOSFET for a long time, the MOSFET will be destroyed.

It is required that the MOSFET is not destroyed after the MOSFET is short-circuited and before the flowing current is cut off from the outside. It takes a predetermined time to shut off the flowing current from the outside. Therefore, it is desirable to improve the time from the short-circuited state of the MOSFET until the destruction, that is, the short-circuit withstand capability.

FIG. 6 is an explanatory diagram of the operation and effect of the semiconductor device of this embodiment. FIG. 6A is an explanatory diagram of a normal ON state of the MOSFET. FIG. 6B is an explanatory diagram when a short circuit occurs in the MOSFET. 6A and 6B are sectional views corresponding to FIG. 4.

In the normal ON state of the MOSFET shown in FIG. 6A, the voltage applied between the source electrode 12 and the drain electrode 14 is small. Therefore, the voltage applied between the drift region 24 and the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is also small.

Therefore, the depletion layer DL extending from the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c to the drift region 24 has a small extension. Therefore, the depletion layer DL has little influence on the current flowing in the drift region 24.

On the other hand, when a short circuit occurs in the MOSFET, a large voltage is applied between the source electrode 12 and the drain electrode 14. Therefore, the voltage applied between the drift region 24 and the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c also increases.

Therefore, the extension of the depletion layer DL extending from the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c to the drift region 24 is significantly larger than that in the normal ON state. Grows to. No current flows in the depletion layer DL portion. The depletion layer DL that greatly extends in the drift region 24 limits the path of the current flowing in the drift region 24.

Therefore, the on-resistance increases when the MOSFET is short-circuited. In other words, the current flowing between the source electrode 12 and the drain electrode 14 at the time of short circuit becomes small. As a result, it becomes possible to improve the time from the short-circuited state of the MOSFET until the destruction, that is, the short-circuit withstand capability.

The distance (s in FIG. 4) between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is equal to the first p-type region 32a and the second p-type region. It is desirable that the width is larger than the widths of 32b and the third p-type region 32c (w in FIG. 4). When the distance between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is relatively narrow, the current path in the normal ON state of the MOSFET is narrowed, and the ON resistance is reduced. May increase.

The width (w in FIG. 4) of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is preferably 1.0 μm or more and 3.0 μm or less. If it is less than the above range, there is a possibility that a sufficient short circuit withstand capability cannot be realized. If it exceeds the above range, the on-resistance of the MOSFET in the normal on-state may increase.

The distance (s in FIG. 4) between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is preferably 2.0 μm or more and 6.0 μm or less. Below the above range, the on-resistance of the MOSFET in the normal on-state may increase. If it exceeds the above range, it may not be possible to sufficiently improve the short-circuit withstand capability.

The thickness (t in FIG. 4) of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c is preferably 0.2 μm or more and 0.5 μm or less. .. If it is less than the above range, the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c may be completely depleted at the time of a short circuit, and the extension of the depletion layer DL may be reduced. If it exceeds the above range, the distribution of p-type impurities introduced by ion implantation into the silicon carbide layer 10 at the time of forming the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c. There is a possibility that the control of the threshold voltage of the MOSFET may become difficult due to the influence of the bottom of the.

The depths of the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c are deeper than the depths of the first body region 26a and the second body region 26b. Is desirable. In other words, the distance (d1 in FIG. 5) between the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c and the drain electrode 14 is equal to the first body region 26a. , And shorter than the distance between the second body region 26b and the drain electrode 14 (d2 in FIG. 5). Due to the influence of the bottom of the distribution of p-type impurities introduced into the silicon carbide layer 10 by ion implantation when forming the first p-type region 32a, the second p-type region 32b, and the third p-type region 32c, It is possible to avoid difficulty in controlling the threshold voltage of the MOSFET.

As described above, according to the present embodiment, the MOSFET 100 capable of improving the short circuit withstand capability is realized.

(Second embodiment)
The semiconductor device of this embodiment is different from that of the first embodiment in that it is an IGBT. The description of the same contents as those in the first embodiment will be omitted.

FIG. 7 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 7 is a diagram corresponding to FIG. 1 of the semiconductor device of the first embodiment.

The semiconductor device of this embodiment is a planar gate type vertical IGBT 200 using silicon carbide.

Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

IGBT 200 includes silicon carbide layer 10, emitter electrode (first electrode) 112, collector electrode (second electrode) 114, gate insulating layer 16, gate electrode 18, and interlayer insulating layer 20.

In the silicon carbide layer 10, ap ⁺ type collector region 122, an n ⁻ type drift region (first silicon carbide region) 24, a p type first body region 26a (second silicon carbide region), P-type second body region 26b (third silicon carbide region), n ⁺ -type first emitter region 128a (fourth silicon carbide region), n ⁺ -type second emitter region 128b (fifth) Silicon carbide region), the p ⁺ -type first body contact region 30a, the p ⁺ -type second body contact region 30b, the first p-type region 32a (sixth silicon carbide region), and the second p-type region. The mold region 32b (seventh silicon carbide region) and the third p-type region 32c are provided.

The only structural difference between the IGBT 200 and the MOSFET 100 of the first embodiment shown in FIG. 1 is that the n ⁺ type drain region 22 of the MOSFET 100 is replaced with a p ⁺ type collector region 122.

According to the present embodiment, the IGBT 200 capable of improving the short circuit withstand capability is realized by the same operation as that of the first embodiment.

In the first and second embodiments, the case where 4H-SiC is used as the crystal structure of SiC has been described as an example, but the present invention is applicable to devices using SiC having other crystal structures such as 6H-SiC and 3C-SiC. It is also possible to apply. It is also possible to apply a surface other than the (0001) surface to the surface of silicon carbide layer 10.

In the first and second embodiments, the case where the first conductivity type is n type and the second conductivity type is p type has been described as an example, but the first conductivity type is p type and the second conductivity type is n type. It is also possible to do so.

Although aluminum (Al) is illustrated as the p-type impurity in the first and second embodiments, boron (B) can also be used. Further, although nitrogen (N) and phosphorus (P) have been illustrated as the n-type impurities, arsenic (As), antimony (Sb) and the like can be applied.

While some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. For example, the components of one embodiment may be replaced or changed with the components of other embodiments. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

12 Source electrode (first electrode)
14 Drain electrode (second electrode)
16 gate insulating layer 18 gate electrode 24 drift region (first silicon carbide region)
24a 1st part 24b 2nd part 26a 1st body region (2nd silicon carbide region)
26b Second body region (third silicon carbide region)
28a First source region (fourth silicon carbide region)
28b Second source region (fifth silicon carbide region)
32a First p-type region (sixth silicon carbide region)
32b Second p-type region (seventh silicon carbide region)
100 MOSFET (semiconductor device)
112 Emitter electrode (first electrode)
114 collector electrode (second electrode)
128a First emitter region (fourth silicon carbide region)
128b Second emitter region (fifth silicon carbide region)
200 IGBT (semiconductor device)

Claims (5)

A first electrode,
A second electrode,
A gate electrode,
At least a part is provided between the first electrode and the second electrode, and at least a part is provided between the gate electrode and the second electrode. A silicon carbide region,
A second silicon carbide region of a second conductivity type provided between the first electrode and the first silicon carbide region;
A second conductivity type that is provided between the first electrode and the first silicon carbide region, and the first portion of the first silicon carbide region is located between the first silicon carbide region and the second silicon carbide region. A third silicon carbide region of
A fourth silicon carbide region of a first conductivity type provided between the first electrode and the second silicon carbide region and separated from the first silicon carbide region;
A fifth silicon carbide region of a first conductivity type which is provided between the first electrode and the third silicon carbide region and is separated from the first silicon carbide region;
A gate insulating layer provided between the gate electrode and the second silicon carbide region, and between the gate electrode and the third silicon carbide region;
Is in contact with the second silicon carbide region and the third silicon carbide region, the first portion of the first silicon carbide region is located between the gate electrode and the second silicon carbide region, and between the second electrode and the second electrode. A second conductivity type sixth silicon carbide region in which the second portion of the first silicon carbide region is located,
Is in contact with the second silicon carbide region and the third silicon carbide region, the first portion of the first silicon carbide region is located between the gate electrode and the second silicon carbide region, and between the second electrode and the second electrode. A second conductive type seventh silicon carbide region in which the second portion of the first silicon carbide region is located in, and the first silicon carbide region is located between the second portion and the sixth silicon carbide region. ,
Equipped with
A portion of the sixth silicon carbide region sandwiched between the first silicon carbide region and the third silicon carbide region, and between the first silicon carbide region and the third silicon carbide region. A semiconductor device in which the first silicon carbide region is located between a part of the seventh silicon carbide region that is sandwiched. The semiconductor according to claim 1, wherein a distance between the sixth silicon carbide region and the seventh silicon carbide region is larger than a width of the sixth silicon carbide region and a width of the seventh silicon carbide region. apparatus. The semiconductor device according to claim 1, wherein the thickness of the sixth silicon carbide region is 0.2 μm or more. 4. The semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type impurity in the first portion is higher than the impurity concentration of the first conductivity type impurity in the second portion. The first portion between the sixth silicon carbide region and the gate electrode and the first portion between the seventh silicon carbide region and the gate electrode are provided with the first portion. The third portion of the silicon carbide region is located, and the impurity concentration of the first conductivity type impurity in the first portion is higher than the impurity concentration of the first conductivity type impurity in the third portion. The semiconductor device according to claim 4.

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