JP6808766B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6808766B2
JP6808766B2 JP2019003427A JP2019003427A JP6808766B2 JP 6808766 B2 JP6808766 B2 JP 6808766B2 JP 2019003427 A JP2019003427 A JP 2019003427A JP 2019003427 A JP2019003427 A JP 2019003427A JP 6808766 B2 JP6808766 B2 JP 6808766B2
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trench
semiconductor device
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輝之 大橋
輝之 大橋
良介 飯島
良介 飯島
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Toshiba Corp
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Description

本発明の実施形態は、半導体装置に関する。 Embodiments of the present invention relate to semiconductor devices.

次世代の半導体デバイス用の材料としてＳｉＣ（炭化珪素）が期待されている。ＳｉＣはＳｉ（シリコン）と比較して、バンドギャップが３倍、破壊電界強度が約１０倍、熱伝導率が約３倍と優れた物性を有する。この特性を活用すれば低損失かつ高温動作可能な半導体デバイスを実現することができる。 SiC (silicon carbide) is expected as a material for next-generation semiconductor devices. Compared with Si (silicon), SiC has excellent physical properties such as a band gap of 3 times, a breaking electric field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing this characteristic, a semiconductor device capable of low loss and high temperature operation can be realized.

しかし、例えば、ＳｉＣを用いてＭＩＳ（Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）構造を形成する場合、ＳｉＣの耐圧が高いため、Ｓｉ（シリコン）を用いたＭＩＳ構造と比較して、ゲート絶縁膜の耐圧が、半導体の耐圧に比べて低くなる恐れがある。特に、素子の集積度をあげるため、トレンチ内にＭＩＳ構造を形成する場合、トレンチ底部での電界集中により、ゲート絶縁膜の耐圧が低くなるという問題がある。 However, for example, when a MIS (Metal Insulator Semiconductor) structure is formed using SiC, the breakdown voltage of the gate insulating film is higher than that of the MIS structure using Si (silicon) because the breakdown voltage of SiC is high. It may be lower than the withstand voltage. In particular, when a MIS structure is formed in a trench in order to increase the degree of integration of elements, there is a problem that the withstand voltage of the gate insulating film is lowered due to the concentration of the electric field at the bottom of the trench.

特開２０１３−２１４６５８号公報Japanese Unexamined Patent Publication No. 2013-214658

本発明が解決しようとする課題は、ゲート絶縁膜の耐圧が高い半導体装置を提供することにある。 An object to be solved by the present invention is to provide a semiconductor device having a high withstand voltage of a gate insulating film.

実施形態の半導体装置は、ＳｉＣ基板と、前記ＳｉＣ基板の上に設けられ、側面と底面とを有する第１のトレンチを表面の側に有するＳｉＣ層と、前記ＳｉＣ層内に設けられた第１導電型の第１のＳｉＣ領域と、前記ＳｉＣ層内に前記第１のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第２導電型の第２のＳｉＣ領域と、前記ＳｉＣ層内に前記第２のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第１導電型の第３のＳｉＣ領域と、前記第１のトレンチの前記側面の上及び前記底面の上に設けられたゲート絶縁膜と、前記第１のＳｉＣ領域、前記第２のＳｉＣ領域、及び、前記第３のＳｉＣ領域との間に前記ゲート絶縁膜が設けられたゲート電極と、を備え、前記第２のＳｉＣ領域と前記第３のＳｉＣ領域との境界は、前記第１のトレンチの前記側面の側方に在り、前記境界は、第１の領域を備え、前記第１の領域は前記ＳｉＣ層の前記表面からの距離が前記第１のトレンチから離れるにしたがって大きくなり、前記第１のトレンチの前記側面から前記第１の領域の前記第１のトレンチの側の端部までの距離が０μｍ以上０．３μｍ以下であり、前記境界が、前記表面に略垂直な第４の領域を備え、前記第４の領域と前記第１のトレンチとの間に前記第１の領域が設けられ、前記ゲート電極の前記底面の側の端部を含み前記表面に平行な仮想平面と、前記第２のＳｉＣ領域との間の前記側面に沿った第１の距離は、前記第３のＳｉＣ領域と前記第１のＳｉＣ領域との間の前記側面に沿った第２の距離の２分の１よりも大きい。 The semiconductor device of the embodiment includes a SiC substrate, a SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on the surface side, and a first provided in the SiC layer. A conductive type first SiC region, a second conductive type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer, and the above in the SiC layer. A first conductive type third SiC region provided between the second SiC region and the SiC substrate, and a gate insulating film provided on the side surface and the bottom surface of the first trench. A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region, and the second SiC region The boundary with the third SiC region is on the side of the side surface of the first trench, the boundary comprises a first region, and the first region is from the surface of the SiC layer. The distance increases as the distance from the first trench increases, and the distance from the side surface of the first trench to the end of the first region on the side of the first trench is 0 μm or more and 0.3 μm or less. The boundary comprises a fourth region substantially perpendicular to the surface, the first region is provided between the fourth region and the first trench, and the bottom surface of the gate electrode is provided. The first distance along the side surface between the virtual plane including the side end and parallel to the surface and the second SiC region is the third SiC region and the first SiC region. Greater than half of the second distance along the side surface between .

第１の実施形態の半導体装置の一例を示す模式断面図。The schematic cross-sectional view which shows an example of the semiconductor device of 1st Embodiment. 第１の実施形態の半導体装置の別の一例を示す模式断面図。FIG. 6 is a schematic cross-sectional view showing another example of the semiconductor device of the first embodiment. 第１の実施形態の半導体装置の製造方法において、製造途中の半導体装置を示す模式断面図。FIG. 3 is a schematic cross-sectional view showing a semiconductor device in the process of being manufactured in the method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態の半導体装置の製造方法において、製造途中の半導体装置を示す模式断面図。FIG. 3 is a schematic cross-sectional view showing a semiconductor device in the process of being manufactured in the method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態の半導体装置の製造方法において、製造途中の半導体装置を示す模式断面図。FIG. 3 is a schematic cross-sectional view showing a semiconductor device in the process of being manufactured in the method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態の半導体装置の製造方法において、製造途中の半導体装置を示す模式断面図。FIG. 3 is a schematic cross-sectional view showing a semiconductor device in the process of being manufactured in the method for manufacturing a semiconductor device according to the first embodiment. 第１の実施形態の半導体装置の製造方法において、製造途中の半導体装置を示す模式断面図。FIG. 3 is a schematic cross-sectional view showing a semiconductor device in the process of being manufactured in the method for manufacturing a semiconductor device according to the first embodiment. 比較形態の半導体装置の一例を示す模式断面図。The schematic cross-sectional view which shows an example of the semiconductor device of the comparative form. 第１の実施形態の半導体装置の別の一例を示す模式断面図。FIG. 6 is a schematic cross-sectional view showing another example of the semiconductor device of the first embodiment. 第１の実施形態の半導体装置の作用・効果の説明図。The explanatory view of the operation and effect of the semiconductor device of 1st Embodiment. 第１の実施形態の半導体装置の作用・効果の説明図。The explanatory view of the operation and effect of the semiconductor device of 1st Embodiment. 第１の実施形態の半導体装置の作用・効果の説明図。The explanatory view of the operation and effect of the semiconductor device of 1st Embodiment. 第２の実施形態の半導体装置を示す模式断面図。The schematic cross-sectional view which shows the semiconductor device of 2nd Embodiment. 比較形態の半導体装置を示す模式断面図。Schematic cross-sectional view showing a semiconductor device of a comparative form. 第２の実施形態の半導体装置の作用・効果の説明図。The explanatory view of the operation and effect of the semiconductor device of the 2nd Embodiment. 第３の実施形態の半導体装置を示す模式断面図。FIG. 6 is a schematic cross-sectional view showing the semiconductor device of the third embodiment. 第４の実施形態の半導体装置を示す模式断面図。FIG. 6 is a schematic cross-sectional view showing the semiconductor device of the fourth embodiment. 第５の実施形態の半導体装置を示す模式断面図。The schematic cross-sectional view which shows the semiconductor device of 5th Embodiment.

以下、図面を参照しつつ本発明の実施形態を説明する。なお、以下の説明では、同一又は類似の部材等には同一の符号を付し、一度説明した部材等については適宜その説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members and the like are designated by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

また、以下の説明において、ｎ＋、ｎ、ｎ−及び、ｐ＋、ｐ、ｐ−の表記は、各導電型における不純物濃度の相対的な高低を表す。すなわちｎ＋はｎよりもｎ型の不純物濃度が相対的に高く、ｎ−はｎよりもｎ型の不純物濃度が相対的に低いことを示す。また、ｐ＋はｐよりもｐ型の不純物濃度が相対的に高く、ｐ−はｐよりもｐ型の不純物濃度が相対的に低いことを示す。なお、ｎ＋型、ｎ−型を単にｎ型、ｐ＋型、ｐ−型を単にｐ型と記載する場合もある。 Further, in the following description, the notations of n + , n, n − and p + , p, p − represent the relative high and low of the impurity concentration in each conductive type. That is, n + indicates that the concentration of n-type impurities is relatively higher than n, and n − indicates that the concentration of n-type impurities is relatively lower than that of n. Further, p + indicates that the concentration of p-type impurities is relatively higher than that of p, and p − indicates that the concentration of p-type impurities is relatively lower than that of p. In addition, n + type and n − type may be simply described as n type, p + type, and p − type may be simply described as p type.

（第１の実施形態）
本実施形態の半導体装置は、ＳｉＣ基板と、ＳｉＣ基板上に設けられ、表面からＳｉＣ基板に向かって伸長し、側面と底面とを有するトレンチを有するＳｉＣ層と、ＳｉＣ層内に設けられた第１導電型の第１のＳｉＣ領域と、ＳｉＣ層内に第１のＳｉＣ領域とＳｉＣ基板との間に設けられた第２導電型の第２のＳｉＣ領域と、ＳｉＣ層内に第２のＳｉＣ領域とＳｉＣ基板との間に設けられた第１導電型の第３のＳｉＣ領域と、トレンチの側面上及び底面上に設けられ、第１のＳｉＣ領域、第２のＳｉＣ領域、及び、第３のＳｉＣ領域に接するゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極と、を備える。そして、第２のＳｉＣ領域と第３のＳｉＣ領域との境界がトレンチの側面に接し、境界がＳｉＣ層の表面からの距離がトレンチから離れるにしたがって大きくなり表面に対して第１の傾斜角を有し、トレンチの側面からの距離が０μｍ以上０．３μｍ以下の第１の領域を備える。 (First Embodiment)
The semiconductor device of the present embodiment has a SiC substrate, a SiC layer provided on the SiC substrate, extending from the surface toward the SiC substrate, and having a trench having a side surface and a bottom surface, and a first provided in the SiC layer. 1 Conductive type 1st SiC region, 2nd conductive type 2nd SiC region provided between the 1st SiC region and the SiC substrate in the SiC layer, and 2nd SiC in the SiC layer A first conductive type third SiC region provided between the region and the SiC substrate, and a first SiC region, a second SiC region, and a third SiC region provided on the side surface and the bottom surface of the trench. It is provided with a gate insulating film in contact with the SiC region of the above, and a gate electrode provided on the gate insulating film. Then, the boundary between the second SiC region and the third SiC region touches the side surface of the trench, and the boundary becomes larger as the distance from the surface of the SiC layer increases from the trench, and the first inclination angle with respect to the surface is increased. It has a first region having a distance from the side surface of the trench of 0 μm or more and 0.3 μm or less.

図１は、本実施形態の半導体装置であるＭＩＳＦＥＴの構成の一例を示す模式断面図である。 FIG. 1 is a schematic cross-sectional view showing an example of the configuration of the MISFET which is the semiconductor device of the present embodiment.

ＭＩＳＦＥＴ１００は、電子をキャリアとするｎ型のＭＩＳＦＥＴである。ＭＩＳＦＥＴ１００は、縦型のデバイスである。ＭＩＳＦＥＴ１００は、ゲート絶縁膜及びゲート電極がトレンチ内に設けられたトレンチゲート型のＭＩＳＦＥＴである。 The MISFET 100 is an n-type MISFET whose carrier is an electron. The MISFET 100 is a vertical device. The MISFET 100 is a trench gate type MISFET in which a gate insulating film and a gate electrode are provided in a trench.

ＭＩＳＦＥＴ１００は、ＳｉＣ基板１０、ＳｉＣ層１２、ドリフト領域（第３のＳｉＣ領域）１４、界面１５、第１の領域１５ａ、第２の領域１５ｂ、第３の領域１５ｃ、第４の領域１５ｄ、ｐウェル領域（第２のＳｉＣ領域）１６、ソース領域（第１のＳｉＣ領域）１８、ｐウェルコンタクト領域（第４のＳｉＣ領域）２０、ゲート絶縁膜（絶縁膜）２８、ゲート電極３０、層間絶縁膜３２、ソース電極（電極）３４、ドレイン電極３６、トレンチ５０を備える。 The MISFET 100 includes a SiC substrate 10, a SiC layer 12, a drift region (third SiC region) 14, an interface 15, a first region 15a, a second region 15b, a third region 15c, a fourth region 15d, p. Well region (second SiC region) 16, source region (first SiC region) 18, p-well contact region (fourth SiC region) 20, gate insulating film (insulating film) 28, gate electrode 30, interlayer insulation A film 32, a source electrode (electrode) 34, a drain electrode 36, and a trench 50 are provided.

本明細書ではＳｉＣ基板１０等の面に対し、図１における上側の面を表面、下側の面を裏面と称する。 In the present specification, the upper surface in FIG. 1 is referred to as a front surface and the lower surface is referred to as a back surface with respect to the surface of the SiC substrate 10 or the like.

ＭＩＳＦＥＴ１００は、ｎ＋型のＳｉＣ基板１０を備える。ＳｉＣ基板１０は、例えばＮ（窒素）をｎ型不純物として含む４Ｈ−ＳｉＣのＳｉＣ基板である。ｎ型不純物の不純物濃度は、例えば、１×１０１８ｃｍ−３以上１×１０２０ｃｍ−３以下である。ＳｉＣ基板１０は、ＭＩＳＦＥＴ１００のドレイン領域として機能する。 The MISFET 100 includes an n + type SiC substrate 10. The SiC substrate 10 is, for example, a 4H-SiC SiC substrate containing N (nitrogen) as an n-type impurity. The impurity concentration of the n-type impurity is, for example, 1 × 10 18 cm -3 or more and 1 × 10 20 cm -3 or less. The SiC substrate 10 functions as a drain region of the MISFET 100.

ＳｉＣ基板１０の表面は、例えば、（０００１）面（シリコン面）に対し０度以上１０度以下傾斜した面である。ＳｉＣ基板１０の裏面は、例えば、（０００−１）面（カーボン面）に対し０度以上１０度以下傾斜した面である。 The surface of the SiC substrate 10 is, for example, a surface inclined from 0 degrees or more and 10 degrees or less with respect to the (0001) surface (silicon surface). The back surface of the SiC substrate 10 is, for example, a surface inclined from 0 degrees or more and 10 degrees or less with respect to the (000-1) surface (carbon surface).

ＳｉＣ層１２は、ＳｉＣ基板１０上に設けられる。ＳｉＣ層１２は、例えば、Ｎ（窒素）をｎ型不純物として含む。ＳｉＣ層１２のｎ型不純物の濃度は、例えば、１×１０１４ｃｍ−３以上１×１０１７ｃｍ−３以下である。ＳｉＣ層１２は、例えば、ＳｉＣ基板１０上にエピタキシャル成長により形成されたＳｉＣのエピタキシャル成長層である。 The SiC layer 12 is provided on the SiC substrate 10. The SiC layer 12 contains, for example, N (nitrogen) as an n-type impurity. The concentration of n-type impurities in the SiC layer 12 is, for example, 1 × 10 14 cm -3 or more and 1 × 10 17 cm -3 or less. The SiC layer 12 is, for example, an epitaxial growth layer of SiC formed on the SiC substrate 10 by epitaxial growth.

ＳｉＣ層１２の表面も、シリコン面に対し０度以上１０度以下傾斜した面である。ＳｉＣ層１２の膜厚は、例えば、５μｍ以上１５０μｍ以下である。 The surface of the SiC layer 12 is also a surface inclined at 0 degrees or more and 10 degrees or less with respect to the silicon surface. The film thickness of the SiC layer 12 is, for example, 5 μm or more and 150 μm or less.

ＳｉＣ層１２は、ＳｉＣ層１２の表面からＳｉＣ基板１０に向かって伸長し、側面と底面とを有するトレンチ５０を有する。 The SiC layer 12 has a trench 50 extending from the surface of the SiC layer 12 toward the SiC substrate 10 and having a side surface and a bottom surface.

ドリフト領域（第３のＳｉＣ領域）１４、ｐウェル領域（第２のＳｉＣ領域）１６、ソース領域（第１のＳｉＣ領域）１８、ｐウェルコンタクト領域（第４のＳｉＣ領域）２０は、ＳｉＣ層１２内に設けられる。 The drift region (third SiC region) 14, the p-well region (second SiC region) 16, the source region (first SiC region) 18, and the p-well contact region (fourth SiC region) 20 are SiC layers. It is provided in 12.

ｎ−型のドリフト領域１４は、ｐウェル領域１６とＳｉＣ基板１０との間に設けられる。ドリフト領域１４は、例えば、Ｎ（窒素）をｎ型不純物として含む。ドリフト領域１４のｎ型不純物の濃度は、例えば、１×１０１４ｃｍ−３以上１×１０１７ｃｍ−３以下である。 n - -type drift region 14 is provided between the p-well region 16 and the SiC substrate 10. The drift region 14 contains, for example, N (nitrogen) as an n-type impurity. The concentration of n-type impurities in the drift region 14 is, for example, 1 × 10 14 cm -3 or more and 1 × 10 17 cm -3 or less.

ｐ型のｐウェル領域１６は、ソース領域１８とＳｉＣ基板１０との間に設けられる。ｐウェル領域１６は、ＭＩＳＦＥＴ１００のチャネル領域として機能する。 The p-type p-well region 16 is provided between the source region 18 and the SiC substrate 10. The p-well region 16 functions as a channel region of the MISFET 100.

ｐウェル領域１６は、例えば、Ａｌ（アルミニウム）をｐ型不純物として含む。ｐウェル領域１６のｐ型不純物の濃度は、例えば、５×１０１５ｃｍ−３以上１×１０１８ｃｍ−３以下である。ｐウェル領域１６の深さは、例えば、０．６μｍ以上１．２μｍ以下である。 The p-well region 16 contains, for example, Al (aluminum) as a p-type impurity. The concentration of p-type impurities in the p-well region 16 is, for example, 5 × 10 15 cm -3 or more and 1 × 10 18 cm -3 or less. The depth of the p-well region 16 is, for example, 0.6 μm or more and 1.2 μm or less.

ｎ＋型のソース領域１８は、ｐウェル領域１６内に設けられる。ソース領域１８の一部は、ＳｉＣ層１２の表面に接する。 The n + type source region 18 is provided in the p-well region 16. A part of the source region 18 is in contact with the surface of the SiC layer 12.

ソース領域１８は、例えば、Ｎ（窒素）をｎ型不純物として含む。ソース領域１８のｎ型不純物の濃度は、例えば、１×１０１８ｃｍ−３以上１×１０２２ｃｍ−３ｃｍ−３以下である。ソース領域１８の深さは、ｐウェル領域１６の深さよりも浅い。ソース領域１８の深さは、例えば０．３μｍ程度である。 The source region 18 contains, for example, N (nitrogen) as an n-type impurity. The concentration of n-type impurities in the source region 18 is, for example, 1 × 10 18 cm -3 or more and 1 × 10 22 cm -3 cm -3 or less. The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, about 0.3 μm.

また、ｐ＋型のｐウェルコンタクト領域２０は、ｐウェル領域１６内に設けられる。ｐウェルコンタクト領域２０は、ソース領域１８の側方に設けられる。 Further, the p + type p-well contact region 20 is provided in the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18.

ｐウェルコンタクト領域２０は、例えば、Ａｌ（アルミニウム）をｐ型不純物として含有する。ｐウェルコンタクト領域２０のｐ型不純物の濃度は、ｐウェル領域１６のｐ型不純物の濃度よりも高い。例えば、１×１０１８ｃｍ−３以上１×１０２２ｃｍ−３以下である。ｐウェルコンタクト領域２０の深さは、ｐウェル領域１６の深さよりも浅く、例えば０．３μｍ程度である。 The p-well contact region 20 contains, for example, Al (aluminum) as a p-type impurity. The concentration of p-type impurities in the p-well contact region 20 is higher than the concentration of p-type impurities in the p-well region 16. For example, it is 1 × 10 18 cm -3 or more and 1 × 10 22 cm -3 or less. The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16, for example, about 0.3 μm.

トレンチ５０は、ＳｉＣ層１２に設けられる。トレンチ５０の側面は、例えば、ｍ面又はａ面となっている。トレンチ５０の深さは、ｐウェル領域１６の最大深さよりも浅い。 The trench 50 is provided in the SiC layer 12. The side surface of the trench 50 is, for example, m-plane or a-plane. The depth of the trench 50 is shallower than the maximum depth of the p-well region 16.

ｐウェル領域１６とドリフト領域１４の境界１５は、トレンチ５０の側面に接する。
ｐウェル領域１６とドリフト領域１４の境界１５は、第１の領域１５ａ、第２の領域１５ｂ、第３の領域１５ｃ、第４の領域１５ｄを備える。 The boundary 15 between the p-well region 16 and the drift region 14 touches the side surface of the trench 50.
The boundary 15 between the p-well region 16 and the drift region 14 includes a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d.

ＳｉＣ層１２の表面からの第１の領域１５ａの距離は、トレンチ５０から離れるにしたがって大きくなる。第１の領域１５ａは、第１の傾斜角（図１中のθ）を有する。第１の傾斜角（図１中のθ）は０度よりも大きい。第１の領域１５ａとトレンチ５０の側面との距離（図１中のｄ）は、０μｍ以上０．３μｍ以下である。 The distance of the first region 15a from the surface of the SiC layer 12 increases as the distance from the trench 50 increases. The first region 15a has a first tilt angle (θ in FIG. 1). The first tilt angle (θ in FIG. 1) is larger than 0 degrees. The distance between the first region 15a and the side surface of the trench 50 (d in FIG. 1) is 0 μm or more and 0.3 μm or less.

第２の領域１５ｂは、ＳｉＣ層１２の表面に略平行である。第２の領域１５ｂは、第１の領域１５ａとトレンチ５０との間に設けられる。第２の領域１５ｂはトレンチ５０の側面に接する。 The second region 15b is substantially parallel to the surface of the SiC layer 12. The second region 15b is provided between the first region 15a and the trench 50. The second region 15b is in contact with the side surface of the trench 50.

第３の領域１５ｃは、ＳｉＣ層１２の表面に略平行である。第３の領域１５ｃとトレンチ５０との間に第１の領域１５ａが設けられる。 The third region 15c is substantially parallel to the surface of the SiC layer 12. A first region 15a is provided between the third region 15c and the trench 50.

第４の領域１５ｄは、ＳｉＣ層１２の表面に略垂直である。第４の領域１５ｄとトレンチ５０との間に第１の領域１５ａが設けられる。第４の領域１５ｄは、第３の領域１５ｃと第１の領域１５ａとの間に設けられる。 The fourth region 15d is substantially perpendicular to the surface of the SiC layer 12. A first region 15a is provided between the fourth region 15d and the trench 50. The fourth region 15d is provided between the third region 15c and the first region 15a.

なお、ｐウェル領域１６とドリフト領域１４の境界１５の形状は、例えば、走査型静電容量顕微鏡法（Ｓｃａｎｎｉｎｇ Ｃａｐａｃｉｔａｎｃｅ Ｍｉｃｒｏｓｃｏｐｙ）により観察することが可能である。 The shape of the boundary 15 between the p-well region 16 and the drift region 14 can be observed, for example, by scanning capacitance microscopy (Scanning Capacitance Microscopy).

ゲート絶縁膜２８は、トレンチ５０の側面上及び底面上に設けられる。ゲート絶縁膜２８の少なくとも一部は、ソース領域１８、ｐウェル領域１６、及び、ドリフト領域１４に接する。ゲート絶縁膜２８は、ＳｉＣ層１２とゲート電極３０との間に設けられる。 The gate insulating film 28 is provided on the side surface and the bottom surface of the trench 50. At least a part of the gate insulating film 28 is in contact with the source region 18, the p-well region 16, and the drift region 14. The gate insulating film 28 is provided between the SiC layer 12 and the gate electrode 30.

ゲート絶縁膜２８には、例えば、酸化膜が適用される。ゲート絶縁膜２８には、例えば、シリコン酸化膜、シリコン酸窒化膜、又は、ｈｉｇｈ−ｋ絶縁膜が適用可能である。 For example, an oxide film is applied to the gate insulating film 28. For the gate insulating film 28, for example, a silicon oxide film, a silicon oxynitride film, or a high-k insulating film can be applied.

ゲート電極３０は、ゲート絶縁膜２８上に設けられる。ゲート電極３０には、例えば、ドーピングされたポリシリコン等が適用可能である。 The gate electrode 30 is provided on the gate insulating film 28. For example, doped polysilicon or the like can be applied to the gate electrode 30.

層間絶縁膜３２は、ゲート電極３０上に設けられる。層間絶縁膜３２は、例えば、シリコン酸化膜で形成される。 The interlayer insulating film 32 is provided on the gate electrode 30. The interlayer insulating film 32 is formed of, for example, a silicon oxide film.

ソース電極３４は、ＳｉＣ層１２上に設けられる。ソース電極３４は、ソース領域１８とｐウェルコンタクト領域２０とに電気的に接続される。ソース電極３４は、ｐウェル領域１６に電位を与えるｐウェル電極としても機能する。 The source electrode 34 is provided on the SiC layer 12. The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies an electric potential to the p-well region 16.

ソース電極３４は、導電性の材料である。ソース電極３４は、例えば、金属又は金属シリサイドである。ソース電極３４は、例えば、ニッケルシリサイド層と、ニッケルシリサイド層上のアルミニウム（Ａｌ）層の積層構造を備える。 The source electrode 34 is a conductive material. The source electrode 34 is, for example, metal or metal silicide. The source electrode 34 includes, for example, a laminated structure of a nickel silicide layer and an aluminum (Al) layer on the nickel silicide layer.

ドレイン電極３６は、ＳｉＣ基板１０のＳｉＣ層１２と反対側、すなわち、裏面側に設けられる。ドレイン電極３６は、ＳｉＣ基板１０と電気的に接続される。 The drain electrode 36 is provided on the side opposite to the SiC layer 12 of the SiC substrate 10, that is, on the back surface side. The drain electrode 36 is electrically connected to the SiC substrate 10.

ドレイン電極３６は、導電性の材料である。ドレイン電極３６は、例えば、金属又は金属シリサイドである。ドレイン電極３６は、例えば、ニッケルシリサイド層と、ニッケルシリサイド層上の金（Ａｕ）層の積層構造を備える。 The drain electrode 36 is a conductive material. The drain electrode 36 is, for example, metal or metal silicide. The drain electrode 36 includes, for example, a laminated structure of a nickel silicide layer and a gold (Au) layer on the nickel silicide layer.

なお、本実施形態において、ｎ型不純物は例えば、Ｎ（窒素）やＰ（リン）が好ましいが、Ａｓ（ヒ素）あるいはＳｂ（アンチモン）等を適用することも可能である。また、ｐ型不純物は例えば、Ａｌ（アルミニウム）が好ましいが、Ｂ（ボロン）、Ｇａ（ガリウム）、Ｉｎ（インジウム）等を適用することも可能である。 In the present embodiment, for example, N (nitrogen) or P (phosphorus) is preferable as the n-type impurity, but As (arsenic), Sb (antimony), or the like can also be applied. Further, for example, Al (aluminum) is preferable as the p-type impurity, but B (boron), Ga (gallium), In (indium) and the like can also be applied.

図２は、本実施形態の半導体装置であるＭＩＳＦＥＴの構成の別の一例を示す模式断面図である。 FIG. 2 is a schematic cross-sectional view showing another example of the configuration of the MISFET which is the semiconductor device of the present embodiment.

ＭＩＳＦＥＴ１０１は、第１の領域１５ａとトレンチ５０の側面との距離が０μｍの場合を示す。すなわち、ＭＩＳＦＥＴ１０１では、第２の領域１５ｂが無く、第１の領域１５ａがトレンチ５０の側面に直接接する。 MISFET 101 shows a case where the distance between the first region 15a and the side surface of the trench 50 is 0 μm. That is, in the MISFET 101, there is no second region 15b, and the first region 15a is in direct contact with the side surface of the trench 50.

次に、本実施形態の半導体装置の製造方法の一例について説明する。図３−図７は、本実施形態の半導体装置の製造方法において、製造途中の半導体装置を示す模式断面図である。 Next, an example of the method for manufacturing the semiconductor device of the present embodiment will be described. 3 is a schematic cross-sectional view showing a semiconductor device in the process of being manufactured in the method of manufacturing the semiconductor device of the present embodiment.

まず、表面がシリコン面、裏面がカーボン面のｎ＋型のＳｉＣ基板１０を準備する。次に、ＳｉＣ基板１０の表面上に、エピタキシャル成長法により、ｎ−型のＳｉＣ層１２を形成する（図３）。 First, an n + type SiC substrate 10 having a silicon surface on the front surface and a carbon surface on the back surface is prepared. Next, on the surface of the SiC substrate 10, by epitaxial growth, n - -type SiC layer 12 (FIG. 3).

次に、公知のフォトリソグラフィー法により所定の領域にフォトレジスト６０を形成する（図４）。 Next, the photoresist 60 is formed in a predetermined region by a known photolithography method (FIG. 4).

次に、熱処理によりフォトレジスト６０を熱収縮させる。フォトレジスト６０は、熱収縮により、その側面がテーパ形状になる。 Next, the photoresist 60 is heat-shrinked by heat treatment. The side surface of the photoresist 60 becomes tapered due to heat shrinkage.

そして、フォトレジスト６０をマスクに、ＳｉＣ層１２にｐ型不純物をイオン注入する（図５）。ｐ型不純物が、フォトレジスト６０を通過してＳｉＣ層１２に達するよう、ｐ型不純物の加速エネルギーを設定する。 Then, using the photoresist 60 as a mask, the p-type impurities are ion-implanted into the SiC layer 12 (FIG. 5). The acceleration energy of the p-type impurity is set so that the p-type impurity passes through the photoresist 60 and reaches the SiC layer 12.

ｐ型不純物をイオン注入によりｐウェル領域１６を形成する。ｐウェル領域１６とＳｉＣ基板１０との間がドリフト領域１４となる。ｐ型不純物は、例えば、アルミニウム（Ａｌ）である。 A p-well region 16 is formed by ion implantation of p-type impurities. The area between the p-well region 16 and the SiC substrate 10 is the drift region 14. The p-type impurity is, for example, aluminum (Al).

フォトレジスト６０の形状が、ｐウェル領域１６とドリフト領域１４の境界１５の形状に反映される。第１の領域１５ａ、第２の領域１５ｂ、第３の領域１５ｃ、第４の領域１５ｄを有する境界１５が形成される。 The shape of the photoresist 60 is reflected in the shape of the boundary 15 between the p-well region 16 and the drift region 14. A boundary 15 having a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d is formed.

次に、ＳｉＣ層１２にトレンチ５０を形成する（図６）。トレンチ５０は、公知のリソグラフィー法及びドライエッチング法により形成される。 Next, a trench 50 is formed in the SiC layer 12 (FIG. 6). The trench 50 is formed by a known lithography method and dry etching method.

次に、トレンチ５０の側面上及び底面上にゲート絶縁膜２８を形成する。ゲート絶縁膜２８は、例えば、トレンチ５０の側面及び底面を熱酸化することにより形成する。ゲート絶縁膜２８は、ＬＰＣＶＤ法により形成することも可能である。次に、公知の方法で、ゲート絶縁膜２８上にゲート電極３０を形成する（図７）。ゲート電極３０は、例えば、ＬＰＣＶＤ法により形成されるドーピングされたポリシリコンである。 Next, the gate insulating film 28 is formed on the side surface and the bottom surface of the trench 50. The gate insulating film 28 is formed, for example, by thermally oxidizing the side surface and the bottom surface of the trench 50. The gate insulating film 28 can also be formed by the LPCVD method. Next, the gate electrode 30 is formed on the gate insulating film 28 by a known method (FIG. 7). The gate electrode 30 is, for example, doped polysilicon formed by the LPCVD method.

その後、公知のプロセスにより、層間絶縁膜３２、ソース電極３４、ドレイン電極３６を形成し、図１に示す本実施形態のＭＩＳＦＥＴ１００が製造される。 Then, the interlayer insulating film 32, the source electrode 34, and the drain electrode 36 are formed by a known process, and the MISFET 100 of the present embodiment shown in FIG. 1 is manufactured.

以下、本実施形態の半導体装置の作用及び効果について説明する。 Hereinafter, the operation and effect of the semiconductor device of the present embodiment will be described.

トレンチゲート型のＭＩＳＦＥＴでは、ＭＩＳＦＥＴのオフ状態において、トレンチ底部での電界集中により、ゲート絶縁膜の耐圧が低くなるという問題がある。特に、トレンチの角部での電界集中により、ゲート絶縁膜の耐圧が低下し、ＭＩＳＦＥＴの耐圧が低下する。 The trench gate type MOSFET has a problem that the withstand voltage of the gate insulating film is lowered due to the electric field concentration at the bottom of the trench when the MOSFET is off. In particular, due to the concentration of the electric field at the corner of the trench, the withstand voltage of the gate insulating film is lowered, and the withstand voltage of the MISFET is lowered.

図８は、比較形態のＭＩＳＦＥＴの構成の一例を示す模式断面図である。トレンチ底部での電界集中を緩和するために、ｐウェル領域１６の一部の深さを深くした形態である。ＭＩＳＦＥＴ８００のオフ状態において、深いｐウェル領域１６から、トレンチ５０側に空乏層が伸びることにより、トレンチの角部での電界が緩和する。したがって、ゲート絶縁膜の耐圧が向上する。 FIG. 8 is a schematic cross-sectional view showing an example of the configuration of the MISFET in the comparative form. In order to alleviate the electric field concentration at the bottom of the trench, a part of the p-well region 16 is deepened. In the off state of the MISFET 800, the depletion layer extends from the deep p-well region 16 to the trench 50 side, so that the electric field at the corner of the trench is relaxed. Therefore, the withstand voltage of the gate insulating film is improved.

一方、ＭＩＳＦＥＴ８００のオン状態においては、深いｐウェル領域１６が存在するため、ｐウェル領域１６とトレンチ５０の側面との間のドリフト領域１４ａの抵抗が上昇する。したがって、ＭＩＳＦＥＴ８００のオン抵抗が増大するという新たな問題が生ずる。 On the other hand, in the ON state of the MISFET 800, since the deep p-well region 16 exists, the resistance of the drift region 14a between the p-well region 16 and the side surface of the trench 50 increases. Therefore, a new problem arises in which the on-resistance of the MISFET 800 increases.

図９は、本実施形態のＭＩＳＦＥＴの構成の別の一例を示す模式断面図である。図９は、図２のＭＩＳＦＥＴ１０１と同様の構成を備える。 FIG. 9 is a schematic cross-sectional view showing another example of the configuration of the MISFET of the present embodiment. FIG. 9 has the same configuration as the MISFET 101 of FIG.

ＭＩＳＦＥＴ１０１のチャネル長（図９中のＬｃｈ）を変化させて、ゲート絶縁膜中の最大電界とオン抵抗との関係をシミュレーションにより求めた。チャネル長は、０．１μｍ、０．２μｍ、０．３μｍとした。チャネル長を変化させる際、境界１５の形状は維持した状態で上下させた。また、第１の傾斜角θは４５度に固定した。 The channel length (Lch in FIG. 9) of the MISFET 101 was changed, and the relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation. The channel lengths were 0.1 μm, 0.2 μm, and 0.3 μm. When the channel length was changed, the shape of the boundary 15 was maintained and moved up and down. Further, the first inclination angle θ was fixed at 45 degrees.

同様に、比較形態のＭＩＳＦＥＴ８００についても、チャネル長（図８中のＬｃｈ）を変化させて、ゲート絶縁膜中の最大電界とオン抵抗との関係をシミュレーションにより求めた。チャネル長は、０．１μｍ、０．２μｍ、０．３μｍ、０．４μｍ、０．５μｍ、０．６μｍとした。 Similarly, for the MISFET 800 in the comparative form, the relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation by changing the channel length (Lch in FIG. 8). The channel lengths were 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm.

図１０は、本実施形態の半導体装置の作用・効果の説明図である。図１０は、ゲート絶縁膜２８中の最大電界とオン抵抗との関係を示す図である。図１０から明らかなように、ゲート絶縁膜２８中の最大電界とオン抵抗とは、実施形態及び比較形態いずれの場合もトレードオフの関係にあることが分かる。 FIG. 10 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 10 is a diagram showing the relationship between the maximum electric field in the gate insulating film 28 and the on-resistance. As is clear from FIG. 10, it can be seen that the maximum electric field and the on-resistance in the gate insulating film 28 are in a trade-off relationship in both the embodiment and the comparative embodiment.

ＭＩＳＦＥＴ１０１、８００のチャネル長（Ｌｃｈ）が短くなると、ｐウェル領域１６から、伸びる空乏層によるトレンチ５０の角部での電界緩和効果が減少し、ゲート絶縁膜２８中の最大電界が大きくなる。したがって、ゲート絶縁膜２８の耐圧が低下する。 When the channel length (Lch) of the MISFETs 101 and 800 is shortened, the electric field relaxation effect at the corners of the trench 50 by the depletion layer extending from the p-well region 16 is reduced, and the maximum electric field in the gate insulating film 28 is increased. Therefore, the withstand voltage of the gate insulating film 28 decreases.

また、ＭＩＳＦＥＴ１０１、８００のチャネル長（Ｌｃｈ）が短くなると、チャネル抵抗が小さくなり、オン抵抗が減少する。 Further, when the channel length (Lch) of the MISFETs 101 and 800 is shortened, the channel resistance is reduced and the on-resistance is reduced.

図１０から明らかなように、実施形態の場合は、比較形態の場合と比べ、ゲート絶縁膜２８中の最大電界とオン抵抗とのトレードオフ関係が改善していることが分かる。実施形態の場合、（１）図９中の白矢印で示すように、傾斜した第１の領域１５ａに沿ってオン電流が流れるため、比較形態の場合に比べてオン抵抗が低下すること、（２）傾斜した第１の領域１５ａからトレンチ５０に向かって空乏層が伸びるため、比較形態に比べてトレンチ５０の角部での電界緩和効果が大きくなることが理由であると考えられる。したがって、同一のオン抵抗で比較した場合、実施形態のＭＩＳＦＥＴ１０１の場合、ゲート絶縁膜２８中の最大電界が緩和し、ゲート絶縁膜２８の耐圧が向上する。 As is clear from FIG. 10, in the case of the embodiment, the trade-off relationship between the maximum electric field and the on-resistance in the gate insulating film 28 is improved as compared with the case of the comparative embodiment. In the case of the embodiment, (1) as shown by the white arrow in FIG. 9, the on-current flows along the inclined first region 15a, so that the on-resistance is lowered as compared with the case of the comparative embodiment. 2) Since the depletion layer extends from the inclined first region 15a toward the trench 50, it is considered that the reason is that the electric field relaxation effect at the corner of the trench 50 is larger than that in the comparative form. Therefore, when compared with the same on-resistance, in the case of the MISFET 101 of the embodiment, the maximum electric field in the gate insulating film 28 is relaxed, and the withstand voltage of the gate insulating film 28 is improved.

図１１は、本実施形態の半導体装置の作用・効果の説明図である。図１に示したＭＩＳＦＥＴ１００の構造において、第１の領域１５ａとトレンチ５０の側面との距離（図１中のｄ）と、ＭＩＳＦＥＴ１００の耐圧との関係をシミュレーションで求めた結果を示す。 FIG. 11 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. In the structure of the MISFET 100 shown in FIG. 1, the result of simulating the relationship between the distance between the first region 15a and the side surface of the trench 50 (d in FIG. 1) and the withstand voltage of the MISFET 100 is shown.

縦軸に示す耐圧は、ソース電極３４とドレイン電極３６間の耐圧である。シミュレーションでは、チャネル長（図１のＬｃｈ）を０．１μｍに固定している。 The withstand voltage shown on the vertical axis is the withstand voltage between the source electrode 34 and the drain electrode 36. In the simulation, the channel length (Lch in FIG. 1) is fixed at 0.1 μm.

図１１に示すように、第１の領域１５ａとトレンチ５０の側面との距離が、０．３μｍを超えると、急激に耐圧が低下する。０．２μｍ以下では安定して高い耐圧が維持できる。 As shown in FIG. 11, when the distance between the first region 15a and the side surface of the trench 50 exceeds 0.3 μm, the withstand voltage sharply decreases. When it is 0.2 μm or less, a high withstand voltage can be stably maintained.

本実施形態のＭＩＳＦＥＴは、傾斜した第１の領域１５ａを有する。第１の領域１５ａが傾斜しているため、ＭＩＳＦＥＴのオフ状態において、ドリフト領域１４からチャネル領域へ向かう空乏層の伸びが抑制される。したがって、チャネル長が短くなった場合でも、ＭＩＳＦＥＴのパンチスルーが抑制され、ＭＩＳＦＥＴの耐圧が向上する。 The MISFET of this embodiment has an inclined first region 15a. Since the first region 15a is inclined, the elongation of the depletion layer from the drift region 14 to the channel region is suppressed in the off state of the MOSFET. Therefore, even when the channel length is shortened, the punch-through of the MISFET is suppressed and the withstand voltage of the MISFET is improved.

もっとも、第１の領域１５ａとトレンチ５０の側面との距離が遠くなりすぎると、ドリフト領域１４からチャネル領域へ向かう空乏層の伸びの抑制効果が減じる。したがって、ＭＩＳＦＥＴの耐圧が低下する。 However, if the distance between the first region 15a and the side surface of the trench 50 becomes too large, the effect of suppressing the elongation of the depletion layer from the drift region 14 to the channel region is reduced. Therefore, the withstand voltage of the MISFET is lowered.

図１１に示した結果より、第１の領域１５ａとトレンチ５０の側面との距離（図１中のｄ）は、０μｍ以上０．３μｍ以下であることが、ＭＩＳＦＥＴの耐圧を向上させる観点から望ましい。第１の領域１５ａとトレンチ５０の側面との距離（図１中のｄ）は、０．２μｍ以下であることが、より望ましく、０．１μｍ以下であることが、さらに望ましい。 From the results shown in FIG. 11, it is desirable that the distance between the first region 15a and the side surface of the trench 50 (d in FIG. 1) is 0 μm or more and 0.3 μm or less from the viewpoint of improving the withstand voltage of the MISFET. .. The distance between the first region 15a and the side surface of the trench 50 (d in FIG. 1) is more preferably 0.2 μm or less, and further preferably 0.1 μm or less.

図１２は、本実施形態の半導体装置の作用・効果を示す図である。図９に示すＭＩＳＦＥＴ１０１の第１の領域１５ａの第１の傾斜角θを変化させて、ゲート絶縁膜中の最大電界とオン抵抗の関係をシミュレーションにより求めた。ソース電極３４とドレイン電極３６間に印加する電圧を１２００Ｖとした。 FIG. 12 is a diagram showing the operation and effect of the semiconductor device of the present embodiment. The relationship between the maximum electric field and the on-resistance in the gate insulating film was obtained by simulation by changing the first inclination angle θ of the first region 15a of the MISFET 101 shown in FIG. The voltage applied between the source electrode 34 and the drain electrode 36 was set to 1200 V.

プレーナ型のＭＩＳＦＥＴよりもオン抵抗を低減するためには、オン抵抗は２ｍΩｃｍ２以下であることが望ましい。また、ゲート絶縁膜２８がシリコン酸化膜である場合、ゲート絶縁膜２８の耐圧を確保する観点から最大電界は３ＭＶ／ｃｍ以下であることが望ましい。したがって、第１の傾斜角θは１５度以上６０度以下であることが望ましい。 In order to reduce the on-resistance as compared with the planar type MOSFET, it is desirable that the on-resistance is 2 mΩcm 2 or less. When the gate insulating film 28 is a silicon oxide film, the maximum electric field is preferably 3 MV / cm or less from the viewpoint of ensuring the withstand voltage of the gate insulating film 28. Therefore, it is desirable that the first inclination angle θ is 15 degrees or more and 60 degrees or less.

なお、ゲート絶縁膜２８の耐圧を向上させる観点から、トレンチ５０の底面上のゲート絶縁膜２８の膜厚が、トレンチ５０の側面上のゲート絶縁膜２８の膜厚よりも厚いことが望ましい。 From the viewpoint of improving the withstand voltage of the gate insulating film 28, it is desirable that the film thickness of the gate insulating film 28 on the bottom surface of the trench 50 is thicker than the film thickness of the gate insulating film 28 on the side surface of the trench 50.

本実施形態のＭＩＳＦＥＴによれば、ゲート絶縁膜２８中の最大電界とオン抵抗とのトレードオフ関係が改善される。したがって、ゲート絶縁膜２８の耐圧が高くなる。また、チャネル領域でのパンチスルーが抑制され、ソース−ドレイン間の耐圧が高くなる。よって、高い耐圧を備えたＭＩＳＦＥＴが実現できる。 According to the MISFET of the present embodiment, the trade-off relationship between the maximum electric field and the on-resistance in the gate insulating film 28 is improved. Therefore, the withstand voltage of the gate insulating film 28 becomes high. In addition, punch-through in the channel region is suppressed, and the withstand voltage between the source and drain increases. Therefore, a MOSFET having a high withstand voltage can be realized.

（第２の実施形態）
本実施形態の半導体装置は、第２のＳｉＣ領域と第３のＳｉＣ領域との境界が第４の領域を備えないこと以外は、第１の実施形態と同様である。したがって、第１の実施形態と重複する内容については記述を省略する。 (Second Embodiment)
The semiconductor device of the present embodiment is the same as that of the first embodiment except that the boundary between the second SiC region and the third SiC region does not include the fourth region. Therefore, the description of the content overlapping with the first embodiment will be omitted.

図１３は、本実施形態の半導体装置であるＭＩＳＦＥＴの構成を示す模式断面図である。このＭＩＳＦＥＴ２００は、トレンチゲート型のＭＯＳＦＥＴである。 FIG. 13 is a schematic cross-sectional view showing the configuration of the MISFET which is the semiconductor device of the present embodiment. The MISFET 200 is a trench gate type MOSFET.

ｐウェル領域１６とドリフト領域１４の境界１５は、トレンチ５０の側面に接する。ｐウェル領域１６とドリフト領域１４の境界１５は、第１の領域１５ａ、第３の領域１５ｃを備える。 The boundary 15 between the p-well region 16 and the drift region 14 touches the side surface of the trench 50. The boundary 15 between the p-well region 16 and the drift region 14 includes a first region 15a and a third region 15c.

第１の領域１５ａは、トレンチ５０の側面に接する。また、ｐウェル領域１６とドリフト領域１４の境界１５は、角度が９０度以下の屈曲部を備えない。 The first region 15a is in contact with the side surface of the trench 50. Further, the boundary 15 between the p-well region 16 and the drift region 14 does not have a bent portion having an angle of 90 degrees or less.

図１４は、比較形態のＭＩＳＦＥＴの構成の一例を示す模式断面図である。トレンチ５０底部での電界集中を緩和するために、ｐウェル領域１６の一部の深さを深くした形態である。ＭＩＳＦＥＴ９００のオフ状態において、深いｐウェル領域１６から、トレンチ５０側に空乏層が伸びることにより、トレンチ５０角部での電界が緩和する。したがって、ゲート絶縁膜２８の耐圧が向上する。 FIG. 14 is a schematic cross-sectional view showing an example of the configuration of the MISFET in the comparative form. In order to alleviate the electric field concentration at the bottom of the trench 50, a part of the p-well region 16 is deepened. In the off state of the MISFET 900, the depletion layer extends from the deep p-well region 16 to the trench 50 side, so that the electric field at the corner of the trench 50 is relaxed. Therefore, the withstand voltage of the gate insulating film 28 is improved.

ＭＩＳＦＥＴ２００のチャネル長（図１３中のＬｃｈ）を変化させて、ゲート絶縁膜２８中の最大電界とオン抵抗との関係をシミュレーションにより求めた。チャネル長は、０．１μｍ、０．２μｍ、０．３μｍ、０．４μｍ、０．５μｍ、０．６μｍとした。第１の傾斜角θは４５度に固定した。 The channel length (Lch in FIG. 13) of the MISFET 200 was changed, and the relationship between the maximum electric field in the gate insulating film 28 and the on-resistance was obtained by simulation. The channel lengths were 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm. The first inclination angle θ was fixed at 45 degrees.

同様に、比較形態のＭＩＳＦＥＴ９００についても、チャネル長（図１４中のＬｃｈ）を変化させて、ゲート絶縁膜中の最大電界とオン抵抗との関係をシミュレーションにより求めた。チャネル長は、０．２μｍ、０．３μｍ、０．４μｍ、０．５μｍ、０．６μｍとした。 Similarly, for the comparative form of the MISFET 900, the relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation by changing the channel length (Lch in FIG. 14). The channel lengths were 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm.

図１５は、本実施形態の半導体装置の作用・効果の説明図である。図１５は、ゲート絶縁膜中の最大電界とオン抵抗との関係を示す図である。 FIG. 15 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 15 is a diagram showing the relationship between the maximum electric field in the gate insulating film and the on-resistance.

図１５から明らかなように、実施形態の場合は、比較形態の場合と比べ、ゲート絶縁膜２８中の最大電界とオン抵抗とのトレードオフ関係が改善していることが分かる。したがって、同一のオン抵抗で比較した場合、実施形態のＭＩＳＦＥＴ２００の場合ゲート絶縁膜２８中の最大電界が緩和し、ゲート絶縁膜２８の耐圧が向上する。 As is clear from FIG. 15, in the case of the embodiment, the trade-off relationship between the maximum electric field and the on-resistance in the gate insulating film 28 is improved as compared with the case of the comparative embodiment. Therefore, when compared with the same on-resistance, in the case of the MISFET 200 of the embodiment, the maximum electric field in the gate insulating film 28 is relaxed, and the withstand voltage of the gate insulating film 28 is improved.

本実施形態のＭＩＳＦＥＴによれば、第１の実施形態のＭＩＳＦＥＴと同様、ゲート絶縁膜２８の耐圧及びソース−ドレイン間の耐圧が高くなる。また、境界１５は角度が９０度以下の屈曲部を備えないため、ＭＩＳＦＥＴのオフ状態における境界１５での電界集中が抑制され、境界１５での絶縁破壊が抑制される。よって、さらに高い耐圧を備えたＭＩＳＦＥＴが実現できる。 According to the MISFET of the present embodiment, the withstand voltage of the gate insulating film 28 and the withstand voltage between the source and the drain are increased as in the MISFET of the first embodiment. Further, since the boundary 15 does not have a bent portion having an angle of 90 degrees or less, the electric field concentration at the boundary 15 in the off state of the MISFET is suppressed, and dielectric breakdown at the boundary 15 is suppressed. Therefore, a MISFET having a higher withstand voltage can be realized.

（第３の実施形態）
本実施形態の半導体装置は、ＳｉＣ層内にトレンチの底面と第３のＳｉＣ領域との間に設けられ、底面に接する第２導電型の第５のＳｉＣ領域を、更に備えること以外は、第１の実施形態と同様である。したがって、第１の実施形態と重複する内容については記述を省略する。 (Third Embodiment)
The semiconductor device of the present embodiment is provided in the SiC layer between the bottom surface of the trench and the third SiC region, and is provided with a second conductive type fifth SiC region in contact with the bottom surface. It is the same as the embodiment of 1. Therefore, the description of the content overlapping with the first embodiment will be omitted.

図１６は、本実施形態の半導体装置であるＭＩＳＦＥＴの構成を示す模式断面図である。このＭＩＳＦＥＴ３００は、トレンチゲート型のＭＯＳＦＥＴである。 FIG. 16 is a schematic cross-sectional view showing the configuration of the MISFET which is the semiconductor device of the present embodiment. The MISFET 300 is a trench gate type MOSFET.

ＭＩＳＦＥＴ３００は、ＳｉＣ層１２内にｐ型の電界緩和領域４０を備える。電界緩和領域４０は、トレンチ５０の底面とドリフト領域１４との間に設けられる。電界緩和領域４０は、ＭＩＳＦＥＴ３００のオフ状態の際に、トレンチ５０底部での電界集中を緩和する機能を備える。 The MISFET 300 includes a p-type electric field relaxation region 40 in the SiC layer 12. The electric field relaxation region 40 is provided between the bottom surface of the trench 50 and the drift region 14. The electric field relaxation region 40 has a function of relaxing the electric field concentration at the bottom of the trench 50 when the MISFET 300 is off.

電界緩和領域４０は、例えば、Ａｌ（アルミニウム）をｐ型不純物として含む。電界緩和領域４０のｐ型不純物の濃度は、例えば、１×１０１７ｃｍ−３以上１×１０１９ｃｍ−３以下である。 The electric field relaxation region 40 contains, for example, Al (aluminum) as a p-type impurity. The concentration of p-type impurities in the electric field relaxation region 40 is, for example, 1 × 10 17 cm -3 or more and 1 × 10 19 cm -3 or less.

本実施形態のＭＩＳＦＥＴによれば、第１の実施形態のＭＩＳＦＥＴと同様、ゲート絶縁膜２８の耐圧及びソース−ドレイン間の耐圧が高くなる。また、電界緩和領域４０を備えることで、トレンチ５０底部でのゲート絶縁膜２８の耐圧が更に向上する。 According to the MISFET of the present embodiment, the withstand voltage of the gate insulating film 28 and the withstand voltage between the source and the drain are increased as in the MISFET of the first embodiment. Further, by providing the electric field relaxation region 40, the withstand voltage of the gate insulating film 28 at the bottom of the trench 50 is further improved.

（第４の実施形態）
本実施形態の半導体装置は、ソース電極３４がトレンチ内に設けられること以外は、第１の実施形態と同様である。したがって、第１の実施形態と重複する内容については記述を省略する。 (Fourth Embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that the source electrode 34 is provided in the trench. Therefore, the description of the content overlapping with the first embodiment will be omitted.

図１７は、本実施形態の半導体装置であるＭＩＳＦＥＴの構成を示す模式断面図である。このＭＩＳＦＥＴ４００は、トレンチゲート型のＭＯＳＦＥＴである。 FIG. 17 is a schematic cross-sectional view showing the configuration of the MISFET which is the semiconductor device of the present embodiment. This MISFET 400 is a trench gate type MOSFET.

ＭＩＳＦＥＴ４００は、ＳｉＣ層１２内に設けられたトレンチ５５内にソース電極３４が設けられている。トレンチ５５の底部又は側面にｐ＋型のｐウェルコンタクト領域２０が設けられる。 In the MISFET 400, the source electrode 34 is provided in the trench 55 provided in the SiC layer 12. A p + -shaped p-well contact region 20 is provided on the bottom or side surface of the trench 55.

本実施形態のＭＩＳＦＥＴによれば、第１の実施形態のＭＩＳＦＥＴと同様、ゲート絶縁膜２８の耐圧及びソース−ドレイン間の耐圧が高くなる。また、トレンチ５５内にソース電極３４を設けることでコンタクト構造の微細化が可能となる。 According to the MISFET of the present embodiment, the withstand voltage of the gate insulating film 28 and the withstand voltage between the source and the drain are increased as in the MISFET of the first embodiment. Further, by providing the source electrode 34 in the trench 55, the contact structure can be miniaturized.

また、トレンチ５５内にソース電極３４を設けることで深いｐウェル領域１６の形成が容易となる。すなわち、ＳｉＣ層１２にトレンチ５５を形成した後、トレンチ５５の底部へイオン注入を行いｐウェル領域１６を形成することで、深いｐウェル領域１６の形成が容易となる。 Further, by providing the source electrode 34 in the trench 55, it becomes easy to form the deep p-well region 16. That is, by forming the trench 55 in the SiC layer 12 and then implanting ions into the bottom of the trench 55 to form the p-well region 16, the deep p-well region 16 can be easily formed.

（第５の実施形態）
本実施形態の半導体装置は、ＭＩＳＦＥＴではなく、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）であること以外は、第１の実施形態と同様である。したがって、第１の実施形態と重複する内容については記述を省略する。 (Fifth Embodiment)
The semiconductor device of the present embodiment is the same as that of the first embodiment except that it is an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET. Therefore, the description of the content overlapping with the first embodiment will be omitted.

図１８は、本実施形態の半導体装置であるＩＧＢＴの構成を示す模式断面図である。ＩＧＢＴ５００は、ゲート絶縁膜及びゲート電極がトレンチ内に設けられたトレンチゲート型ＩＧＢＴである。 FIG. 18 is a schematic cross-sectional view showing the configuration of the IGBT, which is the semiconductor device of the present embodiment. The IGBT 500 is a trench gate type IGBT in which a gate insulating film and a gate electrode are provided in a trench.

ＩＧＢＴ５００は、ＳｉＣ基板１１０、ＳｉＣ層１２、ドリフト領域（第３のＳｉＣ領域）１４、界面１５、第１の領域１５ａ、第２の領域１５ｂ、第３の領域１５ｃ、第４の領域１５ｄ、ｐベース領域（第２のＳｉＣ領域）１１６、エミッタ領域（第１のＳｉＣ領域）１１８、ｐベースコンタクト領域（第４のＳｉＣ領域）１２０、ゲート絶縁膜（絶縁膜）２８、ゲート電極３０、層間絶縁膜３２、エミッタ電極（電極）１３４、コレクタ電極１３６、トレンチ５０を備える。 The IGBT 500 includes a SiC substrate 110, a SiC layer 12, a drift region (third SiC region) 14, an interface 15, a first region 15a, a second region 15b, a third region 15c, a fourth region 15d, p. Base region (second SiC region) 116, emitter region (first SiC region) 118, p base contact region (fourth SiC region) 120, gate insulating film (insulating film) 28, gate electrode 30, interlayer insulation A film 32, an emitter electrode (electrode) 134, a collector electrode 136, and a trench 50 are provided.

ＩＧＢＴ５００は、ｐ＋型のＳｉＣ基板１１０を備える。ＳｉＣ基板１１０は、例えばＡｌ（アルミニウム）をｐ型不純物として含む４Ｈ−ＳｉＣのＳｉＣ基板である。ｐ型不純物の不純物濃度は、例えば、１×１０１８ｃｍ−３以上１×１０２０ｃｍ−３以下である。ＳｉＣ基板１１０は、ＩＧＢＴ５００のコレクタ領域として機能する。 The IGBT 500 includes a p + type SiC substrate 110. The SiC substrate 110 is, for example, a 4H-SiC SiC substrate containing Al (aluminum) as a p-type impurity. The impurity concentration of the p-type impurity is, for example, 1 × 10 18 cm -3 or more and 1 × 10 20 cm -3 or less. The SiC substrate 110 functions as a collector region of the IGBT 500.

ＳｉＣ基板１１０の表面は、例えば、（０００１）面（シリコン面）に対し０度以上１０度以下傾斜した面である。ＳｉＣ基板１１０の裏面は、例えば、（０００−１）面（カーボン面）に対し０度以上１０度以下傾斜した面である。 The surface of the SiC substrate 110 is, for example, a surface inclined from 0 degrees or more and 10 degrees or less with respect to the (0001) surface (silicon surface). The back surface of the SiC substrate 110 is, for example, a surface inclined from 0 degrees or more and 10 degrees or less with respect to the (000-1) surface (carbon surface).

ＳｉＣ層１２は、ＳｉＣ基板１１０上に設けられる。ＳｉＣ層１２は、例えば、Ｎ（窒素）をｎ型不純物として含む。ＳｉＣ層１２のｎ型不純物の濃度は、例えば、１×１０１４ｃｍ−３以上１×１０１７ｃｍ−３以下である。ＳｉＣ層１２は、例えば、ＳｉＣ基板１１０上にエピタキシャル成長により形成されたＳｉＣのエピタキシャル成長層である。 The SiC layer 12 is provided on the SiC substrate 110. The SiC layer 12 contains, for example, N (nitrogen) as an n-type impurity. The concentration of n-type impurities in the SiC layer 12 is, for example, 1 × 10 14 cm -3 or more and 1 × 10 17 cm -3 or less. The SiC layer 12 is, for example, an epitaxial growth layer of SiC formed on the SiC substrate 110 by epitaxial growth.

ＳｉＣ層１２の表面も、シリコン面に対し０度以上１０度以下傾斜した面である。ＳｉＣ層１２の膜厚は、例えば、５μｍ以上１５０μｍ以下である。 The surface of the SiC layer 12 is also a surface inclined at 0 degrees or more and 10 degrees or less with respect to the silicon surface. The film thickness of the SiC layer 12 is, for example, 5 μm or more and 150 μm or less.

ドリフト領域（第３のＳｉＣ領域）１４、ｐベース領域（第２のＳｉＣ領域）１１６、エミッタ領域（第１のＳｉＣ領域）１１８、ｐベースコンタクト領域（第４のＳｉＣ領域）１２０は、ＳｉＣ層１２内に設けられる。 The drift region (third SiC region) 14, the p-base region (second SiC region) 116, the emitter region (first SiC region) 118, and the p-base contact region (fourth SiC region) 120 are SiC layers. It is provided in 12.

ｎ−型のドリフト領域１４は、ｐベース領域１１６とＳｉＣ基板１１０との間に設けられる。ドリフト領域１４は、例えば、Ｎ（窒素）をｎ型不純物として含む。ドリフト領域１４のｎ型不純物の濃度は、例えば、１×１０１４ｃｍ−３以上１×１０１７ｃｍ−３以下である。 The n - type drift region 14 is provided between the p-base region 116 and the SiC substrate 110. The drift region 14 contains, for example, N (nitrogen) as an n-type impurity. The concentration of n-type impurities in the drift region 14 is, for example, 1 × 10 14 cm -3 or more and 1 × 10 17 cm -3 or less.

ｐ型のｐベース領域１１６は、エミッタ領域１１８とＳｉＣ基板１１０との間に設けられる。ｐベース領域１１６は、ＩＧＢＴ５００のチャネル領域として機能する。 The p-type p-base region 116 is provided between the emitter region 118 and the SiC substrate 110. The p-base region 116 functions as a channel region of the IGBT 500.

ｐベース領域１１６は、例えば、Ａｌ（アルミニウム）をｐ型不純物として含む。ｐベース領域１１６のｐ型不純物の濃度は、例えば、５×１０１５ｃｍ−３以上１×１０１８ｃｍ−３以下である。ｐベース領域１１６の深さは、例えば、０．６μｍ以上１．２μｍ以下である。 The p-base region 116 contains, for example, Al (aluminum) as a p-type impurity. The concentration of p-type impurities in the p-base region 116 is, for example, 5 × 10 15 cm -3 or more and 1 × 10 18 cm -3 or less. The depth of the p-base region 116 is, for example, 0.6 μm or more and 1.2 μm or less.

ｎ＋型のエミッタ領域１１８は、ｐベース領域１１６内に設けられる。エミッタ領域１１８の一部は、ＳｉＣ層１２の表面に接する。 The n + type emitter region 118 is provided in the p-base region 116. A part of the emitter region 118 is in contact with the surface of the SiC layer 12.

エミッタ領域１１８は、例えば、Ｎ（窒素）をｎ型不純物として含む。エミッタ領域１１８のｎ型不純物の濃度は、例えば、１×１０１８ｃｍ−３以上１×１０２２ｃｍ−３ｃｍ−３以下である。エミッタ領域１１８の深さは、ｐベース領域１１６の深さよりも浅い。エミッタ領域１１８の深さは、例えば０．３μｍ程度である。 The emitter region 118 contains, for example, N (nitrogen) as an n-type impurity. The concentration of n-type impurities in the emitter region 118 is, for example, 1 × 10 18 cm -3 or more and 1 × 10 22 cm -3 cm -3 or less. The depth of the emitter region 118 is shallower than the depth of the p-base region 116. The depth of the emitter region 118 is, for example, about 0.3 μm.

また、ｐ＋型のｐベースコンタクト領域１２０は、ｐベース領域１１６内に設けられる。ｐベースコンタクト領域１２０は、エミッタ領域１１８の側方に設けられる。 Further, the p + type p-base contact region 120 is provided in the p-base region 116. The p-base contact region 120 is provided on the side of the emitter region 118.

ｐベースコンタクト領域１２０は、例えば、Ａｌ（アルミニウム）をｐ型不純物として含有する。ｐベースコンタクト領域１２０のｐ型不純物の濃度は、ｐベース領域１１６のｐ型不純物の濃度よりも高い。例えば、１×１０１８ｃｍ−３以上１×１０２２ｃｍ−３以下である。ｐベースコンタクト領域１２０の深さは、ｐベース領域１１６の深さよりも浅く、例えば０．３μｍ程度である。 The p-base contact region 120 contains, for example, Al (aluminum) as a p-type impurity. The concentration of p-type impurities in the p-base contact region 120 is higher than the concentration of p-type impurities in the p-base region 116. For example, it is 1 × 10 18 cm -3 or more and 1 × 10 22 cm -3 or less. The depth of the p-base contact region 120 is shallower than the depth of the p-base region 116, for example, about 0.3 μm.

トレンチ５０は、ＳｉＣ層１２に設けられる。トレンチ５０の側面は、例えば、ｍ面又はａ面となっている。トレンチ５０の深さは、ｐベース領域１１６の最大深さよりも浅い。 The trench 50 is provided in the SiC layer 12. The side surface of the trench 50 is, for example, m-plane or a-plane. The depth of the trench 50 is shallower than the maximum depth of the p-base region 116.

ｐベース領域１１６とドリフト領域１４の境界１５は、トレンチ５０の側面に接する。
ｐベース領域１１６とドリフト領域１４の境界１５は、第１の領域１５ａ、第２の領域１５ｂ、第３の領域１５ｃ、第４の領域１５ｄを備える。 The boundary 15 between the p-base region 116 and the drift region 14 touches the side surface of the trench 50.
The boundary 15 between the p-base region 116 and the drift region 14 includes a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d.

ＳｉＣ層１２の表面からの第１の領域１５ａの距離が、トレンチ５０から離れるにしたがって大きくなる。第１の領域１５ａは、第１の傾斜角（図１中のθ）を有する。第１の領域１５ａとトレンチ５０の側面との距離（図１中のｄ）は、０μｍ以上０．３μｍ以下である。 The distance of the first region 15a from the surface of the SiC layer 12 increases as the distance from the trench 50 increases. The first region 15a has a first tilt angle (θ in FIG. 1). The distance between the first region 15a and the side surface of the trench 50 (d in FIG. 1) is 0 μm or more and 0.3 μm or less.

第２の領域１５ｂは、ＳｉＣ層１２の表面に略平行である。第２の領域１５ｂは、第１の領域１５ａとトレンチ５０との間に設けられる。第２の領域１５ｂはトレンチ５０の側面に接する。 The second region 15b is substantially parallel to the surface of the SiC layer 12. The second region 15b is provided between the first region 15a and the trench 50. The second region 15b is in contact with the side surface of the trench 50.

第３の領域１５ｃは、ＳｉＣ層１２の表面に略平行である。第３の領域１５ｃとトレンチ５０との間に第１の領域１５ａが設けられる。 The third region 15c is substantially parallel to the surface of the SiC layer 12. A first region 15a is provided between the third region 15c and the trench 50.

第４の領域１５ｄは、ＳｉＣ層１２の表面に略垂直である。第４の領域１５ｄとトレンチ５０との間に第１の領域１５ａが設けられる。第４の領域１５ｄは、第３の領域１５ｃと第１の領域１５ａとの間に設けられる。 The fourth region 15d is substantially perpendicular to the surface of the SiC layer 12. A first region 15a is provided between the fourth region 15d and the trench 50. The fourth region 15d is provided between the third region 15c and the first region 15a.

なお、ｐベース領域１１６とドリフト領域１４の境界１５の形状は、例えば、走査型静電容量顕微鏡法（Ｓｃａｎｎｉｎｇ Ｃａｐａｃｉｔａｎｃｅ Ｍｉｃｒｏｓｃｏｐｙ）により観察することが可能である。 The shape of the boundary 15 between the p-base region 116 and the drift region 14 can be observed, for example, by scanning capacitance microscopy (Scanning Capacitance Microscope).

ゲート絶縁膜２８は、トレンチ５０の側面上及び底面上に設けられる。ゲート絶縁膜２８の少なくとも一部は、エミッタ領域１１８、ｐベース領域１１６、及び、ドリフト領域１４に接する。ゲート絶縁膜２８は、ＳｉＣ層１２とゲート電極３０との間に設けられる。 The gate insulating film 28 is provided on the side surface and the bottom surface of the trench 50. At least a part of the gate insulating film 28 is in contact with the emitter region 118, the p-base region 116, and the drift region 14. The gate insulating film 28 is provided between the SiC layer 12 and the gate electrode 30.

ゲート絶縁膜２８には、例えば、酸化膜が適用される。ゲート絶縁膜２８には、例えば、シリコン酸化膜、シリコン酸窒化膜、又は、ｈｉｇｈ−ｋ絶縁膜が適用可能である。 For example, an oxide film is applied to the gate insulating film 28. For the gate insulating film 28, for example, a silicon oxide film, a silicon oxynitride film, or a high-k insulating film can be applied.

ゲート電極３０は、ゲート絶縁膜２８上に設けられる。ゲート電極３０には、例えば、ドーピングされたポリシリコン等が適用可能である。 The gate electrode 30 is provided on the gate insulating film 28. For example, doped polysilicon or the like can be applied to the gate electrode 30.

層間絶縁膜３２は、ゲート電極３０上に設けられる。層間絶縁膜３２は、例えば、シリコン酸化膜で形成される。 The interlayer insulating film 32 is provided on the gate electrode 30. The interlayer insulating film 32 is formed of, for example, a silicon oxide film.

エミッタ電極１３４は、ＳｉＣ層１２上に設けられる。エミッタ電極１３４は、エミッタ領域１１８とｐベースコンタクト領域１２０とに電気的に接続される。エミッタ電極１３４は、ｐベース領域１１６に電位を与えるｐベース電極としても機能する。 The emitter electrode 134 is provided on the SiC layer 12. The emitter electrode 134 is electrically connected to the emitter region 118 and the p-base contact region 120. The emitter electrode 134 also functions as a p-base electrode that applies a potential to the p-base region 116.

エミッタ電極１３４は、導電性の材料である。エミッタ電極１３４は、例えば、金属又は金属シリサイドである。エミッタ電極１３４は、例えば、ニッケルシリサイド層と、ニッケルシリサイド層上のアルミニウム（Ａｌ）層の積層構造を備える。 The emitter electrode 134 is a conductive material. The emitter electrode 134 is, for example, metal or metal silicide. The emitter electrode 134 includes, for example, a laminated structure of a nickel silicide layer and an aluminum (Al) layer on the nickel silicide layer.

コレクタ電極１３６は、ＳｉＣ基板１１０のＳｉＣ層１２と反対側、すなわち、裏面側に設けられる。コレクタ電極１３６は、ＳｉＣ基板１１０と電気的に接続される。 The collector electrode 136 is provided on the side opposite to the SiC layer 12 of the SiC substrate 110, that is, on the back surface side. The collector electrode 136 is electrically connected to the SiC substrate 110.

コレクタ電極１３６は、導電性の材料である。コレクタ電極１３６は、例えば、金属又は金属シリサイドである。コレクタ電極１３６は、例えば、ニッケルシリサイド層と、ニッケルシリサイド層上の金（Ａｕ）層の積層構造を備える。 The collector electrode 136 is a conductive material. The collector electrode 136 is, for example, metal or metal silicide. The collector electrode 136 includes, for example, a laminated structure of a nickel silicide layer and a gold (Au) layer on the nickel silicide layer.

なお、本実施形態において、ｎ型不純物は例えば、Ｎ（窒素）やＰ（リン）が好ましいが、Ａｓ（ヒ素）あるいはＳｂ（アンチモン）等を適用することも可能である。また、ｐ型不純物は例えば、Ａｌ（アルミニウム）が好ましいが、Ｂ（ボロン）、Ｇａ（ガリウム）、Ｉｎ（インジウム）等を適用することも可能である。 In the present embodiment, for example, N (nitrogen) or P (phosphorus) is preferable as the n-type impurity, but As (arsenic), Sb (antimony), or the like can also be applied. Further, for example, Al (aluminum) is preferable as the p-type impurity, but B (boron), Ga (gallium), In (indium) and the like can also be applied.

本実施形態のＩＧＢＴによれば、第１の実施形態のＭＩＳＦＥＴと同様に、ゲート絶縁膜２８中の最大電界とオン抵抗とのトレードオフ関係が改善される。したがって、ゲート絶縁膜２８の耐圧が高くなる。また、チャネル領域でのパンチスルーが抑制され、エミッタ−コレクタ間の耐圧が高くなる。よって、高い耐圧を備えたＩＧＢＴが実現できる。 According to the IGBT of the present embodiment, the trade-off relationship between the maximum electric field and the on-resistance in the gate insulating film 28 is improved as in the MISFET of the first embodiment. Therefore, the withstand voltage of the gate insulating film 28 becomes high. In addition, punch-through in the channel region is suppressed, and the withstand voltage between the emitter and collector becomes high. Therefore, an IGBT having a high withstand voltage can be realized.

なお、第１乃至第５の実施形態において、ｎ型とｐ型とを入れ替えた構造のデバイスも同様に特性向上が実現できる。 In addition, in the first to fifth embodiments, the characteristics of the device having the structure in which the n-type and the p-type are exchanged can be similarly improved.

以上、実施形態では、炭化珪素の結晶構造として４Ｈ−ＳｉＣの場合を例に説明したが、本発明は６Ｈ−ＳｉＣ、３Ｃ−ＳｉＣ等、その他の結晶構造の炭化珪素に適用することも可能である。 In the above embodiment, the case of 4H-SiC as the crystal structure of silicon carbide has been described as an example, but the present invention can be applied to silicon carbide having other crystal structures such as 6H-SiC and 3C-SiC. is there.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。例えば、一実施形態の構成要素を他の実施形態の構成要素と置き換え又は変更してもよい。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or modified with the components of another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

１０ ＳｉＣ基板
１２ ＳｉＣ層
１４ ドリフト領域（第３のＳｉＣ領域）
１５ 境界
１５ａ 第１の領域
１５ｂ 第２の領域
１５ｃ 第３の領域
１５ｄ 第４の領域
１６ ｐウェル領域（第２のＳｉＣ領域）
１８ ソース領域（第１のＳｉＣ領域）
２０ ｐウェルコンタクト領域（第４のＳｉＣ領域）
２８ ゲート絶縁膜
３０ ゲート電極
３４ ソース電極
３６ ドレイン電極
４０ 電界緩和領域（第５のＳｉＣ領域）
５０ トレンチ
５５ トレンチ
１００ ＭＩＳＦＥＴ（半導体装置）
１０１ ＭＩＳＦＥＴ（半導体装置）
１１０ ＳｉＣ基板
１１４ エミッタ領域（第３のＳｉＣ領域）
１１６ ｐベース領域（第２のＳｉＣ領域）
１１８ コレクタ領域（第１のＳｉＣ領域）
１２０ ｐベースコンタクト領域（第４のＳｉＣ領域）
１３４ エミッタ電極
１３６ コレクタ電極
２００ ＭＩＳＦＥＴ（半導体装置）
３００ ＭＩＳＦＥＴ（半導体装置）
４００ ＭＩＳＦＥＴ（半導体装置）
５００ ＩＧＢＴ（半導体装置） 10 SiC substrate 12 SiC layer 14 drift region (third SiC region)
15 Boundary 15a First region 15b Second region 15c Third region 15d Fourth region 16p Well region (second SiC region)
18 Source region (first SiC region)
20 p well contact area (4th SiC area)
28 Gate insulating film 30 Gate electrode
34 Source electrode 36 Drain electrode 40 Electric field relaxation region (fifth SiC region)
50 Trench 55 Trench 100 MISFET (Semiconductor device)
101 MISFET (semiconductor device)
110 SiC substrate 114 Emitter region (third SiC region)
116 p base region (second SiC region)
118 Collector area (first SiC area)
120p base contact area (fourth SiC area)
134 Emitter electrode 136 Collector electrode 200 MISFET (semiconductor device)
300 MISFET (semiconductor device)
400 MISFET (semiconductor device)
500 IGBT (Semiconductor Device)

Claims (19)

ＳｉＣ基板と、
前記ＳｉＣ基板の上に設けられ、側面と底面とを有する第１のトレンチを表面の側に有するＳｉＣ層と、
前記ＳｉＣ層内に設けられた第１導電型の第１のＳｉＣ領域と、
前記ＳｉＣ層内に前記第１のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第２導電型の第２のＳｉＣ領域と、
前記ＳｉＣ層内に前記第２のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第１導電型の第３のＳｉＣ領域と、
前記第１のトレンチの前記側面の上及び前記底面の上に設けられたゲート絶縁膜と、
前記第１のＳｉＣ領域、前記第２のＳｉＣ領域、及び、前記第３のＳｉＣ領域との間に前記ゲート絶縁膜が設けられたゲート電極と、を備え、
前記第２のＳｉＣ領域と前記第３のＳｉＣ領域との境界は、前記第１のトレンチの前記側面の側方に在り、
前記境界は、第１の領域を備え、前記第１の領域は前記ＳｉＣ層の前記表面からの距離が前記第１のトレンチから離れるにしたがって大きくなり、前記第１のトレンチの前記側面から前記第１の領域の前記第１のトレンチの側の端部までの距離が０μｍ以上０．３μｍ以下であり、
前記境界が、前記表面に略垂直な第４の領域を備え、前記第４の領域と前記第１のトレンチとの間に前記第１の領域が設けられ、
前記ゲート電極の前記底面の側の端部を含み前記表面に平行な仮想平面と、前記第２のＳｉＣ領域との間の前記側面に沿った第１の距離は、前記第３のＳｉＣ領域と前記第１のＳｉＣ領域との間の前記側面に沿った第２の距離の２分の１よりも大きい半導体装置。 With a SiC substrate
A SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on the surface side.
The first conductive type first SiC region provided in the SiC layer and
A second conductive type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer,
A first conductive type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer,
A gate insulating film provided on the side surface and the bottom surface of the first trench, and
A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region is provided.
The boundary between the second SiC region and the third SiC region is on the side of the side surface of the first trench.
The boundary comprises a first region, the first region increasing as the distance of the SiC layer from the surface increases from the first trench, from the side surface of the first trench to the first. The distance to the end of the region 1 on the side of the first trench is 0 μm or more and 0.3 μm or less.
The boundary comprises a fourth region that is substantially perpendicular to the surface, and the first region is provided between the fourth region and the first trench.
The first distance along the side surface between the virtual plane including the end on the bottom surface side of the gate electrode and parallel to the surface and the second SiC region is the third SiC region. A semiconductor device that is greater than half the second distance along the side surface to and from the first SiC region. 前記第１の領域が前記第１のトレンチの前記側面に接する請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the first region is in contact with the side surface of the first trench. 前記境界が、前記ＳｉＣ層の前記表面に略平行な第２の領域を備え、前記第１の領域と前記第１のトレンチとの間に前記第２の領域が設けられ、前記第２の領域が前記第１のトレンチの前記側面に接する請求項１又は請求項２記載の半導体装置。 The boundary comprises a second region substantially parallel to the surface of the SiC layer, the second region is provided between the first region and the first trench, and the second region is provided. The semiconductor device according to claim 1 or 2 , wherein is in contact with the side surface of the first trench. 前記第１の領域は前記表面に対して第１の傾斜角を有し、前記第１の傾斜角が１５度以上７０度以下である請求項１乃至請求項３いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3 , wherein the first region has a first inclination angle with respect to the surface, and the first inclination angle is 15 degrees or more and 70 degrees or less. .. 前記第１の領域は前記表面に対して第１の傾斜角を有し、前記第１の傾斜角が１５度以上６０度以下である請求項１乃至請求項３いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3 , wherein the first region has a first inclination angle with respect to the surface, and the first inclination angle is 15 degrees or more and 60 degrees or less. .. 前記境界が、前記表面に略平行な第３の領域を備え、前記第３の領域と前記第１のトレンチとの間に前記第１の領域が設けられる請求項１乃至請求項５いずれか一項記載の半導体装置。 Any one of claims 1 to 5 , wherein the boundary comprises a third region substantially parallel to the surface, and the first region is provided between the third region and the first trench. The semiconductor device according to the item . 前記ゲート絶縁膜が酸化膜である請求項１乃至請求項６いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, wherein the gate insulating film is an oxide film. 前記第１のトレンチの前記底面の上の前記ゲート絶縁膜の膜厚が、前記第１のトレンチの前記側面の上の前記ゲート絶縁膜の膜厚よりも厚い請求項１乃至請求項７いずれか一項記載の半導体装置。 Any of claims 1 to 7 , wherein the film thickness of the gate insulating film on the bottom surface of the first trench is thicker than the film thickness of the gate insulating film on the side surface of the first trench . The semiconductor device according to the first paragraph . 前記ＳｉＣ層内に前記第１のＳｉＣ領域の側方に設けられ、前記第２のＳｉＣ領域よりも第２導電型の不純物の濃度の高い第２導電型の第４のＳｉＣ領域を、更に備える請求項１乃至請求項８いずれか一項記載の半導体装置。 A second conductive type fourth SiC region provided in the SiC layer on the side of the first SiC region and having a higher concentration of second conductive type impurities than the second SiC region is further provided. The semiconductor device according to any one of claims 1 to 8 . 前記ＳｉＣ層内に前記第１のトレンチの前記底面と前記第３のＳｉＣ領域との間に設けられ、前記底面に接する第２導電型の第５のＳｉＣ領域を、更に備える請求項１乃至請求項９いずれか一項記載の半導体装置。 Claims 1 to claim further include a second conductive type fifth SiC region provided in the SiC layer between the bottom surface of the first trench and the third SiC region and in contact with the bottom surface. Item 9. The semiconductor device according to any one of the items . 前記第２のＳｉＣ領域の前記境界の部分の内角が９０度以上である請求項１乃至請求項１０いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 10 , wherein the internal angle of the boundary portion of the second SiC region is 90 degrees or more. 前記境界は角度が９０度以下の屈曲部を備えない請求項１乃至請求項１０いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 10, wherein the boundary does not have a bent portion having an angle of 90 degrees or less. 前記第１導電型がｎ型である請求項１乃至請求項１２いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 12, wherein the first conductive type is n-type. 前記ＳｉＣ基板が第１導電型である請求項１乃至請求項１３いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 13, wherein the SiC substrate is a first conductive type. 前記ＳｉＣ基板が第２導電型である請求項１乃至請求項１３いずれか一項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 13, wherein the SiC substrate is a second conductive type. ＳｉＣ基板と、
前記ＳｉＣ基板の上に設けられ、側面と底面とを有する第１のトレンチを表面の側に有するＳｉＣ層と、
前記ＳｉＣ層内に設けられた第１導電型の第１のＳｉＣ領域と、
前記ＳｉＣ層内に前記第１のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第２導電型の第２のＳｉＣ領域と、
前記ＳｉＣ層内に前記第２のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第１導電型の第３のＳｉＣ領域と、
前記第１のトレンチの前記側面の上及び前記底面の上に設けられたゲート絶縁膜と、
前記第１のＳｉＣ領域、前記第２のＳｉＣ領域、及び、前記第３のＳｉＣ領域との間に前記ゲート絶縁膜が設けられたゲート電極と、を備え、
前記第２のＳｉＣ領域と前記第３のＳｉＣ領域との境界は、前記第１のトレンチの前記側面の側方に在り、
前記境界は、第１の領域を備え、前記第１の領域は前記第１のトレンチから近い第１の点と前記第１のトレンチから遠い第２の点を有し、前記第２の点と前記ＳｉＣ層の前記表面との間の距離が、前記第１の点と前記ＳｉＣ層の前記表面との間の距離よりも大きく、前記第１のトレンチの前記側面から前記第１の領域の前記第１のトレンチの側の端部までの距離が０μｍ以上０．３μｍ以下であり、
前記境界が、前記表面に略垂直な第４の領域を備え、前記第４の領域と前記第１のトレンチとの間に前記第１の領域が設けられ、
前記ゲート電極の前記底面の側の端部を含み前記表面に平行な仮想平面と、前記第２のＳｉＣ領域との間の前記側面に沿った第１の距離は、前記第３のＳｉＣ領域と前記第１のＳｉＣ領域との間の前記側面に沿った第２の距離の２分の１よりも大きい半導体装置。 With a SiC substrate
A SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on the surface side.
The first conductive type first SiC region provided in the SiC layer and
A second conductive type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer,
A first conductive type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer,
A gate insulating film provided on the side surface and the bottom surface of the first trench, and
A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region is provided.
The boundary between the second SiC region and the third SiC region is on the side of the side surface of the first trench.
The boundary comprises a first region, the first region having a first point near the first trench and a second point far from the first trench, and the second point. The distance between the surface of the SiC layer is larger than the distance between the first point and the surface of the SiC layer, and the side surface of the first trench to the surface of the first region. The distance to the end on the side of the first trench is 0 μm or more and 0.3 μm or less.
The boundary comprises a fourth region that is substantially perpendicular to the surface, and the first region is provided between the fourth region and the first trench.
The first distance along the side surface between the virtual plane including the end on the bottom surface side of the gate electrode and parallel to the surface and the second SiC region is the third SiC region. A semiconductor device that is greater than half the second distance along the side surface to and from the first SiC region. ＳｉＣ基板と、
前記ＳｉＣ基板の上に設けられ、側面と底面とを有する第１のトレンチを表面の側に有するＳｉＣ層と、
前記ＳｉＣ層内に設けられた第１導電型の第１のＳｉＣ領域と、
前記ＳｉＣ層内に前記第１のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第２導電型の第２のＳｉＣ領域と、
前記ＳｉＣ層内に前記第２のＳｉＣ領域と前記ＳｉＣ基板との間に設けられた第１導電型の第３のＳｉＣ領域と、
前記第１のトレンチの前記側面の上及び前記底面の上に設けられたゲート絶縁膜と、
前記第１のＳｉＣ領域、前記第２のＳｉＣ領域、及び、前記第３のＳｉＣ領域との間に前記ゲート絶縁膜が設けられたゲート電極と、を備え、
前記第２のＳｉＣ領域と前記第３のＳｉＣ領域との境界は、前記第１のトレンチの前記側面の側方に在り、
前記境界は、第１の領域を備え、前記第１の領域は前記第１のトレンチから近い第１の点と前記第１のトレンチから遠い第２の点を有し、前記第２の点と前記ＳｉＣ基板の裏面との間の距離が、前記第１の点と前記ＳｉＣ基板の前記裏面との間の距離よりも小さく、前記第１のトレンチの前記側面から前記第１の領域の前記第１のトレンチの側の端部までの距離が０μｍ以上０．３μｍ以下であり、
前記境界が、前記表面に略垂直な第４の領域を備え、前記第４の領域と前記第１のトレンチとの間に前記第１の領域が設けられ、
前記ゲート電極の前記底面の側の端部を含み前記表面に平行な仮想平面と、前記第２のＳｉＣ領域との間の前記側面に沿った第１の距離は、前記第３のＳｉＣ領域と前記第１のＳｉＣ領域との間の前記側面に沿った第２の距離の２分の１よりも大きい半導体装置。 With a SiC substrate
A SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on the surface side.
The first conductive type first SiC region provided in the SiC layer and
A second conductive type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer,
A first conductive type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer,
A gate insulating film provided on the side surface and the bottom surface of the first trench, and
A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region is provided.
The boundary between the second SiC region and the third SiC region is on the side of the side surface of the first trench.
The boundary comprises a first region, the first region having a first point near the first trench and a second point far from the first trench, and the second point. The distance between the back surface of the SiC substrate is smaller than the distance between the first point and the back surface of the SiC substrate, and the first side of the first trench to the first region of the first region. The distance to the end on the side of the trench of 1 is 0 μm or more and 0.3 μm or less.
The boundary comprises a fourth region that is substantially perpendicular to the surface, and the first region is provided between the fourth region and the first trench.
The first distance along the side surface between the virtual plane including the end on the bottom surface side of the gate electrode and parallel to the surface and the second SiC region is the third SiC region. A semiconductor device that is greater than half the second distance along the side surface to and from the first SiC region. 前記第２の距離は０．１μｍ以上０．６μｍ以下である請求項１乃至請求項１７いずれか一項記載の記載の半導体装置。 The semiconductor device according to any one of claims 1 to 17, wherein the second distance is 0.1 μm or more and 0.6 μm or less. 前記ＳｉＣ層の前記表面の側に設けられた第１の電極と、
前記第１の電極との間に前記ＳｉＣ層と前記ＳｉＣ基板とが設けられた第２の電極と、
前記ＳｉＣ層内に前記第１のＳｉＣ領域の側方に設けられ、前記第２のＳｉＣ領域よりも第２導電型の不純物の濃度の高い第２導電型の第４のＳｉＣ領域を、更に備え、
前記第２の電極と前記第１のトレンチとの間の最小距離が、前記第２の電極と前記第２のＳｉＣ領域との間の最小距離よりも大きく、
前記第１の電極と、前記第２のＳｉＣ領域と前記第４のＳｉＣ領域との境界との間の前記表面に垂直な方向の第３の距離が、前記第２のＳｉＣ領域と前記第４のＳｉＣ領域との境界と、前記第２のＳｉＣ領域と前記第３のＳｉＣ領域との境界との間の前記表面に垂直な方向の第４の距離よりも小さい請求項１、請求項１６又は請求項１７記載の半導体装置。 A first electrode provided on the surface side of the SiC layer and
A second electrode provided with the SiC layer and the SiC substrate between the first electrode and
A second conductive type fourth SiC region provided in the SiC layer on the side of the first SiC region and having a higher concentration of second conductive type impurities than the second SiC region is further provided. ,
The minimum distance between the second electrode and the first trench is greater than the minimum distance between the second electrode and the second SiC region.
The third distance in the direction perpendicular to the surface between the first electrode and the boundary between the second SiC region and the fourth SiC region is the second SiC region and the fourth. 1, 16 or 16 or less than the fourth distance in the direction perpendicular to the surface between the boundary with the SiC region and the boundary between the second SiC region and the third SiC region. The semiconductor device according to claim 17.
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